projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd/common: get ME/PFP/CE firmware feature versions as well
[mesa.git] / src / gallium / drivers / radeon / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112 unsigned sel = EOP_DATA_SEL(data_sel);
113
114 /* Wait for write confirmation before writing data, but don't send
115 * an interrupt. */
116 if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD)
117 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
118
119 if (ctx->chip_class >= GFX9) {
120 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
121 * counters) must immediately precede every timestamp event to
122 * prevent a GPU hang on GFX9.
123 *
124 * Occlusion queries don't need to do it here, because they
125 * always do ZPASS_DONE before the timestamp.
126 */
127 if (ctx->chip_class == GFX9 &&
128 query_type != PIPE_QUERY_OCCLUSION_COUNTER &&
129 query_type != PIPE_QUERY_OCCLUSION_PREDICATE) {
130 struct r600_resource *scratch = ctx->eop_bug_scratch;
131
132 assert(16 * ctx->screen->info.num_render_backends <=
133 scratch->b.b.width0);
134 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
135 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
136 radeon_emit(cs, scratch->gpu_address);
137 radeon_emit(cs, scratch->gpu_address >> 32);
138
139 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
140 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
141 }
142
143 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
144 radeon_emit(cs, op);
145 radeon_emit(cs, sel);
146 radeon_emit(cs, va); /* address lo */
147 radeon_emit(cs, va >> 32); /* address hi */
148 radeon_emit(cs, new_fence); /* immediate data lo */
149 radeon_emit(cs, 0); /* immediate data hi */
150 radeon_emit(cs, 0); /* unused */
151 } else {
152 if (ctx->chip_class == CIK ||
153 ctx->chip_class == VI) {
154 struct r600_resource *scratch = ctx->eop_bug_scratch;
155 uint64_t va = scratch->gpu_address;
156
157 /* Two EOP events are required to make all engines go idle
158 * (and optional cache flushes executed) before the timestamp
159 * is written.
160 */
161 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
162 radeon_emit(cs, op);
163 radeon_emit(cs, va);
164 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
165 radeon_emit(cs, 0); /* immediate data */
166 radeon_emit(cs, 0); /* unused */
167
168 radeon_add_to_buffer_list(ctx, &ctx->gfx, scratch,
169 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
170 }
171
172 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
173 radeon_emit(cs, op);
174 radeon_emit(cs, va);
175 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
176 radeon_emit(cs, new_fence); /* immediate data */
177 radeon_emit(cs, 0); /* unused */
178 }
179
180 if (buf)
181 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
182 RADEON_PRIO_QUERY);
183 }
184
185 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
186 {
187 unsigned dwords = 6;
188
189 if (screen->chip_class == CIK ||
190 screen->chip_class == VI)
191 dwords *= 2;
192
193 if (!screen->info.has_virtual_memory)
194 dwords += 2;
195
196 return dwords;
197 }
198
199 void r600_gfx_wait_fence(struct r600_common_context *ctx,
200 uint64_t va, uint32_t ref, uint32_t mask)
201 {
202 struct radeon_winsys_cs *cs = ctx->gfx.cs;
203
204 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
205 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
206 radeon_emit(cs, va);
207 radeon_emit(cs, va >> 32);
208 radeon_emit(cs, ref); /* reference value */
209 radeon_emit(cs, mask); /* mask */
210 radeon_emit(cs, 4); /* poll interval */
211 }
212
213 void r600_draw_rectangle(struct blitter_context *blitter,
214 int x1, int y1, int x2, int y2,
215 float depth, unsigned num_instances,
216 enum blitter_attrib_type type,
217 const union blitter_attrib *attrib)
218 {
219 struct r600_common_context *rctx =
220 (struct r600_common_context*)util_blitter_get_pipe(blitter);
221 struct pipe_viewport_state viewport;
222 struct pipe_resource *buf = NULL;
223 unsigned offset = 0;
224 float *vb;
225
226 /* Some operations (like color resolve on r6xx) don't work
227 * with the conventional primitive types.
228 * One that works is PT_RECTLIST, which we use here. */
229
230 /* setup viewport */
231 viewport.scale[0] = 1.0f;
232 viewport.scale[1] = 1.0f;
233 viewport.scale[2] = 1.0f;
234 viewport.translate[0] = 0.0f;
235 viewport.translate[1] = 0.0f;
236 viewport.translate[2] = 0.0f;
237 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
238
239 /* Upload vertices. The hw rectangle has only 3 vertices,
240 * The 4th one is derived from the first 3.
241 * The vertex specification should match u_blitter's vertex element state. */
242 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
243 rctx->screen->info.tcc_cache_line_size,
244 &offset, &buf, (void**)&vb);
245 if (!buf)
246 return;
247
248 vb[0] = x1;
249 vb[1] = y1;
250 vb[2] = depth;
251 vb[3] = 1;
252
253 vb[8] = x1;
254 vb[9] = y2;
255 vb[10] = depth;
256 vb[11] = 1;
257
258 vb[16] = x2;
259 vb[17] = y1;
260 vb[18] = depth;
261 vb[19] = 1;
262
263 switch (type) {
264 case UTIL_BLITTER_ATTRIB_COLOR:
265 memcpy(vb+4, attrib->color, sizeof(float)*4);
266 memcpy(vb+12, attrib->color, sizeof(float)*4);
267 memcpy(vb+20, attrib->color, sizeof(float)*4);
268 break;
269 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
270 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
271 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
272 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
273 /* fall through */
274 vb[4] = attrib->texcoord.x1;
275 vb[5] = attrib->texcoord.y1;
276 vb[12] = attrib->texcoord.x1;
277 vb[13] = attrib->texcoord.y2;
278 vb[20] = attrib->texcoord.x2;
279 vb[21] = attrib->texcoord.y1;
280 break;
281 default:; /* Nothing to do. */
282 }
283
284 /* draw */
285 struct pipe_vertex_buffer vbuffer = {};
286 vbuffer.buffer.resource = buf;
287 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
288 vbuffer.buffer_offset = offset;
289
290 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
291 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
292 0, num_instances);
293 pipe_resource_reference(&buf, NULL);
294 }
295
296 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
297 {
298 struct radeon_winsys_cs *cs = rctx->dma.cs;
299
300 /* NOP waits for idle on Evergreen and later. */
301 if (rctx->chip_class >= CIK)
302 radeon_emit(cs, 0x00000000); /* NOP */
303 else if (rctx->chip_class >= EVERGREEN)
304 radeon_emit(cs, 0xf0000000); /* NOP */
305 else {
306 /* TODO: R600-R700 should use the FENCE packet.
307 * CS checker support is required. */
308 }
309 }
310
311 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
312 struct r600_resource *dst, struct r600_resource *src)
313 {
314 uint64_t vram = ctx->dma.cs->used_vram;
315 uint64_t gtt = ctx->dma.cs->used_gart;
316
317 if (dst) {
318 vram += dst->vram_usage;
319 gtt += dst->gart_usage;
320 }
321 if (src) {
322 vram += src->vram_usage;
323 gtt += src->gart_usage;
324 }
325
326 /* Flush the GFX IB if DMA depends on it. */
327 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
328 ((dst &&
329 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
330 RADEON_USAGE_READWRITE)) ||
331 (src &&
332 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
333 RADEON_USAGE_WRITE))))
334 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
335
336 /* Flush if there's not enough space, or if the memory usage per IB
337 * is too large.
338 *
339 * IBs using too little memory are limited by the IB submission overhead.
340 * IBs using too much memory are limited by the kernel/TTM overhead.
341 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
342 *
343 * This heuristic makes sure that DMA requests are executed
344 * very soon after the call is made and lowers memory usage.
345 * It improves texture upload performance by keeping the DMA
346 * engine busy while uploads are being submitted.
347 */
348 num_dw++; /* for emit_wait_idle below */
349 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
350 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
351 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
352 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
353 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
354 }
355
356 /* Wait for idle if either buffer has been used in the IB before to
357 * prevent read-after-write hazards.
358 */
359 if ((dst &&
360 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
361 RADEON_USAGE_READWRITE)) ||
362 (src &&
363 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
364 RADEON_USAGE_WRITE)))
365 r600_dma_emit_wait_idle(ctx);
366
367 /* If GPUVM is not supported, the CS checker needs 2 entries
368 * in the buffer list per packet, which has to be done manually.
369 */
370 if (ctx->screen->info.has_virtual_memory) {
371 if (dst)
372 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
373 RADEON_USAGE_WRITE,
374 RADEON_PRIO_SDMA_BUFFER);
375 if (src)
376 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
377 RADEON_USAGE_READ,
378 RADEON_PRIO_SDMA_BUFFER);
379 }
380
381 /* this function is called before all DMA calls, so increment this. */
382 ctx->num_dma_calls++;
383 }
384
385 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
386 {
387 }
388
389 void r600_preflush_suspend_features(struct r600_common_context *ctx)
390 {
391 /* suspend queries */
392 if (!LIST_IS_EMPTY(&ctx->active_queries))
393 r600_suspend_queries(ctx);
394
395 ctx->streamout.suspended = false;
396 if (ctx->streamout.begin_emitted) {
397 r600_emit_streamout_end(ctx);
398 ctx->streamout.suspended = true;
399 }
400 }
401
402 void r600_postflush_resume_features(struct r600_common_context *ctx)
403 {
404 if (ctx->streamout.suspended) {
405 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
406 r600_streamout_buffers_dirty(ctx);
407 }
408
409 /* resume queries */
410 if (!LIST_IS_EMPTY(&ctx->active_queries))
411 r600_resume_queries(ctx);
412 }
413
414 static void r600_add_fence_dependency(struct r600_common_context *rctx,
415 struct pipe_fence_handle *fence)
416 {
417 struct radeon_winsys *ws = rctx->ws;
418
419 if (rctx->dma.cs)
420 ws->cs_add_fence_dependency(rctx->dma.cs, fence);
421 ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
422 }
423
424 static void r600_fence_server_sync(struct pipe_context *ctx,
425 struct pipe_fence_handle *fence)
426 {
427 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
428 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
429
430 /* Only amdgpu needs to handle fence dependencies (for fence imports).
431 * radeon synchronizes all rings by default and will not implement
432 * fence imports.
433 */
434 if (rctx->screen->info.drm_major == 2)
435 return;
436
437 /* Only imported fences need to be handled by fence_server_sync,
438 * because the winsys handles synchronizations automatically for BOs
439 * within the process.
440 *
441 * Simply skip unflushed fences here, and the winsys will drop no-op
442 * dependencies (i.e. dependencies within the same ring).
443 */
444 if (rfence->gfx_unflushed.ctx)
445 return;
446
447 /* All unflushed commands will not start execution before
448 * this fence dependency is signalled.
449 *
450 * Should we flush the context to allow more GPU parallelism?
451 */
452 if (rfence->sdma)
453 r600_add_fence_dependency(rctx, rfence->sdma);
454 if (rfence->gfx)
455 r600_add_fence_dependency(rctx, rfence->gfx);
456 }
457
458 static void r600_flush_from_st(struct pipe_context *ctx,
459 struct pipe_fence_handle **fence,
460 unsigned flags)
461 {
462 struct pipe_screen *screen = ctx->screen;
463 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
464 struct radeon_winsys *ws = rctx->ws;
465 struct pipe_fence_handle *gfx_fence = NULL;
466 struct pipe_fence_handle *sdma_fence = NULL;
467 bool deferred_fence = false;
468 unsigned rflags = RADEON_FLUSH_ASYNC;
469
470 if (flags & PIPE_FLUSH_END_OF_FRAME)
471 rflags |= RADEON_FLUSH_END_OF_FRAME;
472
473 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
474 if (rctx->dma.cs)
475 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
476
477 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
478 if (fence)
479 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
480 if (!(flags & PIPE_FLUSH_DEFERRED))
481 ws->cs_sync_flush(rctx->gfx.cs);
482 } else {
483 /* Instead of flushing, create a deferred fence. Constraints:
484 * - The state tracker must allow a deferred flush.
485 * - The state tracker must request a fence.
486 * Thread safety in fence_finish must be ensured by the state tracker.
487 */
488 if (flags & PIPE_FLUSH_DEFERRED && fence) {
489 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
490 deferred_fence = true;
491 } else {
492 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
493 }
494 }
495
496 /* Both engines can signal out of order, so we need to keep both fences. */
497 if (fence) {
498 struct r600_multi_fence *multi_fence =
499 CALLOC_STRUCT(r600_multi_fence);
500 if (!multi_fence) {
501 ws->fence_reference(&sdma_fence, NULL);
502 ws->fence_reference(&gfx_fence, NULL);
503 goto finish;
504 }
505
506 multi_fence->reference.count = 1;
507 /* If both fences are NULL, fence_finish will always return true. */
508 multi_fence->gfx = gfx_fence;
509 multi_fence->sdma = sdma_fence;
510
511 if (deferred_fence) {
512 multi_fence->gfx_unflushed.ctx = rctx;
513 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
514 }
515
516 screen->fence_reference(screen, fence, NULL);
517 *fence = (struct pipe_fence_handle*)multi_fence;
518 }
519 finish:
520 if (!(flags & PIPE_FLUSH_DEFERRED)) {
521 if (rctx->dma.cs)
522 ws->cs_sync_flush(rctx->dma.cs);
523 ws->cs_sync_flush(rctx->gfx.cs);
524 }
525 }
526
527 static void r600_flush_dma_ring(void *ctx, unsigned flags,
528 struct pipe_fence_handle **fence)
529 {
530 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
531 struct radeon_winsys_cs *cs = rctx->dma.cs;
532 struct radeon_saved_cs saved;
533 bool check_vm =
534 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
535 rctx->check_vm_faults;
536
537 if (!radeon_emitted(cs, 0)) {
538 if (fence)
539 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
540 return;
541 }
542
543 if (check_vm)
544 radeon_save_cs(rctx->ws, cs, &saved, true);
545
546 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
547 if (fence)
548 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
549
550 if (check_vm) {
551 /* Use conservative timeout 800ms, after which we won't wait any
552 * longer and assume the GPU is hung.
553 */
554 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
555
556 rctx->check_vm_faults(rctx, &saved, RING_DMA);
557 radeon_clear_saved_cs(&saved);
558 }
559 }
560
561 /**
562 * Store a linearized copy of all chunks of \p cs together with the buffer
563 * list in \p saved.
564 */
565 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
566 struct radeon_saved_cs *saved, bool get_buffer_list)
567 {
568 uint32_t *buf;
569 unsigned i;
570
571 /* Save the IB chunks. */
572 saved->num_dw = cs->prev_dw + cs->current.cdw;
573 saved->ib = MALLOC(4 * saved->num_dw);
574 if (!saved->ib)
575 goto oom;
576
577 buf = saved->ib;
578 for (i = 0; i < cs->num_prev; ++i) {
579 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
580 buf += cs->prev[i].cdw;
581 }
582 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
583
584 if (!get_buffer_list)
585 return;
586
587 /* Save the buffer list. */
588 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
589 saved->bo_list = CALLOC(saved->bo_count,
590 sizeof(saved->bo_list[0]));
591 if (!saved->bo_list) {
592 FREE(saved->ib);
593 goto oom;
594 }
595 ws->cs_get_buffer_list(cs, saved->bo_list);
596
597 return;
598
599 oom:
600 fprintf(stderr, "%s: out of memory\n", __func__);
601 memset(saved, 0, sizeof(*saved));
602 }
603
604 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
605 {
606 FREE(saved->ib);
607 FREE(saved->bo_list);
608
609 memset(saved, 0, sizeof(*saved));
610 }
611
612 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
613 {
614 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
615 unsigned latest = rctx->ws->query_value(rctx->ws,
616 RADEON_GPU_RESET_COUNTER);
617
618 if (rctx->gpu_reset_counter == latest)
619 return PIPE_NO_RESET;
620
621 rctx->gpu_reset_counter = latest;
622 return PIPE_UNKNOWN_CONTEXT_RESET;
623 }
624
625 static void r600_set_debug_callback(struct pipe_context *ctx,
626 const struct pipe_debug_callback *cb)
627 {
628 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
629
630 if (cb)
631 rctx->debug = *cb;
632 else
633 memset(&rctx->debug, 0, sizeof(rctx->debug));
634 }
635
636 static void r600_set_device_reset_callback(struct pipe_context *ctx,
637 const struct pipe_device_reset_callback *cb)
638 {
639 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
640
641 if (cb)
642 rctx->device_reset_callback = *cb;
643 else
644 memset(&rctx->device_reset_callback, 0,
645 sizeof(rctx->device_reset_callback));
646 }
647
648 bool r600_check_device_reset(struct r600_common_context *rctx)
649 {
650 enum pipe_reset_status status;
651
652 if (!rctx->device_reset_callback.reset)
653 return false;
654
655 if (!rctx->b.get_device_reset_status)
656 return false;
657
658 status = rctx->b.get_device_reset_status(&rctx->b);
659 if (status == PIPE_NO_RESET)
660 return false;
661
662 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
663 return true;
664 }
665
666 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
667 struct pipe_resource *dst,
668 uint64_t offset, uint64_t size,
669 unsigned value)
670 {
671 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
672
673 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
674 }
675
676 static bool r600_resource_commit(struct pipe_context *pctx,
677 struct pipe_resource *resource,
678 unsigned level, struct pipe_box *box,
679 bool commit)
680 {
681 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
682 struct r600_resource *res = r600_resource(resource);
683
684 /*
685 * Since buffer commitment changes cannot be pipelined, we need to
686 * (a) flush any pending commands that refer to the buffer we're about
687 * to change, and
688 * (b) wait for threaded submit to finish, including those that were
689 * triggered by some other, earlier operation.
690 */
691 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
692 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
693 res->buf, RADEON_USAGE_READWRITE)) {
694 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
695 }
696 if (radeon_emitted(ctx->dma.cs, 0) &&
697 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
698 res->buf, RADEON_USAGE_READWRITE)) {
699 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
700 }
701
702 ctx->ws->cs_sync_flush(ctx->dma.cs);
703 ctx->ws->cs_sync_flush(ctx->gfx.cs);
704
705 assert(resource->target == PIPE_BUFFER);
706
707 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
708 }
709
710 bool r600_common_context_init(struct r600_common_context *rctx,
711 struct r600_common_screen *rscreen,
712 unsigned context_flags)
713 {
714 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
715 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
716
717 rctx->screen = rscreen;
718 rctx->ws = rscreen->ws;
719 rctx->family = rscreen->family;
720 rctx->chip_class = rscreen->chip_class;
721
722 rctx->b.invalidate_resource = r600_invalidate_resource;
723 rctx->b.resource_commit = r600_resource_commit;
724 rctx->b.transfer_map = u_transfer_map_vtbl;
725 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
726 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
727 rctx->b.texture_subdata = u_default_texture_subdata;
728 rctx->b.memory_barrier = r600_memory_barrier;
729 rctx->b.flush = r600_flush_from_st;
730 rctx->b.set_debug_callback = r600_set_debug_callback;
731 rctx->b.fence_server_sync = r600_fence_server_sync;
732 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
733
734 /* evergreen_compute.c has a special codepath for global buffers.
735 * Everything else can use the direct path.
736 */
737 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
738 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
739 rctx->b.buffer_subdata = u_default_buffer_subdata;
740 else
741 rctx->b.buffer_subdata = r600_buffer_subdata;
742
743 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
744 rctx->b.get_device_reset_status = r600_get_reset_status;
745 rctx->gpu_reset_counter =
746 rctx->ws->query_value(rctx->ws,
747 RADEON_GPU_RESET_COUNTER);
748 }
749
750 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
751
752 r600_init_context_texture_functions(rctx);
753 r600_init_viewport_functions(rctx);
754 r600_streamout_init(rctx);
755 r600_query_init(rctx);
756 cayman_init_msaa(&rctx->b);
757
758 if (rctx->chip_class == CIK ||
759 rctx->chip_class == VI ||
760 rctx->chip_class == GFX9) {
761 rctx->eop_bug_scratch = (struct r600_resource*)
762 pipe_buffer_create(&rscreen->b, 0, PIPE_USAGE_DEFAULT,
763 16 * rscreen->info.num_render_backends);
764 if (!rctx->eop_bug_scratch)
765 return false;
766 }
767
768 rctx->allocator_zeroed_memory =
769 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
770 0, PIPE_USAGE_DEFAULT, 0, true);
771 if (!rctx->allocator_zeroed_memory)
772 return false;
773
774 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
775 0, PIPE_USAGE_STREAM);
776 if (!rctx->b.stream_uploader)
777 return false;
778
779 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
780 0, PIPE_USAGE_DEFAULT);
781 if (!rctx->b.const_uploader)
782 return false;
783
784 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
785 if (!rctx->ctx)
786 return false;
787
788 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
789 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
790 r600_flush_dma_ring,
791 rctx);
792 rctx->dma.flush = r600_flush_dma_ring;
793 }
794
795 return true;
796 }
797
798 void r600_common_context_cleanup(struct r600_common_context *rctx)
799 {
800 unsigned i,j;
801
802 /* Release DCC stats. */
803 for (i = 0; i < ARRAY_SIZE(rctx->dcc_stats); i++) {
804 assert(!rctx->dcc_stats[i].query_active);
805
806 for (j = 0; j < ARRAY_SIZE(rctx->dcc_stats[i].ps_stats); j++)
807 if (rctx->dcc_stats[i].ps_stats[j])
808 rctx->b.destroy_query(&rctx->b,
809 rctx->dcc_stats[i].ps_stats[j]);
810
811 r600_texture_reference(&rctx->dcc_stats[i].tex, NULL);
812 }
813
814 if (rctx->query_result_shader)
815 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
816
817 if (rctx->gfx.cs)
818 rctx->ws->cs_destroy(rctx->gfx.cs);
819 if (rctx->dma.cs)
820 rctx->ws->cs_destroy(rctx->dma.cs);
821 if (rctx->ctx)
822 rctx->ws->ctx_destroy(rctx->ctx);
823
824 if (rctx->b.stream_uploader)
825 u_upload_destroy(rctx->b.stream_uploader);
826 if (rctx->b.const_uploader)
827 u_upload_destroy(rctx->b.const_uploader);
828
829 slab_destroy_child(&rctx->pool_transfers);
830 slab_destroy_child(&rctx->pool_transfers_unsync);
831
832 if (rctx->allocator_zeroed_memory) {
833 u_suballocator_destroy(rctx->allocator_zeroed_memory);
834 }
835 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
836 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
837 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
838 }
839
840 /*
841 * pipe_screen
842 */
843
844 static const struct debug_named_value common_debug_options[] = {
845 /* logging */
846 { "tex", DBG_TEX, "Print texture info" },
847 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
848 { "compute", DBG_COMPUTE, "Print compute info" },
849 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
850 { "info", DBG_INFO, "Print driver information" },
851
852 /* shaders */
853 { "fs", DBG_FS, "Print fetch shaders" },
854 { "vs", DBG_VS, "Print vertex shaders" },
855 { "gs", DBG_GS, "Print geometry shaders" },
856 { "ps", DBG_PS, "Print pixel shaders" },
857 { "cs", DBG_CS, "Print compute shaders" },
858 { "tcs", DBG_TCS, "Print tessellation control shaders" },
859 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
860 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
861 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
862 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
863 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
864 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
865 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
866
867 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
868 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
869 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
870 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
871
872 /* features */
873 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
874 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
875 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
876 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
877 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
878 { "notiling", DBG_NO_TILING, "Disable tiling" },
879 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
880 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
881 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
882 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
883 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
884 { "nodcc", DBG_NO_DCC, "Disable DCC." },
885 { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
886 { "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
887 { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
888 { "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
889 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
890 { "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main framebuffer" },
891 { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
892 { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
893
894 DEBUG_NAMED_VALUE_END /* must be last */
895 };
896
897 static const char* r600_get_vendor(struct pipe_screen* pscreen)
898 {
899 return "X.Org";
900 }
901
902 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
903 {
904 return "AMD";
905 }
906
907 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
908 {
909 if (!ws->get_chip_name)
910 return NULL;
911 return ws->get_chip_name(ws);
912 }
913
914 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
915 {
916 switch (rscreen->info.family) {
917 case CHIP_R600: return "AMD R600";
918 case CHIP_RV610: return "AMD RV610";
919 case CHIP_RV630: return "AMD RV630";
920 case CHIP_RV670: return "AMD RV670";
921 case CHIP_RV620: return "AMD RV620";
922 case CHIP_RV635: return "AMD RV635";
923 case CHIP_RS780: return "AMD RS780";
924 case CHIP_RS880: return "AMD RS880";
925 case CHIP_RV770: return "AMD RV770";
926 case CHIP_RV730: return "AMD RV730";
927 case CHIP_RV710: return "AMD RV710";
928 case CHIP_RV740: return "AMD RV740";
929 case CHIP_CEDAR: return "AMD CEDAR";
930 case CHIP_REDWOOD: return "AMD REDWOOD";
931 case CHIP_JUNIPER: return "AMD JUNIPER";
932 case CHIP_CYPRESS: return "AMD CYPRESS";
933 case CHIP_HEMLOCK: return "AMD HEMLOCK";
934 case CHIP_PALM: return "AMD PALM";
935 case CHIP_SUMO: return "AMD SUMO";
936 case CHIP_SUMO2: return "AMD SUMO2";
937 case CHIP_BARTS: return "AMD BARTS";
938 case CHIP_TURKS: return "AMD TURKS";
939 case CHIP_CAICOS: return "AMD CAICOS";
940 case CHIP_CAYMAN: return "AMD CAYMAN";
941 case CHIP_ARUBA: return "AMD ARUBA";
942 case CHIP_TAHITI: return "AMD TAHITI";
943 case CHIP_PITCAIRN: return "AMD PITCAIRN";
944 case CHIP_VERDE: return "AMD CAPE VERDE";
945 case CHIP_OLAND: return "AMD OLAND";
946 case CHIP_HAINAN: return "AMD HAINAN";
947 case CHIP_BONAIRE: return "AMD BONAIRE";
948 case CHIP_KAVERI: return "AMD KAVERI";
949 case CHIP_KABINI: return "AMD KABINI";
950 case CHIP_HAWAII: return "AMD HAWAII";
951 case CHIP_MULLINS: return "AMD MULLINS";
952 case CHIP_TONGA: return "AMD TONGA";
953 case CHIP_ICELAND: return "AMD ICELAND";
954 case CHIP_CARRIZO: return "AMD CARRIZO";
955 case CHIP_FIJI: return "AMD FIJI";
956 case CHIP_POLARIS10: return "AMD POLARIS10";
957 case CHIP_POLARIS11: return "AMD POLARIS11";
958 case CHIP_POLARIS12: return "AMD POLARIS12";
959 case CHIP_STONEY: return "AMD STONEY";
960 case CHIP_VEGA10: return "AMD VEGA10";
961 case CHIP_RAVEN: return "AMD RAVEN";
962 default: return "AMD unknown";
963 }
964 }
965
966 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
967 {
968 /* Don't use the cache if shader dumping is enabled. */
969 if (rscreen->debug_flags & DBG_ALL_SHADERS)
970 return;
971
972 uint32_t mesa_timestamp;
973 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
974 &mesa_timestamp)) {
975 char *timestamp_str;
976 int res = -1;
977 if (rscreen->chip_class < SI) {
978 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
979 }
980 #if HAVE_LLVM
981 else {
982 uint32_t llvm_timestamp;
983 if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
984 &llvm_timestamp)) {
985 res = asprintf(&timestamp_str, "%u_%u",
986 mesa_timestamp, llvm_timestamp);
987 }
988 }
989 #endif
990 if (res != -1) {
991 /* These flags affect shader compilation. */
992 uint64_t shader_debug_flags =
993 rscreen->debug_flags &
994 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
995 DBG_SI_SCHED |
996 DBG_UNSAFE_MATH);
997
998 rscreen->disk_shader_cache =
999 disk_cache_create(r600_get_family_name(rscreen),
1000 timestamp_str,
1001 shader_debug_flags);
1002 free(timestamp_str);
1003 }
1004 }
1005 }
1006
1007 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
1008 {
1009 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
1010 return rscreen->disk_shader_cache;
1011 }
1012
1013 static const char* r600_get_name(struct pipe_screen* pscreen)
1014 {
1015 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
1016
1017 return rscreen->renderer_string;
1018 }
1019
1020 static float r600_get_paramf(struct pipe_screen* pscreen,
1021 enum pipe_capf param)
1022 {
1023 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
1024
1025 switch (param) {
1026 case PIPE_CAPF_MAX_LINE_WIDTH:
1027 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
1028 case PIPE_CAPF_MAX_POINT_WIDTH:
1029 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
1030 if (rscreen->family >= CHIP_CEDAR)
1031 return 16384.0f;
1032 else
1033 return 8192.0f;
1034 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
1035 return 16.0f;
1036 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
1037 return 16.0f;
1038 case PIPE_CAPF_GUARD_BAND_LEFT:
1039 case PIPE_CAPF_GUARD_BAND_TOP:
1040 case PIPE_CAPF_GUARD_BAND_RIGHT:
1041 case PIPE_CAPF_GUARD_BAND_BOTTOM:
1042 return 0.0f;
1043 }
1044 return 0.0f;
1045 }
1046
1047 static int r600_get_video_param(struct pipe_screen *screen,
1048 enum pipe_video_profile profile,
1049 enum pipe_video_entrypoint entrypoint,
1050 enum pipe_video_cap param)
1051 {
1052 switch (param) {
1053 case PIPE_VIDEO_CAP_SUPPORTED:
1054 return vl_profile_supported(screen, profile, entrypoint);
1055 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
1056 return 1;
1057 case PIPE_VIDEO_CAP_MAX_WIDTH:
1058 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1059 return vl_video_buffer_max_size(screen);
1060 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1061 return PIPE_FORMAT_NV12;
1062 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1063 return false;
1064 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1065 return false;
1066 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1067 return true;
1068 case PIPE_VIDEO_CAP_MAX_LEVEL:
1069 return vl_level_supported(screen, profile);
1070 default:
1071 return 0;
1072 }
1073 }
1074
1075 const char *r600_get_llvm_processor_name(enum radeon_family family)
1076 {
1077 switch (family) {
1078 case CHIP_R600:
1079 case CHIP_RV630:
1080 case CHIP_RV635:
1081 case CHIP_RV670:
1082 return "r600";
1083 case CHIP_RV610:
1084 case CHIP_RV620:
1085 case CHIP_RS780:
1086 case CHIP_RS880:
1087 return "rs880";
1088 case CHIP_RV710:
1089 return "rv710";
1090 case CHIP_RV730:
1091 return "rv730";
1092 case CHIP_RV740:
1093 case CHIP_RV770:
1094 return "rv770";
1095 case CHIP_PALM:
1096 case CHIP_CEDAR:
1097 return "cedar";
1098 case CHIP_SUMO:
1099 case CHIP_SUMO2:
1100 return "sumo";
1101 case CHIP_REDWOOD:
1102 return "redwood";
1103 case CHIP_JUNIPER:
1104 return "juniper";
1105 case CHIP_HEMLOCK:
1106 case CHIP_CYPRESS:
1107 return "cypress";
1108 case CHIP_BARTS:
1109 return "barts";
1110 case CHIP_TURKS:
1111 return "turks";
1112 case CHIP_CAICOS:
1113 return "caicos";
1114 case CHIP_CAYMAN:
1115 case CHIP_ARUBA:
1116 return "cayman";
1117
1118 case CHIP_TAHITI: return "tahiti";
1119 case CHIP_PITCAIRN: return "pitcairn";
1120 case CHIP_VERDE: return "verde";
1121 case CHIP_OLAND: return "oland";
1122 case CHIP_HAINAN: return "hainan";
1123 case CHIP_BONAIRE: return "bonaire";
1124 case CHIP_KABINI: return "kabini";
1125 case CHIP_KAVERI: return "kaveri";
1126 case CHIP_HAWAII: return "hawaii";
1127 case CHIP_MULLINS:
1128 return "mullins";
1129 case CHIP_TONGA: return "tonga";
1130 case CHIP_ICELAND: return "iceland";
1131 case CHIP_CARRIZO: return "carrizo";
1132 case CHIP_FIJI:
1133 return "fiji";
1134 case CHIP_STONEY:
1135 return "stoney";
1136 case CHIP_POLARIS10:
1137 return "polaris10";
1138 case CHIP_POLARIS11:
1139 case CHIP_POLARIS12: /* same as polaris11 */
1140 return "polaris11";
1141 case CHIP_VEGA10:
1142 case CHIP_RAVEN:
1143 return "gfx900";
1144 default:
1145 return "";
1146 }
1147 }
1148
1149 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
1150 enum pipe_shader_ir ir_type)
1151 {
1152 if (ir_type != PIPE_SHADER_IR_TGSI)
1153 return 256;
1154
1155 /* Only 16 waves per thread-group on gfx9. */
1156 if (screen->chip_class >= GFX9)
1157 return 1024;
1158
1159 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
1160 * round number.
1161 */
1162 if (screen->chip_class >= SI)
1163 return 2048;
1164
1165 return 256;
1166 }
1167
1168 static int r600_get_compute_param(struct pipe_screen *screen,
1169 enum pipe_shader_ir ir_type,
1170 enum pipe_compute_cap param,
1171 void *ret)
1172 {
1173 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1174
1175 //TODO: select these params by asic
1176 switch (param) {
1177 case PIPE_COMPUTE_CAP_IR_TARGET: {
1178 const char *gpu;
1179 const char *triple;
1180 if (rscreen->family <= CHIP_ARUBA) {
1181 triple = "r600--";
1182 } else {
1183 if (HAVE_LLVM < 0x0400) {
1184 triple = "amdgcn--";
1185 } else {
1186 triple = "amdgcn-mesa-mesa3d";
1187 }
1188 }
1189 switch(rscreen->family) {
1190 /* Clang < 3.6 is missing Hainan in its list of
1191 * GPUs, so we need to use the name of a similar GPU.
1192 */
1193 default:
1194 gpu = r600_get_llvm_processor_name(rscreen->family);
1195 break;
1196 }
1197 if (ret) {
1198 sprintf(ret, "%s-%s", gpu, triple);
1199 }
1200 /* +2 for dash and terminating NIL byte */
1201 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1202 }
1203 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1204 if (ret) {
1205 uint64_t *grid_dimension = ret;
1206 grid_dimension[0] = 3;
1207 }
1208 return 1 * sizeof(uint64_t);
1209
1210 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1211 if (ret) {
1212 uint64_t *grid_size = ret;
1213 grid_size[0] = 65535;
1214 grid_size[1] = 65535;
1215 grid_size[2] = 65535;
1216 }
1217 return 3 * sizeof(uint64_t) ;
1218
1219 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1220 if (ret) {
1221 uint64_t *block_size = ret;
1222 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1223 block_size[0] = threads_per_block;
1224 block_size[1] = threads_per_block;
1225 block_size[2] = threads_per_block;
1226 }
1227 return 3 * sizeof(uint64_t);
1228
1229 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1230 if (ret) {
1231 uint64_t *max_threads_per_block = ret;
1232 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1233 }
1234 return sizeof(uint64_t);
1235 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1236 if (ret) {
1237 uint32_t *address_bits = ret;
1238 address_bits[0] = 32;
1239 if (rscreen->chip_class >= SI)
1240 address_bits[0] = 64;
1241 }
1242 return 1 * sizeof(uint32_t);
1243
1244 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1245 if (ret) {
1246 uint64_t *max_global_size = ret;
1247 uint64_t max_mem_alloc_size;
1248
1249 r600_get_compute_param(screen, ir_type,
1250 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1251 &max_mem_alloc_size);
1252
1253 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1254 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1255 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1256 * make sure we never report more than
1257 * 4 * MAX_MEM_ALLOC_SIZE.
1258 */
1259 *max_global_size = MIN2(4 * max_mem_alloc_size,
1260 MAX2(rscreen->info.gart_size,
1261 rscreen->info.vram_size));
1262 }
1263 return sizeof(uint64_t);
1264
1265 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1266 if (ret) {
1267 uint64_t *max_local_size = ret;
1268 /* Value reported by the closed source driver. */
1269 *max_local_size = 32768;
1270 }
1271 return sizeof(uint64_t);
1272
1273 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1274 if (ret) {
1275 uint64_t *max_input_size = ret;
1276 /* Value reported by the closed source driver. */
1277 *max_input_size = 1024;
1278 }
1279 return sizeof(uint64_t);
1280
1281 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1282 if (ret) {
1283 uint64_t *max_mem_alloc_size = ret;
1284
1285 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1286 }
1287 return sizeof(uint64_t);
1288
1289 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1290 if (ret) {
1291 uint32_t *max_clock_frequency = ret;
1292 *max_clock_frequency = rscreen->info.max_shader_clock;
1293 }
1294 return sizeof(uint32_t);
1295
1296 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1297 if (ret) {
1298 uint32_t *max_compute_units = ret;
1299 *max_compute_units = rscreen->info.num_good_compute_units;
1300 }
1301 return sizeof(uint32_t);
1302
1303 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1304 if (ret) {
1305 uint32_t *images_supported = ret;
1306 *images_supported = 0;
1307 }
1308 return sizeof(uint32_t);
1309 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1310 break; /* unused */
1311 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1312 if (ret) {
1313 uint32_t *subgroup_size = ret;
1314 *subgroup_size = r600_wavefront_size(rscreen->family);
1315 }
1316 return sizeof(uint32_t);
1317 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1318 if (ret) {
1319 uint64_t *max_variable_threads_per_block = ret;
1320 if (rscreen->chip_class >= SI &&
1321 ir_type == PIPE_SHADER_IR_TGSI)
1322 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
1323 else
1324 *max_variable_threads_per_block = 0;
1325 }
1326 return sizeof(uint64_t);
1327 }
1328
1329 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1330 return 0;
1331 }
1332
1333 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1334 {
1335 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1336
1337 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1338 rscreen->info.clock_crystal_freq;
1339 }
1340
1341 static void r600_fence_reference(struct pipe_screen *screen,
1342 struct pipe_fence_handle **dst,
1343 struct pipe_fence_handle *src)
1344 {
1345 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1346 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1347 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1348
1349 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1350 ws->fence_reference(&(*rdst)->gfx, NULL);
1351 ws->fence_reference(&(*rdst)->sdma, NULL);
1352 FREE(*rdst);
1353 }
1354 *rdst = rsrc;
1355 }
1356
1357 static boolean r600_fence_finish(struct pipe_screen *screen,
1358 struct pipe_context *ctx,
1359 struct pipe_fence_handle *fence,
1360 uint64_t timeout)
1361 {
1362 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1363 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1364 struct r600_common_context *rctx;
1365 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1366
1367 ctx = threaded_context_unwrap_sync(ctx);
1368 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1369
1370 if (rfence->sdma) {
1371 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1372 return false;
1373
1374 /* Recompute the timeout after waiting. */
1375 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1376 int64_t time = os_time_get_nano();
1377 timeout = abs_timeout > time ? abs_timeout - time : 0;
1378 }
1379 }
1380
1381 if (!rfence->gfx)
1382 return true;
1383
1384 /* Flush the gfx IB if it hasn't been flushed yet. */
1385 if (rctx &&
1386 rfence->gfx_unflushed.ctx == rctx &&
1387 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1388 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1389 rfence->gfx_unflushed.ctx = NULL;
1390
1391 if (!timeout)
1392 return false;
1393
1394 /* Recompute the timeout after all that. */
1395 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1396 int64_t time = os_time_get_nano();
1397 timeout = abs_timeout > time ? abs_timeout - time : 0;
1398 }
1399 }
1400
1401 return rws->fence_wait(rws, rfence->gfx, timeout);
1402 }
1403
1404 static void r600_query_memory_info(struct pipe_screen *screen,
1405 struct pipe_memory_info *info)
1406 {
1407 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1408 struct radeon_winsys *ws = rscreen->ws;
1409 unsigned vram_usage, gtt_usage;
1410
1411 info->total_device_memory = rscreen->info.vram_size / 1024;
1412 info->total_staging_memory = rscreen->info.gart_size / 1024;
1413
1414 /* The real TTM memory usage is somewhat random, because:
1415 *
1416 * 1) TTM delays freeing memory, because it can only free it after
1417 * fences expire.
1418 *
1419 * 2) The memory usage can be really low if big VRAM evictions are
1420 * taking place, but the real usage is well above the size of VRAM.
1421 *
1422 * Instead, return statistics of this process.
1423 */
1424 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1425 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1426
1427 info->avail_device_memory =
1428 vram_usage <= info->total_device_memory ?
1429 info->total_device_memory - vram_usage : 0;
1430 info->avail_staging_memory =
1431 gtt_usage <= info->total_staging_memory ?
1432 info->total_staging_memory - gtt_usage : 0;
1433
1434 info->device_memory_evicted =
1435 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1436
1437 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1438 info->nr_device_memory_evictions =
1439 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1440 else
1441 /* Just return the number of evicted 64KB pages. */
1442 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1443 }
1444
1445 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1446 const struct pipe_resource *templ)
1447 {
1448 if (templ->target == PIPE_BUFFER) {
1449 return r600_buffer_create(screen, templ, 256);
1450 } else {
1451 return r600_texture_create(screen, templ);
1452 }
1453 }
1454
1455 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1456 struct radeon_winsys *ws)
1457 {
1458 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1459 struct utsname uname_data;
1460 const char *chip_name;
1461
1462 ws->query_info(ws, &rscreen->info);
1463 rscreen->ws = ws;
1464
1465 if ((chip_name = r600_get_marketing_name(ws)))
1466 snprintf(family_name, sizeof(family_name), "%s / ",
1467 r600_get_family_name(rscreen) + 4);
1468 else
1469 chip_name = r600_get_family_name(rscreen);
1470
1471 if (uname(&uname_data) == 0)
1472 snprintf(kernel_version, sizeof(kernel_version),
1473 " / %s", uname_data.release);
1474
1475 if (HAVE_LLVM > 0) {
1476 snprintf(llvm_string, sizeof(llvm_string),
1477 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1478 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1479 }
1480
1481 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1482 "%s (%sDRM %i.%i.%i%s%s)",
1483 chip_name, family_name, rscreen->info.drm_major,
1484 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1485 kernel_version, llvm_string);
1486
1487 rscreen->b.get_name = r600_get_name;
1488 rscreen->b.get_vendor = r600_get_vendor;
1489 rscreen->b.get_device_vendor = r600_get_device_vendor;
1490 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1491 rscreen->b.get_compute_param = r600_get_compute_param;
1492 rscreen->b.get_paramf = r600_get_paramf;
1493 rscreen->b.get_timestamp = r600_get_timestamp;
1494 rscreen->b.fence_finish = r600_fence_finish;
1495 rscreen->b.fence_reference = r600_fence_reference;
1496 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1497 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1498 rscreen->b.query_memory_info = r600_query_memory_info;
1499
1500 if (rscreen->info.has_hw_decode) {
1501 rscreen->b.get_video_param = rvid_get_video_param;
1502 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1503 } else {
1504 rscreen->b.get_video_param = r600_get_video_param;
1505 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1506 }
1507
1508 r600_init_screen_texture_functions(rscreen);
1509 r600_init_screen_query_functions(rscreen);
1510
1511 rscreen->family = rscreen->info.family;
1512 rscreen->chip_class = rscreen->info.chip_class;
1513 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1514 rscreen->has_rbplus = false;
1515 rscreen->rbplus_allowed = false;
1516
1517 r600_disk_cache_create(rscreen);
1518
1519 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1520
1521 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1522 if (rscreen->force_aniso >= 0) {
1523 printf("radeon: Forcing anisotropy filter to %ix\n",
1524 /* round down to a power of two */
1525 1 << util_logbase2(rscreen->force_aniso));
1526 }
1527
1528 util_format_s3tc_init();
1529 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1530 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1531
1532 if (rscreen->debug_flags & DBG_INFO) {
1533 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1534 rscreen->info.pci_domain, rscreen->info.pci_bus,
1535 rscreen->info.pci_dev, rscreen->info.pci_func);
1536 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1537 printf("family = %i (%s)\n", rscreen->info.family,
1538 r600_get_family_name(rscreen));
1539 printf("chip_class = %i\n", rscreen->info.chip_class);
1540 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1541 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1542 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1543 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1544 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1545 printf("max_alloc_size = %i MB\n",
1546 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1547 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1548 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1549 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1550 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1551 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1552 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1553 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1554 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1555 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1556 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1557 printf("me_fw_feature = %i\n", rscreen->info.me_fw_feature);
1558 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1559 printf("pfp_fw_feature = %i\n", rscreen->info.pfp_fw_feature);
1560 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1561 printf("ce_fw_feature = %i\n", rscreen->info.ce_fw_feature);
1562 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1563 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1564 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1565 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1566 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1567 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1568 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1569
1570 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1571 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1572 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1573 printf("max_se = %i\n", rscreen->info.max_se);
1574 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1575
1576 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1577 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1578 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1579 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1580 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1581 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1582 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1583 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1584 }
1585 return true;
1586 }
1587
1588 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1589 {
1590 r600_perfcounters_destroy(rscreen);
1591 r600_gpu_load_kill_thread(rscreen);
1592
1593 mtx_destroy(&rscreen->gpu_load_mutex);
1594 mtx_destroy(&rscreen->aux_context_lock);
1595 rscreen->aux_context->destroy(rscreen->aux_context);
1596
1597 slab_destroy_parent(&rscreen->pool_transfers);
1598
1599 disk_cache_destroy(rscreen->disk_shader_cache);
1600 rscreen->ws->destroy(rscreen->ws);
1601 FREE(rscreen);
1602 }
1603
1604 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1605 unsigned processor)
1606 {
1607 return rscreen->debug_flags & (1 << processor);
1608 }
1609
1610 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1611 {
1612 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1613 r600_can_dump_shader(rscreen, processor);
1614 }
1615
1616 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1617 uint64_t offset, uint64_t size, unsigned value)
1618 {
1619 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1620
1621 mtx_lock(&rscreen->aux_context_lock);
1622 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1623 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1624 mtx_unlock(&rscreen->aux_context_lock);
1625 }