src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/drm/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/u_double_list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  47 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  48 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  49
  50 #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  51 #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  52 #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  53 #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  54 #define R600_QUERY_NUM_CS_FLUSHES       (PIPE_QUERY_DRIVER_SPECIFIC + 4)
  55 #define R600_QUERY_NUM_BYTES_MOVED      (PIPE_QUERY_DRIVER_SPECIFIC + 5)
  56 #define R600_QUERY_VRAM_USAGE           (PIPE_QUERY_DRIVER_SPECIFIC + 6)
  57 #define R600_QUERY_GTT_USAGE            (PIPE_QUERY_DRIVER_SPECIFIC + 7)
  58
  59 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  60 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 1)
  61
  62 /* special primitive types */
  63 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  64
  65 /* Debug flags. */
  66 /* logging */
  67 #define DBG_TEX                 (1 << 0)
  68 #define DBG_TEXMIP              (1 << 1)
  69 #define DBG_COMPUTE             (1 << 2)
  70 #define DBG_VM                  (1 << 3)
  71 #define DBG_TRACE_CS            (1 << 4)
  72 /* shader logging */
  73 #define DBG_FS                  (1 << 5)
  74 #define DBG_VS                  (1 << 6)
  75 #define DBG_GS                  (1 << 7)
  76 #define DBG_PS                  (1 << 8)
  77 #define DBG_CS                  (1 << 9)
  78 /* features */
  79 #define DBG_NO_ASYNC_DMA        (1 << 10)
  80 #define DBG_NO_HYPERZ           (1 << 11)
  81 #define DBG_NO_DISCARD_RANGE    (1 << 12)
  82 #define DBG_NO_2D_TILING        (1 << 13)
  83 #define DBG_NO_TILING           (1 << 14)
  84 #define DBG_SWITCH_ON_EOP       (1 << 15)
  85 #define DBG_FORCE_DMA           (1 << 16)
  86 /* The maximum allowed bit is 20. */
  87
  88 #define R600_MAP_BUFFER_ALIGNMENT 64
  89
  90 struct r600_common_context;
  91
  92 struct radeon_shader_reloc {
  93         char *name;
  94         uint64_t offset;
  95 };
  96
  97 struct radeon_shader_binary {
  98         /** Shader code */
  99         unsigned char *code;
 100         unsigned code_size;
 101
 102         /** Config/Context register state that accompanies this shader.
 103          * This is a stream of dword pairs.  First dword contains the
 104          * register address, the second dword contains the value.*/
 105         unsigned char *config;
 106         unsigned config_size;
 107
 108         /** The number of bytes of config information for each global symbol.
 109          */
 110         unsigned config_size_per_symbol;
 111
 112         /** Constant data accessed by the shader.  This will be uploaded
 113          * into a constant buffer. */
 114         unsigned char *rodata;
 115         unsigned rodata_size;
 116
 117         /** List of symbol offsets for the shader */
 118         uint64_t *global_symbol_offsets;
 119         unsigned global_symbol_count;
 120
 121         struct radeon_shader_reloc *relocs;
 122         unsigned reloc_count;
 123
 124         /** Set to 1 if the disassembly for this binary has been dumped to
 125          *  stderr. */
 126         int disassembled;
 127 };
 128
 129 struct r600_resource {
 130         struct u_resource               b;
 131
 132         /* Winsys objects. */
 133         struct pb_buffer                *buf;
 134         struct radeon_winsys_cs_handle  *cs_buf;
 135         uint64_t                        gpu_address;
 136
 137         /* Resource state. */
 138         enum radeon_bo_domain           domains;
 139
 140         /* The buffer range which is initialized (with a write transfer,
 141          * streamout, DMA, or as a random access target). The rest of
 142          * the buffer is considered invalid and can be mapped unsynchronized.
 143          *
 144          * This allows unsychronized mapping of a buffer range which hasn't
 145          * been used yet. It's for applications which forget to use
 146          * the unsynchronized map flag and expect the driver to figure it out.
 147          */
 148         struct util_range               valid_buffer_range;
 149
 150         /* For buffers only. This indicates that a write operation has been
 151          * performed by TC L2, but the cache hasn't been flushed.
 152          * Any hw block which doesn't use or bypasses TC L2 should check this
 153          * flag and flush the cache before using the buffer.
 154          *
 155          * For example, TC L2 must be flushed if a buffer which has been
 156          * modified by a shader store instruction is about to be used as
 157          * an index buffer. The reason is that VGT DMA index fetching doesn't
 158          * use TC L2.
 159          */
 160         bool                            TC_L2_dirty;
 161 };
 162
 163 struct r600_transfer {
 164         struct pipe_transfer            transfer;
 165         struct r600_resource            *staging;
 166         unsigned                        offset;
 167 };
 168
 169 struct r600_fmask_info {
 170         unsigned offset;
 171         unsigned size;
 172         unsigned alignment;
 173         unsigned pitch;
 174         unsigned bank_height;
 175         unsigned slice_tile_max;
 176         unsigned tile_mode_index;
 177 };
 178
 179 struct r600_cmask_info {
 180         unsigned offset;
 181         unsigned size;
 182         unsigned alignment;
 183         unsigned slice_tile_max;
 184         unsigned base_address_reg;
 185 };
 186
 187 struct r600_texture {
 188         struct r600_resource            resource;
 189
 190         unsigned                        size;
 191         unsigned                        pitch_override;
 192         bool                            is_depth;
 193         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 194         struct r600_texture             *flushed_depth_texture;
 195         boolean                         is_flushing_texture;
 196         struct radeon_surface           surface;
 197
 198         /* Colorbuffer compression and fast clear. */
 199         struct r600_fmask_info          fmask;
 200         struct r600_cmask_info          cmask;
 201         struct r600_resource            *cmask_buffer;
 202         unsigned                        cb_color_info; /* fast clear enable bit */
 203         unsigned                        color_clear_value[2];
 204
 205         /* Depth buffer compression and fast clear. */
 206         struct r600_resource            *htile_buffer;
 207         bool                            depth_cleared; /* if it was cleared at least once */
 208         float                           depth_clear_value;
 209
 210         bool                            non_disp_tiling; /* R600-Cayman only */
 211         unsigned                        mipmap_shift;
 212 };
 213
 214 struct r600_surface {
 215         struct pipe_surface             base;
 216
 217         bool color_initialized;
 218         bool depth_initialized;
 219
 220         /* Misc. color flags. */
 221         bool alphatest_bypass;
 222         bool export_16bpc;
 223
 224         /* Color registers. */
 225         unsigned cb_color_info;
 226         unsigned cb_color_base;
 227         unsigned cb_color_view;
 228         unsigned cb_color_size;         /* R600 only */
 229         unsigned cb_color_dim;          /* EG only */
 230         unsigned cb_color_pitch;        /* EG and later */
 231         unsigned cb_color_slice;        /* EG and later */
 232         unsigned cb_color_attrib;       /* EG and later */
 233         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 234         unsigned cb_color_fmask_slice;  /* EG and later */
 235         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 236         unsigned cb_color_mask;         /* R600 only */
 237         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 238         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 239
 240         /* DB registers. */
 241         unsigned db_depth_info;         /* R600 only, then SI and later */
 242         unsigned db_z_info;             /* EG and later */
 243         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 244         unsigned db_depth_view;
 245         unsigned db_depth_size;
 246         unsigned db_depth_slice;        /* EG and later */
 247         unsigned db_stencil_base;       /* EG and later */
 248         unsigned db_stencil_info;       /* EG and later */
 249         unsigned db_prefetch_limit;     /* R600 only */
 250         unsigned db_htile_surface;
 251         unsigned db_htile_data_base;
 252         unsigned db_preload_control;    /* EG and later */
 253         unsigned pa_su_poly_offset_db_fmt_cntl;
 254 };
 255
 256 struct r600_tiling_info {
 257         unsigned num_channels;
 258         unsigned num_banks;
 259         unsigned group_bytes;
 260 };
 261
 262 struct r600_common_screen {
 263         struct pipe_screen              b;
 264         struct radeon_winsys            *ws;
 265         enum radeon_family              family;
 266         enum chip_class                 chip_class;
 267         struct radeon_info              info;
 268         struct r600_tiling_info         tiling_info;
 269         unsigned                        debug_flags;
 270         bool                            has_cp_dma;
 271         bool                            has_streamout;
 272
 273         /* Auxiliary context. Mainly used to initialize resources.
 274          * It must be locked prior to using and flushed before unlocking. */
 275         struct pipe_context             *aux_context;
 276         pipe_mutex                      aux_context_lock;
 277
 278         struct r600_resource            *trace_bo;
 279         uint32_t                        *trace_ptr;
 280         unsigned                        cs_count;
 281 };
 282
 283 /* This encapsulates a state or an operation which can emitted into the GPU
 284  * command stream. */
 285 struct r600_atom {
 286         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 287         unsigned                num_dw;
 288         bool                    dirty;
 289 };
 290
 291 struct r600_so_target {
 292         struct pipe_stream_output_target b;
 293
 294         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 295         struct r600_resource    *buf_filled_size;
 296         unsigned                buf_filled_size_offset;
 297
 298         unsigned                stride_in_dw;
 299 };
 300
 301 struct r600_streamout {
 302         struct r600_atom                begin_atom;
 303         bool                            begin_emitted;
 304         unsigned                        num_dw_for_end;
 305
 306         unsigned                        enabled_mask;
 307         unsigned                        num_targets;
 308         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 309
 310         unsigned                        append_bitmask;
 311         bool                            suspended;
 312
 313         /* External state which comes from the vertex shader,
 314          * it must be set explicitly when binding a shader. */
 315         unsigned                        *stride_in_dw;
 316
 317         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 318         struct r600_atom                enable_atom;
 319         bool                            streamout_enabled;
 320         bool                            prims_gen_query_enabled;
 321         int                             num_prims_gen_queries;
 322 };
 323
 324 struct r600_ring {
 325         struct radeon_winsys_cs         *cs;
 326         bool                            flushing;
 327         void (*flush)(void *ctx, unsigned flags,
 328                       struct pipe_fence_handle **fence);
 329 };
 330
 331 struct r600_rings {
 332         struct r600_ring                gfx;
 333         struct r600_ring                dma;
 334 };
 335
 336 struct r600_common_context {
 337         struct pipe_context b; /* base class */
 338
 339         struct r600_common_screen       *screen;
 340         struct radeon_winsys            *ws;
 341         enum radeon_family              family;
 342         enum chip_class                 chip_class;
 343         struct r600_rings               rings;
 344         unsigned                        initial_gfx_cs_size;
 345
 346         struct u_upload_mgr             *uploader;
 347         struct u_suballocator           *allocator_so_filled_size;
 348         struct util_slab_mempool        pool_transfers;
 349
 350         /* Current unaccounted memory usage. */
 351         uint64_t                        vram;
 352         uint64_t                        gtt;
 353
 354         /* States. */
 355         struct r600_streamout           streamout;
 356
 357         /* Additional context states. */
 358         unsigned flags; /* flush flags */
 359
 360         /* Queries. */
 361         /* The list of active queries. Only one query of each type can be active. */
 362         int                             num_occlusion_queries;
 363         int                             num_pipelinestat_queries;
 364         /* Keep track of non-timer queries, because they should be suspended
 365          * during context flushing.
 366          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
 367         struct list_head                active_nontimer_queries;
 368         unsigned                        num_cs_dw_nontimer_queries_suspend;
 369         /* If queries have been suspended. */
 370         bool                            nontimer_queries_suspended;
 371         /* Additional hardware info. */
 372         unsigned                        backend_mask;
 373         unsigned                        max_db; /* for OQ */
 374         /* Misc stats. */
 375         unsigned                        num_draw_calls;
 376
 377         /* Render condition. */
 378         struct pipe_query               *current_render_cond;
 379         unsigned                        current_render_cond_mode;
 380         boolean                         current_render_cond_cond;
 381         boolean                         predicate_drawing;
 382         /* For context flushing. */
 383         struct pipe_query               *saved_render_cond;
 384         boolean                         saved_render_cond_cond;
 385         unsigned                        saved_render_cond_mode;
 386
 387         /* MSAA sample locations.
 388          * The first index is the sample index.
 389          * The second index is the coordinate: X, Y. */
 390         float                           sample_locations_1x[1][2];
 391         float                           sample_locations_2x[2][2];
 392         float                           sample_locations_4x[4][2];
 393         float                           sample_locations_8x[8][2];
 394         float                           sample_locations_16x[16][2];
 395
 396         /* The list of all texture buffer objects in this context.
 397          * This list is walked when a buffer is invalidated/reallocated and
 398          * the GPU addresses are updated. */
 399         struct list_head                texture_buffers;
 400
 401         /* Copy one resource to another using async DMA. */
 402         void (*dma_copy)(struct pipe_context *ctx,
 403                          struct pipe_resource *dst,
 404                          unsigned dst_level,
 405                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 406                          struct pipe_resource *src,
 407                          unsigned src_level,
 408                          const struct pipe_box *src_box);
 409
 410         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 411                              unsigned offset, unsigned size, unsigned value,
 412                              bool is_framebuffer);
 413
 414         void (*blit_decompress_depth)(struct pipe_context *ctx,
 415                                       struct r600_texture *texture,
 416                                       struct r600_texture *staging,
 417                                       unsigned first_level, unsigned last_level,
 418                                       unsigned first_layer, unsigned last_layer,
 419                                       unsigned first_sample, unsigned last_sample);
 420
 421         /* Reallocate the buffer and update all resource bindings where
 422          * the buffer is bound, including all resource descriptors. */
 423         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 424
 425         /* Enable or disable occlusion queries. */
 426         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 427
 428         /* This ensures there is enough space in the command stream. */
 429         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 430                                   bool include_draw_vbo);
 431 };
 432
 433 /* r600_buffer.c */
 434 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 435                                         struct radeon_winsys_cs_handle *buf,
 436                                         enum radeon_bo_usage usage);
 437 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 438                                       struct r600_resource *resource,
 439                                       unsigned usage);
 440 bool r600_init_resource(struct r600_common_screen *rscreen,
 441                         struct r600_resource *res,
 442                         unsigned size, unsigned alignment,
 443                         bool use_reusable_pool);
 444 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 445                                          const struct pipe_resource *templ,
 446                                          unsigned alignment);
 447
 448 /* r600_common_pipe.c */
 449 void r600_draw_rectangle(struct blitter_context *blitter,
 450                          int x1, int y1, int x2, int y2, float depth,
 451                          enum blitter_attrib_type type,
 452                          const union pipe_color_union *attrib);
 453 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 454                              struct radeon_winsys *ws);
 455 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 456 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 457 void r600_postflush_resume_features(struct r600_common_context *ctx);
 458 bool r600_common_context_init(struct r600_common_context *rctx,
 459                               struct r600_common_screen *rscreen);
 460 void r600_common_context_cleanup(struct r600_common_context *rctx);
 461 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 462 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 463                           const struct tgsi_token *tokens);
 464 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 465                               unsigned offset, unsigned size, unsigned value,
 466                               bool is_framebuffer);
 467 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 468                                                   const struct pipe_resource *templ);
 469 const char *r600_get_llvm_processor_name(enum radeon_family family);
 470 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 471
 472 /* r600_query.c */
 473 void r600_query_init(struct r600_common_context *rctx);
 474 void r600_suspend_nontimer_queries(struct r600_common_context *ctx);
 475 void r600_resume_nontimer_queries(struct r600_common_context *ctx);
 476 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 477
 478 /* r600_streamout.c */
 479 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 480 void r600_set_streamout_targets(struct pipe_context *ctx,
 481                                 unsigned num_targets,
 482                                 struct pipe_stream_output_target **targets,
 483                                 const unsigned *offset);
 484 void r600_emit_streamout_end(struct r600_common_context *rctx);
 485 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 486                                              unsigned type, int diff);
 487 void r600_streamout_init(struct r600_common_context *rctx);
 488
 489 /* r600_texture.c */
 490 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 491                                  struct r600_texture *rtex,
 492                                  unsigned nr_samples,
 493                                  struct r600_fmask_info *out);
 494 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 495                                  struct r600_texture *rtex,
 496                                  struct r600_cmask_info *out);
 497 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 498                                      struct pipe_resource *texture,
 499                                      struct r600_texture **staging);
 500 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 501                                         const struct pipe_resource *templ);
 502 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 503                                                 struct pipe_resource *texture,
 504                                                 const struct pipe_surface *templ,
 505                                                 unsigned width, unsigned height);
 506 unsigned r600_translate_colorswap(enum pipe_format format);
 507 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 508                                    struct pipe_framebuffer_state *fb,
 509                                    struct r600_atom *fb_state,
 510                                    unsigned *buffers,
 511                                    const union pipe_color_union *color);
 512 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 513 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 514
 515 /* cayman_msaa.c */
 516 extern const uint32_t eg_sample_locs_2x[4];
 517 extern const unsigned eg_max_dist_2x;
 518 extern const uint32_t eg_sample_locs_4x[4];
 519 extern const unsigned eg_max_dist_4x;
 520 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 521                                 unsigned sample_index, float *out_value);
 522 void cayman_init_msaa(struct pipe_context *ctx);
 523 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 524 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 525                              int ps_iter_samples);
 526
 527
 528 /* Inline helpers. */
 529
 530 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 531 {
 532         return (struct r600_resource*)r;
 533 }
 534
 535 static INLINE void
 536 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 537 {
 538         pipe_resource_reference((struct pipe_resource **)ptr,
 539                                 (struct pipe_resource *)res);
 540 }
 541
 542 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 543 {
 544         if (filter <= 1)   return 0;
 545         if (filter <= 2)   return 1;
 546         if (filter <= 4)   return 2;
 547         if (filter <= 8)   return 3;
 548          /* else */        return 4;
 549 }
 550
 551 #define COMPUTE_DBG(rscreen, fmt, args...) \
 552         do { \
 553                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 554         } while (0);
 555
 556 #define R600_ERR(fmt, args...) \
 557         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
 558
 559 /* For MSAA sample positions. */
 560 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 561         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 562         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 563         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 564          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 565
 566 #endif