src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 /**
  25  * This file contains common screen and context structures and functions
  26  * for r600g and radeonsi.
  27  */
  28
  29 #ifndef R600_PIPE_COMMON_H
  30 #define R600_PIPE_COMMON_H
  31
  32 #include <stdio.h>
  33
  34 #include "amd/common/ac_binary.h"
  35
  36 #include "radeon/radeon_winsys.h"
  37
  38 #include "util/disk_cache.h"
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45 #include "util/u_threaded_context.h"
  46
  47 struct u_log_context;
  48 struct si_screen;
  49 struct si_context;
  50
  51 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  53 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  54 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  55 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  56 #define R600_RESOURCE_FLAG_READ_ONLY            (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
  57 #define R600_RESOURCE_FLAG_32BIT                (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
  58
  59 /* Debug flags. */
  60 enum {
  61         /* Shader logging options: */
  62         DBG_VS = PIPE_SHADER_VERTEX,
  63         DBG_PS = PIPE_SHADER_FRAGMENT,
  64         DBG_GS = PIPE_SHADER_GEOMETRY,
  65         DBG_TCS = PIPE_SHADER_TESS_CTRL,
  66         DBG_TES = PIPE_SHADER_TESS_EVAL,
  67         DBG_CS = PIPE_SHADER_COMPUTE,
  68         DBG_NO_IR,
  69         DBG_NO_TGSI,
  70         DBG_NO_ASM,
  71         DBG_PREOPT_IR,
  72
  73         /* Shader compiler options the shader cache should be aware of: */
  74         DBG_FS_CORRECT_DERIVS_AFTER_KILL,
  75         DBG_UNSAFE_MATH,
  76         DBG_SI_SCHED,
  77
  78         /* Shader compiler options (with no effect on the shader cache): */
  79         DBG_CHECK_IR,
  80         DBG_NIR,
  81         DBG_MONOLITHIC_SHADERS,
  82         DBG_NO_OPT_VARIANT,
  83
  84         /* Information logging options: */
  85         DBG_INFO,
  86         DBG_TEX,
  87         DBG_COMPUTE,
  88         DBG_VM,
  89
  90         /* Driver options: */
  91         DBG_FORCE_DMA,
  92         DBG_NO_ASYNC_DMA,
  93         DBG_NO_WC,
  94         DBG_CHECK_VM,
  95         DBG_RESERVE_VMID,
  96
  97         /* 3D engine options: */
  98         DBG_SWITCH_ON_EOP,
  99         DBG_NO_OUT_OF_ORDER,
 100         DBG_NO_DPBB,
 101         DBG_NO_DFSM,
 102         DBG_DPBB,
 103         DBG_DFSM,
 104         DBG_NO_HYPERZ,
 105         DBG_NO_RB_PLUS,
 106         DBG_NO_2D_TILING,
 107         DBG_NO_TILING,
 108         DBG_NO_DCC,
 109         DBG_NO_DCC_CLEAR,
 110         DBG_NO_DCC_FB,
 111         DBG_NO_DCC_MSAA,
 112         DBG_DCC_MSAA,
 113         DBG_NO_FMASK,
 114
 115         /* Tests: */
 116         DBG_TEST_DMA,
 117         DBG_TEST_VMFAULT_CP,
 118         DBG_TEST_VMFAULT_SDMA,
 119         DBG_TEST_VMFAULT_SHADER,
 120 };
 121
 122 #define DBG_ALL_SHADERS         (((1 << (DBG_CS + 1)) - 1))
 123 #define DBG(name)               (1ull << DBG_##name)
 124
 125 #define R600_MAP_BUFFER_ALIGNMENT 64
 126
 127 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 128
 129 struct r600_common_context;
 130 struct r600_perfcounters;
 131 struct tgsi_shader_info;
 132 struct r600_qbo_state;
 133
 134 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 135  * at the moment.
 136  */
 137 struct r600_resource {
 138         struct threaded_resource        b;
 139
 140         /* Winsys objects. */
 141         struct pb_buffer                *buf;
 142         uint64_t                        gpu_address;
 143         /* Memory usage if the buffer placement is optimal. */
 144         uint64_t                        vram_usage;
 145         uint64_t                        gart_usage;
 146
 147         /* Resource properties. */
 148         uint64_t                        bo_size;
 149         unsigned                        bo_alignment;
 150         enum radeon_bo_domain           domains;
 151         enum radeon_bo_flag             flags;
 152         unsigned                        bind_history;
 153         int                             max_forced_staging_uploads;
 154
 155         /* The buffer range which is initialized (with a write transfer,
 156          * streamout, DMA, or as a random access target). The rest of
 157          * the buffer is considered invalid and can be mapped unsynchronized.
 158          *
 159          * This allows unsychronized mapping of a buffer range which hasn't
 160          * been used yet. It's for applications which forget to use
 161          * the unsynchronized map flag and expect the driver to figure it out.
 162          */
 163         struct util_range               valid_buffer_range;
 164
 165         /* For buffers only. This indicates that a write operation has been
 166          * performed by TC L2, but the cache hasn't been flushed.
 167          * Any hw block which doesn't use or bypasses TC L2 should check this
 168          * flag and flush the cache before using the buffer.
 169          *
 170          * For example, TC L2 must be flushed if a buffer which has been
 171          * modified by a shader store instruction is about to be used as
 172          * an index buffer. The reason is that VGT DMA index fetching doesn't
 173          * use TC L2.
 174          */
 175         bool                            TC_L2_dirty;
 176
 177         /* Whether the resource has been exported via resource_get_handle. */
 178         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 179
 180         /* Whether this resource is referenced by bindless handles. */
 181         bool                            texture_handle_allocated;
 182         bool                            image_handle_allocated;
 183 };
 184
 185 struct r600_transfer {
 186         struct threaded_transfer        b;
 187         struct r600_resource            *staging;
 188         unsigned                        offset;
 189 };
 190
 191 struct r600_fmask_info {
 192         uint64_t offset;
 193         uint64_t size;
 194         unsigned alignment;
 195         unsigned pitch_in_pixels;
 196         unsigned bank_height;
 197         unsigned slice_tile_max;
 198         unsigned tile_mode_index;
 199         unsigned tile_swizzle;
 200 };
 201
 202 struct r600_cmask_info {
 203         uint64_t offset;
 204         uint64_t size;
 205         unsigned alignment;
 206         unsigned slice_tile_max;
 207         uint64_t base_address_reg;
 208 };
 209
 210 struct r600_texture {
 211         struct r600_resource            resource;
 212
 213         struct radeon_surf              surface;
 214         uint64_t                        size;
 215         struct r600_texture             *flushed_depth_texture;
 216
 217         /* Colorbuffer compression and fast clear. */
 218         struct r600_fmask_info          fmask;
 219         struct r600_cmask_info          cmask;
 220         struct r600_resource            *cmask_buffer;
 221         uint64_t                        dcc_offset; /* 0 = disabled */
 222         unsigned                        cb_color_info; /* fast clear enable bit */
 223         unsigned                        color_clear_value[2];
 224         unsigned                        last_msaa_resolve_target_micro_mode;
 225         unsigned                        num_level0_transfers;
 226
 227         /* Depth buffer compression and fast clear. */
 228         uint64_t                        htile_offset;
 229         float                           depth_clear_value;
 230         uint16_t                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 231         uint16_t                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 232         enum pipe_format                db_render_format:16;
 233         uint8_t                         stencil_clear_value;
 234         bool                            tc_compatible_htile:1;
 235         bool                            depth_cleared:1; /* if it was cleared at least once */
 236         bool                            stencil_cleared:1; /* if it was cleared at least once */
 237         bool                            upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
 238         bool                            is_depth:1;
 239         bool                            db_compatible:1;
 240         bool                            can_sample_z:1;
 241         bool                            can_sample_s:1;
 242
 243         /* We need to track DCC dirtiness, because st/dri usually calls
 244          * flush_resource twice per frame (not a bug) and we don't wanna
 245          * decompress DCC twice. Also, the dirty tracking must be done even
 246          * if DCC isn't used, because it's required by the DCC usage analysis
 247          * for a possible future enablement.
 248          */
 249         bool                            separate_dcc_dirty:1;
 250         /* Statistics gathering for the DCC enablement heuristic. */
 251         bool                            dcc_gather_statistics:1;
 252         /* Counter that should be non-zero if the texture is bound to a
 253          * framebuffer.
 254          */
 255         unsigned                        framebuffers_bound;
 256         /* Whether the texture is a displayable back buffer and needs DCC
 257          * decompression, which is expensive. Therefore, it's enabled only
 258          * if statistics suggest that it will pay off and it's allocated
 259          * separately. It can't be bound as a sampler by apps. Limited to
 260          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 261          * the absolute GPUVM address, not the relative one.
 262          */
 263         struct r600_resource            *dcc_separate_buffer;
 264         /* When DCC is temporarily disabled, the separate buffer is here. */
 265         struct r600_resource            *last_dcc_separate_buffer;
 266         /* Estimate of how much this color buffer is written to in units of
 267          * full-screen draws: ps_invocations / (width * height)
 268          * Shader kills, late Z, and blending with trivial discards make it
 269          * inaccurate (we need to count CB updates, not PS invocations).
 270          */
 271         unsigned                        ps_draw_ratio;
 272         /* The number of clears since the last DCC usage analysis. */
 273         unsigned                        num_slow_clears;
 274 };
 275
 276 struct r600_surface {
 277         struct pipe_surface             base;
 278
 279         /* These can vary with block-compressed textures. */
 280         uint16_t width0;
 281         uint16_t height0;
 282
 283         bool color_initialized:1;
 284         bool depth_initialized:1;
 285
 286         /* Misc. color flags. */
 287         bool color_is_int8:1;
 288         bool color_is_int10:1;
 289         bool dcc_incompatible:1;
 290
 291         /* Color registers. */
 292         unsigned cb_color_info;
 293         unsigned cb_color_view;
 294         unsigned cb_color_attrib;
 295         unsigned cb_color_attrib2;      /* GFX9 and later */
 296         unsigned cb_dcc_control;        /* VI and later */
 297         unsigned spi_shader_col_format:8;       /* no blending, no alpha-to-coverage. */
 298         unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
 299         unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
 300         unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
 301
 302         /* DB registers. */
 303         uint64_t db_depth_base;         /* DB_Z_READ/WRITE_BASE */
 304         uint64_t db_stencil_base;
 305         uint64_t db_htile_data_base;
 306         unsigned db_depth_info;
 307         unsigned db_z_info;
 308         unsigned db_z_info2;            /* GFX9+ */
 309         unsigned db_depth_view;
 310         unsigned db_depth_size;
 311         unsigned db_depth_slice;
 312         unsigned db_stencil_info;
 313         unsigned db_stencil_info2;      /* GFX9+ */
 314         unsigned db_htile_surface;
 315 };
 316
 317 struct r600_mmio_counter {
 318         unsigned busy;
 319         unsigned idle;
 320 };
 321
 322 union r600_mmio_counters {
 323         struct {
 324                 /* For global GPU load including SDMA. */
 325                 struct r600_mmio_counter gpu;
 326
 327                 /* GRBM_STATUS */
 328                 struct r600_mmio_counter spi;
 329                 struct r600_mmio_counter gui;
 330                 struct r600_mmio_counter ta;
 331                 struct r600_mmio_counter gds;
 332                 struct r600_mmio_counter vgt;
 333                 struct r600_mmio_counter ia;
 334                 struct r600_mmio_counter sx;
 335                 struct r600_mmio_counter wd;
 336                 struct r600_mmio_counter bci;
 337                 struct r600_mmio_counter sc;
 338                 struct r600_mmio_counter pa;
 339                 struct r600_mmio_counter db;
 340                 struct r600_mmio_counter cp;
 341                 struct r600_mmio_counter cb;
 342
 343                 /* SRBM_STATUS2 */
 344                 struct r600_mmio_counter sdma;
 345
 346                 /* CP_STAT */
 347                 struct r600_mmio_counter pfp;
 348                 struct r600_mmio_counter meq;
 349                 struct r600_mmio_counter me;
 350                 struct r600_mmio_counter surf_sync;
 351                 struct r600_mmio_counter cp_dma;
 352                 struct r600_mmio_counter scratch_ram;
 353         } named;
 354         unsigned array[0];
 355 };
 356
 357 struct r600_memory_object {
 358         struct pipe_memory_object       b;
 359         struct pb_buffer                *buf;
 360         uint32_t                        stride;
 361         uint32_t                        offset;
 362 };
 363
 364 /* This encapsulates a state or an operation which can emitted into the GPU
 365  * command stream. */
 366 struct r600_atom {
 367         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 368         unsigned short          id;
 369 };
 370
 371 struct r600_ring {
 372         struct radeon_winsys_cs         *cs;
 373         void (*flush)(void *ctx, unsigned flags,
 374                       struct pipe_fence_handle **fence);
 375 };
 376
 377 /* Saved CS data for debugging features. */
 378 struct radeon_saved_cs {
 379         uint32_t                        *ib;
 380         unsigned                        num_dw;
 381
 382         struct radeon_bo_list_item      *bo_list;
 383         unsigned                        bo_count;
 384 };
 385
 386 struct r600_common_context {
 387         struct pipe_context b; /* base class */
 388
 389         struct si_screen                *screen;
 390         struct radeon_winsys            *ws;
 391         struct radeon_winsys_ctx        *ctx;
 392         enum radeon_family              family;
 393         enum chip_class                 chip_class;
 394         struct r600_ring                gfx;
 395         struct r600_ring                dma;
 396         struct pipe_fence_handle        *last_gfx_fence;
 397         struct pipe_fence_handle        *last_sdma_fence;
 398         struct r600_resource            *eop_bug_scratch;
 399         struct u_upload_mgr             *cached_gtt_allocator;
 400         unsigned                        num_gfx_cs_flushes;
 401         unsigned                        initial_gfx_cs_size;
 402         unsigned                        gpu_reset_counter;
 403         unsigned                        last_dirty_tex_counter;
 404         unsigned                        last_compressed_colortex_counter;
 405         unsigned                        last_num_draw_calls;
 406
 407         struct threaded_context         *tc;
 408         struct u_suballocator           *allocator_zeroed_memory;
 409         struct slab_child_pool          pool_transfers;
 410         struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 411
 412         /* Current unaccounted memory usage. */
 413         uint64_t                        vram;
 414         uint64_t                        gtt;
 415
 416         /* Additional context states. */
 417         unsigned flags; /* flush flags */
 418
 419         /* Queries. */
 420         /* Maintain the list of active queries for pausing between IBs. */
 421         int                             num_occlusion_queries;
 422         int                             num_perfect_occlusion_queries;
 423         struct list_head                active_queries;
 424         unsigned                        num_cs_dw_queries_suspend;
 425         /* Misc stats. */
 426         unsigned                        num_draw_calls;
 427         unsigned                        num_decompress_calls;
 428         unsigned                        num_mrt_draw_calls;
 429         unsigned                        num_prim_restart_calls;
 430         unsigned                        num_spill_draw_calls;
 431         unsigned                        num_compute_calls;
 432         unsigned                        num_spill_compute_calls;
 433         unsigned                        num_dma_calls;
 434         unsigned                        num_cp_dma_calls;
 435         unsigned                        num_vs_flushes;
 436         unsigned                        num_ps_flushes;
 437         unsigned                        num_cs_flushes;
 438         unsigned                        num_cb_cache_flushes;
 439         unsigned                        num_db_cache_flushes;
 440         unsigned                        num_L2_invalidates;
 441         unsigned                        num_L2_writebacks;
 442         unsigned                        num_resident_handles;
 443         uint64_t                        num_alloc_tex_transfer_bytes;
 444         unsigned                        last_tex_ps_draw_ratio; /* for query */
 445
 446         /* Render condition. */
 447         struct r600_atom                render_cond_atom;
 448         struct pipe_query               *render_cond;
 449         unsigned                        render_cond_mode;
 450         bool                            render_cond_invert;
 451         bool                            render_cond_force_off; /* for u_blitter */
 452
 453         /* Statistics gathering for the DCC enablement heuristic. It can't be
 454          * in r600_texture because r600_texture can be shared by multiple
 455          * contexts. This is for back buffers only. We shouldn't get too many
 456          * of those.
 457          *
 458          * X11 DRI3 rotates among a finite set of back buffers. They should
 459          * all fit in this array. If they don't, separate DCC might never be
 460          * enabled by DCC stat gathering.
 461          */
 462         struct {
 463                 struct r600_texture             *tex;
 464                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 465                 struct pipe_query               *ps_stats[3];
 466                 /* If all slots are used and another slot is needed,
 467                  * the least recently used slot is evicted based on this. */
 468                 int64_t                         last_use_timestamp;
 469                 bool                            query_active;
 470         } dcc_stats[5];
 471
 472         struct pipe_device_reset_callback device_reset_callback;
 473         struct u_log_context            *log;
 474
 475         void                            *query_result_shader;
 476
 477         /* Copy one resource to another using async DMA. */
 478         void (*dma_copy)(struct pipe_context *ctx,
 479                          struct pipe_resource *dst,
 480                          unsigned dst_level,
 481                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 482                          struct pipe_resource *src,
 483                          unsigned src_level,
 484                          const struct pipe_box *src_box);
 485
 486         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 487                                  uint64_t offset, uint64_t size, unsigned value);
 488
 489         void (*blit_decompress_depth)(struct pipe_context *ctx,
 490                                       struct r600_texture *texture,
 491                                       struct r600_texture *staging,
 492                                       unsigned first_level, unsigned last_level,
 493                                       unsigned first_layer, unsigned last_layer,
 494                                       unsigned first_sample, unsigned last_sample);
 495
 496         void (*decompress_dcc)(struct pipe_context *ctx,
 497                                struct r600_texture *rtex);
 498
 499         /* Reallocate the buffer and update all resource bindings where
 500          * the buffer is bound, including all resource descriptors. */
 501         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 502
 503         /* Update all resource bindings where the buffer is bound, including
 504          * all resource descriptors. This is invalidate_buffer without
 505          * the invalidation. */
 506         void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
 507                               uint64_t old_gpu_address);
 508
 509         /* Enable or disable occlusion queries. */
 510         void (*set_occlusion_query_state)(struct pipe_context *ctx,
 511                                           bool old_enable,
 512                                           bool old_perfect_enable);
 513
 514         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 515
 516         /* This ensures there is enough space in the command stream. */
 517         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 518                                   bool include_draw_vbo);
 519 };
 520
 521 /* r600_buffer_common.c */
 522 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
 523                                    struct pb_buffer *buf,
 524                                    enum radeon_bo_usage usage);
 525 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 526                                     struct r600_resource *resource,
 527                                     unsigned usage);
 528 void si_init_resource_fields(struct si_screen *sscreen,
 529                              struct r600_resource *res,
 530                              uint64_t size, unsigned alignment);
 531 bool si_alloc_resource(struct si_screen *sscreen,
 532                        struct r600_resource *res);
 533 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 534                                                unsigned flags,
 535                                                unsigned usage,
 536                                                unsigned size,
 537                                                unsigned alignment);
 538 void si_replace_buffer_storage(struct pipe_context *ctx,
 539                                struct pipe_resource *dst,
 540                                struct pipe_resource *src);
 541 void si_init_screen_buffer_functions(struct si_screen *sscreen);
 542 void si_init_buffer_functions(struct si_context *sctx);
 543
 544 /* r600_common_pipe.c */
 545 void si_gfx_write_event_eop(struct r600_common_context *ctx,
 546                             unsigned event, unsigned event_flags,
 547                             unsigned data_sel,
 548                             struct r600_resource *buf, uint64_t va,
 549                             uint32_t new_fence, unsigned query_type);
 550 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
 551 void si_gfx_wait_fence(struct r600_common_context *ctx,
 552                        uint64_t va, uint32_t ref, uint32_t mask);
 553 bool si_common_context_init(struct r600_common_context *rctx,
 554                             struct si_screen *sscreen,
 555                             unsigned context_flags);
 556 void si_common_context_cleanup(struct r600_common_context *rctx);
 557 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
 558                             uint64_t offset, uint64_t size, unsigned value);
 559 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 560                        struct r600_resource *dst, struct r600_resource *src);
 561 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 562                 struct radeon_saved_cs *saved, bool get_buffer_list);
 563 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 564 bool si_check_device_reset(struct r600_common_context *rctx);
 565 void si_flush_dma_cs(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
 566
 567 /* r600_gpu_load.c */
 568 void si_gpu_load_kill_thread(struct si_screen *sscreen);
 569 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
 570 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
 571                         uint64_t begin);
 572
 573 /* r600_perfcounters.c */
 574 void si_perfcounters_destroy(struct si_screen *sscreen);
 575
 576 /* r600_query.c */
 577 void si_init_screen_query_functions(struct si_screen *sscreen);
 578 void si_init_query_functions(struct r600_common_context *rctx);
 579 void si_suspend_queries(struct r600_common_context *ctx);
 580 void si_resume_queries(struct r600_common_context *ctx);
 581
 582 /* r600_texture.c */
 583 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 584                              struct r600_texture *rdst,
 585                              unsigned dst_level, unsigned dstx,
 586                              unsigned dsty, unsigned dstz,
 587                              struct r600_texture *rsrc,
 588                              unsigned src_level,
 589                              const struct pipe_box *src_box);
 590 void si_texture_get_fmask_info(struct si_screen *sscreen,
 591                                struct r600_texture *rtex,
 592                                unsigned nr_samples,
 593                                struct r600_fmask_info *out);
 594 void si_texture_get_cmask_info(struct si_screen *sscreen,
 595                                struct r600_texture *rtex,
 596                                struct r600_cmask_info *out);
 597 void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
 598                                    struct r600_texture *rtex);
 599 void si_texture_discard_cmask(struct si_screen *sscreen,
 600                               struct r600_texture *rtex);
 601 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 602                                    struct pipe_resource *texture,
 603                                    struct r600_texture **staging);
 604 void si_print_texture_info(struct si_screen *sscreen,
 605                            struct r600_texture *rtex, struct u_log_context *log);
 606 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 607                                         const struct pipe_resource *templ);
 608 bool vi_dcc_formats_compatible(enum pipe_format format1,
 609                                enum pipe_format format2);
 610 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 611                                      unsigned level,
 612                                      enum pipe_format view_format);
 613 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 614                                            struct pipe_resource *tex,
 615                                            unsigned level,
 616                                            enum pipe_format view_format);
 617 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
 618                                               struct pipe_resource *texture,
 619                                               const struct pipe_surface *templ,
 620                                               unsigned width0, unsigned height0,
 621                                               unsigned width, unsigned height);
 622 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 623 void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
 624                                 struct r600_texture *tex);
 625 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 626                                  struct r600_texture *tex);
 627 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 628                                 struct r600_texture *tex);
 629 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 630                                              struct r600_texture *tex);
 631 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 632                             struct r600_texture *rtex);
 633 void si_init_screen_texture_functions(struct si_screen *sscreen);
 634 void si_init_context_texture_functions(struct r600_common_context *rctx);
 635
 636
 637 /* Inline helpers. */
 638
 639 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 640 {
 641         return (struct r600_resource*)r;
 642 }
 643
 644 static inline void
 645 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 646 {
 647         pipe_resource_reference((struct pipe_resource **)ptr,
 648                                 (struct pipe_resource *)res);
 649 }
 650
 651 static inline void
 652 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 653 {
 654         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 655 }
 656
 657 static inline bool
 658 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 659 {
 660         return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 661 }
 662
 663 #define R600_ERR(fmt, args...) \
 664         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 665
 666 #endif