src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102 #define DBG_UNSAFE_MATH         (1llu << 49)
 103 #define DBG_NO_DCC_FB           (1llu << 50)
 104
 105 #define R600_MAP_BUFFER_ALIGNMENT 64
 106 #define R600_MAX_VIEWPORTS        16
 107
 108 enum r600_coherency {
 109         R600_COHERENCY_NONE, /* no cache flushes needed */
 110         R600_COHERENCY_SHADER,
 111         R600_COHERENCY_CB_META,
 112 };
 113
 114 #ifdef PIPE_ARCH_BIG_ENDIAN
 115 #define R600_BIG_ENDIAN 1
 116 #else
 117 #define R600_BIG_ENDIAN 0
 118 #endif
 119
 120 struct r600_common_context;
 121 struct r600_perfcounters;
 122 struct tgsi_shader_info;
 123 struct r600_qbo_state;
 124
 125 struct radeon_shader_reloc {
 126         char name[32];
 127         uint64_t offset;
 128 };
 129
 130 struct radeon_shader_binary {
 131         /** Shader code */
 132         unsigned char *code;
 133         unsigned code_size;
 134
 135         /** Config/Context register state that accompanies this shader.
 136          * This is a stream of dword pairs.  First dword contains the
 137          * register address, the second dword contains the value.*/
 138         unsigned char *config;
 139         unsigned config_size;
 140
 141         /** The number of bytes of config information for each global symbol.
 142          */
 143         unsigned config_size_per_symbol;
 144
 145         /** Constant data accessed by the shader.  This will be uploaded
 146          * into a constant buffer. */
 147         unsigned char *rodata;
 148         unsigned rodata_size;
 149
 150         /** List of symbol offsets for the shader */
 151         uint64_t *global_symbol_offsets;
 152         unsigned global_symbol_count;
 153
 154         struct radeon_shader_reloc *relocs;
 155         unsigned reloc_count;
 156
 157         /** Disassembled shader in a string. */
 158         char *disasm_string;
 159         char *llvm_ir_string;
 160 };
 161
 162 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 163 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 164
 165 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 166  * at the moment.
 167  */
 168 struct r600_resource {
 169         struct u_resource               b;
 170
 171         /* Winsys objects. */
 172         struct pb_buffer                *buf;
 173         uint64_t                        gpu_address;
 174         /* Memory usage if the buffer placement is optimal. */
 175         uint64_t                        vram_usage;
 176         uint64_t                        gart_usage;
 177
 178         /* Resource properties. */
 179         uint64_t                        bo_size;
 180         unsigned                        bo_alignment;
 181         enum radeon_bo_domain           domains;
 182         enum radeon_bo_flag             flags;
 183         unsigned                        bind_history;
 184
 185         /* The buffer range which is initialized (with a write transfer,
 186          * streamout, DMA, or as a random access target). The rest of
 187          * the buffer is considered invalid and can be mapped unsynchronized.
 188          *
 189          * This allows unsychronized mapping of a buffer range which hasn't
 190          * been used yet. It's for applications which forget to use
 191          * the unsynchronized map flag and expect the driver to figure it out.
 192          */
 193         struct util_range               valid_buffer_range;
 194
 195         /* For buffers only. This indicates that a write operation has been
 196          * performed by TC L2, but the cache hasn't been flushed.
 197          * Any hw block which doesn't use or bypasses TC L2 should check this
 198          * flag and flush the cache before using the buffer.
 199          *
 200          * For example, TC L2 must be flushed if a buffer which has been
 201          * modified by a shader store instruction is about to be used as
 202          * an index buffer. The reason is that VGT DMA index fetching doesn't
 203          * use TC L2.
 204          */
 205         bool                            TC_L2_dirty;
 206
 207         /* Whether the resource has been exported via resource_get_handle. */
 208         bool                            is_shared;
 209         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 210 };
 211
 212 struct r600_transfer {
 213         struct pipe_transfer            transfer;
 214         struct r600_resource            *staging;
 215         unsigned                        offset;
 216 };
 217
 218 struct r600_fmask_info {
 219         uint64_t offset;
 220         uint64_t size;
 221         unsigned alignment;
 222         unsigned pitch_in_pixels;
 223         unsigned bank_height;
 224         unsigned slice_tile_max;
 225         unsigned tile_mode_index;
 226 };
 227
 228 struct r600_cmask_info {
 229         uint64_t offset;
 230         uint64_t size;
 231         unsigned alignment;
 232         unsigned pitch;
 233         unsigned height;
 234         unsigned xalign;
 235         unsigned yalign;
 236         unsigned slice_tile_max;
 237         unsigned base_address_reg;
 238 };
 239
 240 struct r600_htile_info {
 241         unsigned pitch;
 242         unsigned height;
 243         unsigned xalign;
 244         unsigned yalign;
 245 };
 246
 247 struct r600_texture {
 248         struct r600_resource            resource;
 249
 250         uint64_t                        size;
 251         unsigned                        num_level0_transfers;
 252         bool                            is_depth;
 253         bool                            db_compatible;
 254         bool                            can_sample_z;
 255         bool                            can_sample_s;
 256         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 257         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 258         struct r600_texture             *flushed_depth_texture;
 259         struct radeon_surf              surface;
 260
 261         /* Colorbuffer compression and fast clear. */
 262         struct r600_fmask_info          fmask;
 263         struct r600_cmask_info          cmask;
 264         struct r600_resource            *cmask_buffer;
 265         uint64_t                        dcc_offset; /* 0 = disabled */
 266         unsigned                        cb_color_info; /* fast clear enable bit */
 267         unsigned                        color_clear_value[2];
 268         unsigned                        last_msaa_resolve_target_micro_mode;
 269
 270         /* Depth buffer compression and fast clear. */
 271         struct r600_htile_info          htile;
 272         struct r600_resource            *htile_buffer;
 273         bool                            depth_cleared; /* if it was cleared at least once */
 274         float                           depth_clear_value;
 275         bool                            stencil_cleared; /* if it was cleared at least once */
 276         uint8_t                         stencil_clear_value;
 277
 278         bool                            non_disp_tiling; /* R600-Cayman only */
 279
 280         /* Whether the texture is a displayable back buffer and needs DCC
 281          * decompression, which is expensive. Therefore, it's enabled only
 282          * if statistics suggest that it will pay off and it's allocated
 283          * separately. It can't be bound as a sampler by apps. Limited to
 284          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 285          * the absolute GPUVM address, not the relative one.
 286          */
 287         struct r600_resource            *dcc_separate_buffer;
 288         /* When DCC is temporarily disabled, the separate buffer is here. */
 289         struct r600_resource            *last_dcc_separate_buffer;
 290         /* We need to track DCC dirtiness, because st/dri usually calls
 291          * flush_resource twice per frame (not a bug) and we don't wanna
 292          * decompress DCC twice. Also, the dirty tracking must be done even
 293          * if DCC isn't used, because it's required by the DCC usage analysis
 294          * for a possible future enablement.
 295          */
 296         bool                            separate_dcc_dirty;
 297         /* Statistics gathering for the DCC enablement heuristic. */
 298         bool                            dcc_gather_statistics;
 299         /* Estimate of how much this color buffer is written to in units of
 300          * full-screen draws: ps_invocations / (width * height)
 301          * Shader kills, late Z, and blending with trivial discards make it
 302          * inaccurate (we need to count CB updates, not PS invocations).
 303          */
 304         unsigned                        ps_draw_ratio;
 305         /* The number of clears since the last DCC usage analysis. */
 306         unsigned                        num_slow_clears;
 307
 308         /* Counter that should be non-zero if the texture is bound to a
 309          * framebuffer. Implemented in radeonsi only.
 310          */
 311         uint32_t                        framebuffers_bound;
 312 };
 313
 314 struct r600_surface {
 315         struct pipe_surface             base;
 316         const struct radeon_surf_level  *level_info;
 317
 318         bool color_initialized;
 319         bool depth_initialized;
 320
 321         /* Misc. color flags. */
 322         bool alphatest_bypass;
 323         bool export_16bpc;
 324         bool color_is_int8;
 325
 326         /* Color registers. */
 327         unsigned cb_color_info;
 328         unsigned cb_color_base;
 329         unsigned cb_color_view;
 330         unsigned cb_color_size;         /* R600 only */
 331         unsigned cb_color_dim;          /* EG only */
 332         unsigned cb_color_pitch;        /* EG and later */
 333         unsigned cb_color_slice;        /* EG and later */
 334         unsigned cb_color_attrib;       /* EG and later */
 335         unsigned cb_dcc_control;        /* VI and later */
 336         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 337         unsigned cb_color_fmask_slice;  /* EG and later */
 338         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 339         unsigned cb_color_mask;         /* R600 only */
 340         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 341         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 342         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 343         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 344         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 345         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 346
 347         /* DB registers. */
 348         unsigned db_depth_info;         /* R600 only, then SI and later */
 349         unsigned db_z_info;             /* EG and later */
 350         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 351         unsigned db_depth_view;
 352         unsigned db_depth_size;
 353         unsigned db_depth_slice;        /* EG and later */
 354         unsigned db_stencil_base;       /* EG and later */
 355         unsigned db_stencil_info;       /* EG and later */
 356         unsigned db_prefetch_limit;     /* R600 only */
 357         unsigned db_htile_surface;
 358         unsigned db_htile_data_base;
 359         unsigned db_preload_control;    /* EG and later */
 360 };
 361
 362 struct r600_common_screen {
 363         struct pipe_screen              b;
 364         struct radeon_winsys            *ws;
 365         enum radeon_family              family;
 366         enum chip_class                 chip_class;
 367         struct radeon_info              info;
 368         uint64_t                        debug_flags;
 369         bool                            has_cp_dma;
 370         bool                            has_streamout;
 371
 372         /* Texture filter settings. */
 373         int                             force_aniso; /* -1 = disabled */
 374
 375         /* Auxiliary context. Mainly used to initialize resources.
 376          * It must be locked prior to using and flushed before unlocking. */
 377         struct pipe_context             *aux_context;
 378         pipe_mutex                      aux_context_lock;
 379
 380         /* This must be in the screen, because UE4 uses one context for
 381          * compilation and another one for rendering.
 382          */
 383         unsigned                        num_compilations;
 384         /* Along with ST_DEBUG=precompile, this should show if applications
 385          * are loading shaders on demand. This is a monotonic counter.
 386          */
 387         unsigned                        num_shaders_created;
 388
 389         /* GPU load thread. */
 390         pipe_mutex                      gpu_load_mutex;
 391         pipe_thread                     gpu_load_thread;
 392         unsigned                        gpu_load_counter_busy;
 393         unsigned                        gpu_load_counter_idle;
 394         volatile unsigned               gpu_load_stop_thread; /* bool */
 395
 396         char                            renderer_string[100];
 397
 398         /* Performance counters. */
 399         struct r600_perfcounters        *perfcounters;
 400
 401         /* If pipe_screen wants to re-emit the framebuffer state of all
 402          * contexts, it should atomically increment this. Each context will
 403          * compare this with its own last known value of the counter before
 404          * drawing and re-emit the framebuffer state accordingly.
 405          */
 406         unsigned                        dirty_fb_counter;
 407
 408         /* Atomically increment this counter when an existing texture's
 409          * metadata is enabled or disabled in a way that requires changing
 410          * contexts' compressed texture binding masks.
 411          */
 412         unsigned                        compressed_colortex_counter;
 413
 414         /* Atomically increment this counter when an existing texture's
 415          * backing buffer or tile mode parameters have changed that requires
 416          * recomputation of shader descriptors.
 417          */
 418         unsigned                        dirty_tex_descriptor_counter;
 419
 420         struct {
 421                 /* Context flags to set so that all writes from earlier jobs
 422                  * in the CP are seen by L2 clients.
 423                  */
 424                 unsigned cp_to_L2;
 425
 426                 /* Context flags to set so that all writes from earlier
 427                  * compute jobs are seen by L2 clients.
 428                  */
 429                 unsigned compute_to_L2;
 430         } barrier_flags;
 431
 432         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 433                                       struct r600_texture *rtex,
 434                                       struct radeon_bo_metadata *md);
 435
 436         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 437                                     struct r600_texture *rtex,
 438                                     struct radeon_bo_metadata *md);
 439 };
 440
 441 /* This encapsulates a state or an operation which can emitted into the GPU
 442  * command stream. */
 443 struct r600_atom {
 444         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 445         unsigned                num_dw;
 446         unsigned short          id;
 447 };
 448
 449 struct r600_so_target {
 450         struct pipe_stream_output_target b;
 451
 452         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 453         struct r600_resource    *buf_filled_size;
 454         unsigned                buf_filled_size_offset;
 455         bool                    buf_filled_size_valid;
 456
 457         unsigned                stride_in_dw;
 458 };
 459
 460 struct r600_streamout {
 461         struct r600_atom                begin_atom;
 462         bool                            begin_emitted;
 463         unsigned                        num_dw_for_end;
 464
 465         unsigned                        enabled_mask;
 466         unsigned                        num_targets;
 467         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 468
 469         unsigned                        append_bitmask;
 470         bool                            suspended;
 471
 472         /* External state which comes from the vertex shader,
 473          * it must be set explicitly when binding a shader. */
 474         unsigned                        *stride_in_dw;
 475         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 476
 477         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 478         unsigned                        hw_enabled_mask;
 479
 480         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 481         struct r600_atom                enable_atom;
 482         bool                            streamout_enabled;
 483         bool                            prims_gen_query_enabled;
 484         int                             num_prims_gen_queries;
 485 };
 486
 487 struct r600_signed_scissor {
 488         int minx;
 489         int miny;
 490         int maxx;
 491         int maxy;
 492 };
 493
 494 struct r600_scissors {
 495         struct r600_atom                atom;
 496         unsigned                        dirty_mask;
 497         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 498 };
 499
 500 struct r600_viewports {
 501         struct r600_atom                atom;
 502         unsigned                        dirty_mask;
 503         unsigned                        depth_range_dirty_mask;
 504         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 505         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 506 };
 507
 508 struct r600_ring {
 509         struct radeon_winsys_cs         *cs;
 510         void (*flush)(void *ctx, unsigned flags,
 511                       struct pipe_fence_handle **fence);
 512 };
 513
 514 /* Saved CS data for debugging features. */
 515 struct radeon_saved_cs {
 516         uint32_t                        *ib;
 517         unsigned                        num_dw;
 518
 519         struct radeon_bo_list_item      *bo_list;
 520         unsigned                        bo_count;
 521 };
 522
 523 struct r600_common_context {
 524         struct pipe_context b; /* base class */
 525
 526         struct r600_common_screen       *screen;
 527         struct radeon_winsys            *ws;
 528         struct radeon_winsys_ctx        *ctx;
 529         enum radeon_family              family;
 530         enum chip_class                 chip_class;
 531         struct r600_ring                gfx;
 532         struct r600_ring                dma;
 533         struct pipe_fence_handle        *last_gfx_fence;
 534         struct pipe_fence_handle        *last_sdma_fence;
 535         unsigned                        num_gfx_cs_flushes;
 536         unsigned                        initial_gfx_cs_size;
 537         unsigned                        gpu_reset_counter;
 538         unsigned                        last_dirty_fb_counter;
 539         unsigned                        last_compressed_colortex_counter;
 540         unsigned                        last_dirty_tex_descriptor_counter;
 541
 542         struct u_upload_mgr             *uploader;
 543         struct u_suballocator           *allocator_zeroed_memory;
 544         struct slab_mempool     pool_transfers;
 545
 546         /* Current unaccounted memory usage. */
 547         uint64_t                        vram;
 548         uint64_t                        gtt;
 549
 550         /* States. */
 551         struct r600_streamout           streamout;
 552         struct r600_scissors            scissors;
 553         struct r600_viewports           viewports;
 554         bool                            scissor_enabled;
 555         bool                            clip_halfz;
 556         bool                            vs_writes_viewport_index;
 557         bool                            vs_disables_clipping_viewport;
 558
 559         /* Additional context states. */
 560         unsigned flags; /* flush flags */
 561
 562         /* Queries. */
 563         /* Maintain the list of active queries for pausing between IBs. */
 564         int                             num_occlusion_queries;
 565         int                             num_perfect_occlusion_queries;
 566         struct list_head                active_queries;
 567         unsigned                        num_cs_dw_queries_suspend;
 568         /* Additional hardware info. */
 569         unsigned                        backend_mask;
 570         unsigned                        max_db; /* for OQ */
 571         /* Misc stats. */
 572         unsigned                        num_draw_calls;
 573         unsigned                        num_spill_draw_calls;
 574         unsigned                        num_compute_calls;
 575         unsigned                        num_spill_compute_calls;
 576         unsigned                        num_dma_calls;
 577         unsigned                        num_vs_flushes;
 578         unsigned                        num_ps_flushes;
 579         unsigned                        num_cs_flushes;
 580         uint64_t                        num_alloc_tex_transfer_bytes;
 581         unsigned                        last_tex_ps_draw_ratio; /* for query */
 582
 583         /* Render condition. */
 584         struct r600_atom                render_cond_atom;
 585         struct pipe_query               *render_cond;
 586         unsigned                        render_cond_mode;
 587         bool                            render_cond_invert;
 588         bool                            render_cond_force_off; /* for u_blitter */
 589
 590         /* MSAA sample locations.
 591          * The first index is the sample index.
 592          * The second index is the coordinate: X, Y. */
 593         float                           sample_locations_1x[1][2];
 594         float                           sample_locations_2x[2][2];
 595         float                           sample_locations_4x[4][2];
 596         float                           sample_locations_8x[8][2];
 597         float                           sample_locations_16x[16][2];
 598
 599         /* Statistics gathering for the DCC enablement heuristic. It can't be
 600          * in r600_texture because r600_texture can be shared by multiple
 601          * contexts. This is for back buffers only. We shouldn't get too many
 602          * of those.
 603          *
 604          * X11 DRI3 rotates among a finite set of back buffers. They should
 605          * all fit in this array. If they don't, separate DCC might never be
 606          * enabled by DCC stat gathering.
 607          */
 608         struct {
 609                 struct r600_texture             *tex;
 610                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 611                 struct pipe_query               *ps_stats[3];
 612                 /* If all slots are used and another slot is needed,
 613                  * the least recently used slot is evicted based on this. */
 614                 int64_t                         last_use_timestamp;
 615                 bool                            query_active;
 616         } dcc_stats[5];
 617
 618         /* The list of all texture buffer objects in this context.
 619          * This list is walked when a buffer is invalidated/reallocated and
 620          * the GPU addresses are updated. */
 621         struct list_head                texture_buffers;
 622
 623         struct pipe_debug_callback      debug;
 624
 625         void                            *query_result_shader;
 626
 627         /* Copy one resource to another using async DMA. */
 628         void (*dma_copy)(struct pipe_context *ctx,
 629                          struct pipe_resource *dst,
 630                          unsigned dst_level,
 631                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 632                          struct pipe_resource *src,
 633                          unsigned src_level,
 634                          const struct pipe_box *src_box);
 635
 636         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 637                              uint64_t offset, uint64_t size, unsigned value,
 638                              enum r600_coherency coher);
 639
 640         void (*blit_decompress_depth)(struct pipe_context *ctx,
 641                                       struct r600_texture *texture,
 642                                       struct r600_texture *staging,
 643                                       unsigned first_level, unsigned last_level,
 644                                       unsigned first_layer, unsigned last_layer,
 645                                       unsigned first_sample, unsigned last_sample);
 646
 647         void (*decompress_dcc)(struct pipe_context *ctx,
 648                                struct r600_texture *rtex);
 649
 650         /* Reallocate the buffer and update all resource bindings where
 651          * the buffer is bound, including all resource descriptors. */
 652         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 653
 654         /* Enable or disable occlusion queries. */
 655         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 656
 657         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 658
 659         /* This ensures there is enough space in the command stream. */
 660         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 661                                   bool include_draw_vbo);
 662
 663         void (*set_atom_dirty)(struct r600_common_context *ctx,
 664                                struct r600_atom *atom, bool dirty);
 665
 666         void (*check_vm_faults)(struct r600_common_context *ctx,
 667                                 struct radeon_saved_cs *saved,
 668                                 enum ring_type ring);
 669 };
 670
 671 /* r600_buffer.c */
 672 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 673                                      struct pb_buffer *buf,
 674                                      enum radeon_bo_usage usage);
 675 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 676                                       struct r600_resource *resource,
 677                                       unsigned usage);
 678 void r600_buffer_subdata(struct pipe_context *ctx,
 679                          struct pipe_resource *buffer,
 680                          unsigned usage, unsigned offset,
 681                          unsigned size, const void *data);
 682 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 683                                struct r600_resource *res,
 684                                uint64_t size, unsigned alignment);
 685 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 686                          struct r600_resource *res);
 687 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 688                                          const struct pipe_resource *templ,
 689                                          unsigned alignment);
 690 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 691                                                   unsigned bind,
 692                                                   unsigned usage,
 693                                                   unsigned size,
 694                                                   unsigned alignment);
 695 struct pipe_resource *
 696 r600_buffer_from_user_memory(struct pipe_screen *screen,
 697                              const struct pipe_resource *templ,
 698                              void *user_memory);
 699 void
 700 r600_invalidate_resource(struct pipe_context *ctx,
 701                          struct pipe_resource *resource);
 702
 703 /* r600_common_pipe.c */
 704 void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
 705                           uint64_t va, uint32_t old_value, uint32_t new_value);
 706 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 707 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 708                          uint64_t va, uint32_t ref, uint32_t mask);
 709 void r600_draw_rectangle(struct blitter_context *blitter,
 710                          int x1, int y1, int x2, int y2, float depth,
 711                          enum blitter_attrib_type type,
 712                          const union pipe_color_union *attrib);
 713 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 714                              struct radeon_winsys *ws);
 715 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 716 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 717 void r600_postflush_resume_features(struct r600_common_context *ctx);
 718 bool r600_common_context_init(struct r600_common_context *rctx,
 719                               struct r600_common_screen *rscreen,
 720                               unsigned context_flags);
 721 void r600_common_context_cleanup(struct r600_common_context *rctx);
 722 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 723                           unsigned processor);
 724 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 725                               uint64_t offset, uint64_t size, unsigned value,
 726                               enum r600_coherency coher);
 727 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 728                                                   const struct pipe_resource *templ);
 729 const char *r600_get_llvm_processor_name(enum radeon_family family);
 730 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 731                          struct r600_resource *dst, struct r600_resource *src);
 732 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 733 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 734                     struct radeon_saved_cs *saved);
 735 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 736
 737 /* r600_gpu_load.c */
 738 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 739 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 740 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 741
 742 /* r600_perfcounters.c */
 743 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 744
 745 /* r600_query.c */
 746 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 747 void r600_query_init(struct r600_common_context *rctx);
 748 void r600_suspend_queries(struct r600_common_context *ctx);
 749 void r600_resume_queries(struct r600_common_context *ctx);
 750 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 751
 752 /* r600_streamout.c */
 753 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 754 void r600_set_streamout_targets(struct pipe_context *ctx,
 755                                 unsigned num_targets,
 756                                 struct pipe_stream_output_target **targets,
 757                                 const unsigned *offset);
 758 void r600_emit_streamout_end(struct r600_common_context *rctx);
 759 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 760                                              unsigned type, int diff);
 761 void r600_streamout_init(struct r600_common_context *rctx);
 762
 763 /* r600_test_dma.c */
 764 void r600_test_dma(struct r600_common_screen *rscreen);
 765
 766 /* r600_texture.c */
 767 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 768                                 struct r600_texture *rdst,
 769                                 unsigned dst_level, unsigned dstx,
 770                                 unsigned dsty, unsigned dstz,
 771                                 struct r600_texture *rsrc,
 772                                 unsigned src_level,
 773                                 const struct pipe_box *src_box);
 774 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 775                                  struct r600_texture *rtex,
 776                                  unsigned nr_samples,
 777                                  struct r600_fmask_info *out);
 778 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 779                                  struct r600_texture *rtex,
 780                                  struct r600_cmask_info *out);
 781 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 782                                      struct pipe_resource *texture,
 783                                      struct r600_texture **staging);
 784 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 785 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 786                                         const struct pipe_resource *templ);
 787 bool vi_dcc_formats_compatible(enum pipe_format format1,
 788                                enum pipe_format format2);
 789 void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 790                                            struct pipe_resource *tex,
 791                                            unsigned level,
 792                                            enum pipe_format view_format);
 793 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 794                                                 struct pipe_resource *texture,
 795                                                 const struct pipe_surface *templ,
 796                                                 unsigned width, unsigned height);
 797 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 798 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 799                                  struct r600_texture *tex);
 800 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 801                                 struct r600_texture *tex);
 802 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 803                                              struct r600_texture *tex);
 804 void vi_dcc_clear_level(struct r600_common_context *rctx,
 805                         struct r600_texture *rtex,
 806                         unsigned level, unsigned clear_value);
 807 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 808                                    struct pipe_framebuffer_state *fb,
 809                                    struct r600_atom *fb_state,
 810                                    unsigned *buffers, unsigned *dirty_cbufs,
 811                                    const union pipe_color_union *color);
 812 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 813                               struct r600_texture *rtex);
 814 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 815 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 816
 817 /* r600_viewport.c */
 818 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 819                                             struct pipe_scissor_state *scissor);
 820 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 821                                  bool scissor_enable, bool clip_halfz);
 822 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 823                                           struct tgsi_shader_info *info);
 824 void r600_init_viewport_functions(struct r600_common_context *rctx);
 825
 826 /* cayman_msaa.c */
 827 extern const uint32_t eg_sample_locs_2x[4];
 828 extern const unsigned eg_max_dist_2x;
 829 extern const uint32_t eg_sample_locs_4x[4];
 830 extern const unsigned eg_max_dist_4x;
 831 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 832                                 unsigned sample_index, float *out_value);
 833 void cayman_init_msaa(struct pipe_context *ctx);
 834 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 835 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 836                              int ps_iter_samples, int overrast_samples,
 837                              unsigned sc_mode_cntl_1);
 838
 839
 840 /* Inline helpers. */
 841
 842 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 843 {
 844         return (struct r600_resource*)r;
 845 }
 846
 847 static inline void
 848 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 849 {
 850         pipe_resource_reference((struct pipe_resource **)ptr,
 851                                 (struct pipe_resource *)res);
 852 }
 853
 854 static inline void
 855 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 856 {
 857         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 858 }
 859
 860 static inline void
 861 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 862 {
 863         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 864         struct r600_resource *res = (struct r600_resource *)r;
 865
 866         if (res) {
 867                 /* Add memory usage for need_gfx_cs_space */
 868                 rctx->vram += res->vram_usage;
 869                 rctx->gtt += res->gart_usage;
 870         }
 871 }
 872
 873 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 874 {
 875         return rctx->streamout.streamout_enabled ||
 876                rctx->streamout.prims_gen_query_enabled;
 877 }
 878
 879 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 880 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 881 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 882 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 883
 884 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 885 {
 886         if (filter == PIPE_TEX_FILTER_LINEAR)
 887                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 888                                      : SQ_TEX_XY_FILTER_BILINEAR;
 889         else
 890                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 891                                      : SQ_TEX_XY_FILTER_POINT;
 892 }
 893
 894 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 895 {
 896         if (filter < 2)
 897                 return 0;
 898         if (filter < 4)
 899                 return 1;
 900         if (filter < 8)
 901                 return 2;
 902         if (filter < 16)
 903                 return 3;
 904         return 4;
 905 }
 906
 907 static inline unsigned r600_wavefront_size(enum radeon_family family)
 908 {
 909         switch (family) {
 910         case CHIP_RV610:
 911         case CHIP_RS780:
 912         case CHIP_RV620:
 913         case CHIP_RS880:
 914                 return 16;
 915         case CHIP_RV630:
 916         case CHIP_RV635:
 917         case CHIP_RV730:
 918         case CHIP_RV710:
 919         case CHIP_PALM:
 920         case CHIP_CEDAR:
 921                 return 32;
 922         default:
 923                 return 64;
 924         }
 925 }
 926
 927 static inline enum radeon_bo_priority
 928 r600_get_sampler_view_priority(struct r600_resource *res)
 929 {
 930         if (res->b.b.target == PIPE_BUFFER)
 931                 return RADEON_PRIO_SAMPLER_BUFFER;
 932
 933         if (res->b.b.nr_samples > 1)
 934                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 935
 936         return RADEON_PRIO_SAMPLER_TEXTURE;
 937 }
 938
 939 static inline bool
 940 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 941 {
 942         return (stencil_sampler && tex->can_sample_s) ||
 943                (!stencil_sampler && tex->can_sample_z);
 944 }
 945
 946 #define COMPUTE_DBG(rscreen, fmt, args...) \
 947         do { \
 948                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 949         } while (0);
 950
 951 #define R600_ERR(fmt, args...) \
 952         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 953
 954 /* For MSAA sample positions. */
 955 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 956         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 957         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 958         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 959          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 960
 961 #endif