2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.level
[level
].slice_size
+
185 (box
->y
/ rtex
->surface
.blk_h
*
186 rtex
->surface
.level
[level
].nblk_x
+
187 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
193 enum radeon_surf_mode array_mode
,
194 unsigned pitch_in_bytes_override
,
198 bool is_flushed_depth
,
199 bool tc_compatible_htile
)
201 const struct util_format_description
*desc
=
202 util_format_description(ptex
->format
);
203 bool is_depth
, is_stencil
;
205 unsigned i
, bpe
, flags
= 0;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 bpe
= 4; /* stencil is allocated separately on evergreen */
214 bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
221 if (!is_flushed_depth
&& is_depth
) {
222 flags
|= RADEON_SURF_ZBUFFER
;
224 if (tc_compatible_htile
&&
225 array_mode
== RADEON_SURF_MODE_2D
) {
226 /* TC-compatible HTILE only supports Z32_FLOAT.
227 * Promote Z16 to Z32. DB->CB copies will convert
228 * the format for transfers.
231 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
235 flags
|= RADEON_SURF_SBUFFER
;
238 if (rscreen
->chip_class
>= VI
&&
239 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
240 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
241 flags
|= RADEON_SURF_DISABLE_DCC
;
243 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
244 /* This should catch bugs in gallium users setting incorrect flags. */
245 assert(ptex
->nr_samples
<= 1 &&
246 ptex
->array_size
== 1 &&
248 ptex
->last_level
== 0 &&
249 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
251 flags
|= RADEON_SURF_SCANOUT
;
255 flags
|= RADEON_SURF_IMPORTED
;
256 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
257 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
259 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
260 array_mode
, surface
);
265 if (pitch_in_bytes_override
&&
266 pitch_in_bytes_override
!= surface
->level
[0].nblk_x
* bpe
) {
267 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
270 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
271 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
275 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
276 surface
->level
[i
].offset
+= offset
;
281 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
282 struct radeon_bo_metadata
*metadata
)
284 struct radeon_surf
*surface
= &rtex
->surface
;
286 memset(metadata
, 0, sizeof(*metadata
));
287 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
288 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
289 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
290 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
291 metadata
->pipe_config
= surface
->pipe_config
;
292 metadata
->bankw
= surface
->bankw
;
293 metadata
->bankh
= surface
->bankh
;
294 metadata
->tile_split
= surface
->tile_split
;
295 metadata
->mtilea
= surface
->mtilea
;
296 metadata
->num_banks
= surface
->num_banks
;
297 metadata
->stride
= surface
->level
[0].nblk_x
* surface
->bpe
;
298 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
301 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
302 struct r600_texture
*rtex
)
304 struct r600_common_screen
*rscreen
= rctx
->screen
;
305 struct pipe_context
*ctx
= &rctx
->b
;
307 if (ctx
== rscreen
->aux_context
)
308 pipe_mutex_lock(rscreen
->aux_context_lock
);
310 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
311 ctx
->flush(ctx
, NULL
, 0);
313 if (ctx
== rscreen
->aux_context
)
314 pipe_mutex_unlock(rscreen
->aux_context_lock
);
317 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
318 struct r600_texture
*rtex
)
320 if (!rtex
->cmask
.size
)
323 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
326 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
327 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
328 rtex
->dirty_level_mask
= 0;
330 if (rscreen
->chip_class
>= SI
)
331 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
333 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
335 if (rtex
->cmask_buffer
!= &rtex
->resource
)
336 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
338 /* Notify all contexts about the change. */
339 p_atomic_inc(&rscreen
->dirty_tex_counter
);
340 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
343 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
345 /* We can't disable DCC if it can be written by another process. */
346 return rtex
->dcc_offset
&&
347 (!rtex
->resource
.is_shared
||
348 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
351 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
352 struct r600_texture
*rtex
)
354 if (!r600_can_disable_dcc(rtex
))
357 assert(rtex
->dcc_separate_buffer
== NULL
);
360 rtex
->dcc_offset
= 0;
362 /* Notify all contexts about the change. */
363 p_atomic_inc(&rscreen
->dirty_tex_counter
);
368 * Disable DCC for the texture. (first decompress, then discard metadata).
370 * There is unresolved multi-context synchronization issue between
371 * screen::aux_context and the current context. If applications do this with
372 * multiple contexts, it's already undefined behavior for them and we don't
373 * have to worry about that. The scenario is:
375 * If context 1 disables DCC and context 2 has queued commands that write
376 * to the texture via CB with DCC enabled, and the order of operations is
378 * context 2 queues draw calls rendering to the texture, but doesn't flush
379 * context 1 disables DCC and flushes
380 * context 1 & 2 reset descriptors and FB state
381 * context 2 flushes (new compressed tiles written by the draw calls)
382 * context 1 & 2 read garbage, because DCC is disabled, yet there are
385 * \param rctx the current context if you have one, or rscreen->aux_context
388 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
389 struct r600_texture
*rtex
)
391 struct r600_common_screen
*rscreen
= rctx
->screen
;
393 if (!r600_can_disable_dcc(rtex
))
396 if (&rctx
->b
== rscreen
->aux_context
)
397 pipe_mutex_lock(rscreen
->aux_context_lock
);
399 /* Decompress DCC. */
400 rctx
->decompress_dcc(&rctx
->b
, rtex
);
401 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
403 if (&rctx
->b
== rscreen
->aux_context
)
404 pipe_mutex_unlock(rscreen
->aux_context_lock
);
406 return r600_texture_discard_dcc(rscreen
, rtex
);
409 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
410 struct r600_texture
*rtex
,
411 bool invalidate_storage
)
413 struct pipe_screen
*screen
= rctx
->b
.screen
;
414 struct r600_texture
*new_tex
;
415 struct pipe_resource templ
= rtex
->resource
.b
.b
;
418 templ
.bind
|= PIPE_BIND_LINEAR
;
420 /* r600g doesn't react to dirty_tex_descriptor_counter */
421 if (rctx
->chip_class
< SI
)
424 if (rtex
->resource
.is_shared
||
425 rtex
->surface
.is_linear
)
428 /* This fails with MSAA, depth, and compressed textures. */
429 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
430 RADEON_SURF_MODE_LINEAR_ALIGNED
)
433 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
437 /* Copy the pixels to the new texture. */
438 if (!invalidate_storage
) {
439 for (i
= 0; i
<= templ
.last_level
; i
++) {
443 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
444 util_max_layer(&templ
, i
) + 1, &box
);
446 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
447 &rtex
->resource
.b
.b
, i
, &box
);
451 r600_texture_discard_cmask(rctx
->screen
, rtex
);
452 r600_texture_discard_dcc(rctx
->screen
, rtex
);
454 /* Replace the structure fields of rtex. */
455 rtex
->resource
.b
.b
.bind
= templ
.bind
;
456 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
457 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
458 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
459 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
460 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
461 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
462 rtex
->resource
.domains
= new_tex
->resource
.domains
;
463 rtex
->resource
.flags
= new_tex
->resource
.flags
;
464 rtex
->size
= new_tex
->size
;
465 rtex
->surface
= new_tex
->surface
;
466 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
467 rtex
->cb_color_info
= new_tex
->cb_color_info
;
468 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
470 assert(!rtex
->htile_buffer
);
471 assert(!rtex
->cmask
.size
);
472 assert(!rtex
->fmask
.size
);
473 assert(!rtex
->dcc_offset
);
474 assert(!rtex
->is_depth
);
476 r600_texture_reference(&new_tex
, NULL
);
478 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
481 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
482 struct pipe_context
*ctx
,
483 struct pipe_resource
*resource
,
484 struct winsys_handle
*whandle
,
487 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
488 struct r600_common_context
*rctx
= (struct r600_common_context
*)
489 (ctx
? ctx
: rscreen
->aux_context
);
490 struct r600_resource
*res
= (struct r600_resource
*)resource
;
491 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
492 struct radeon_bo_metadata metadata
;
493 bool update_metadata
= false;
495 /* This is not supported now, but it might be required for OpenCL
496 * interop in the future.
498 if (resource
->target
!= PIPE_BUFFER
&&
499 (resource
->nr_samples
> 1 || rtex
->is_depth
))
502 if (resource
->target
!= PIPE_BUFFER
) {
503 /* Since shader image stores don't support DCC on VI,
504 * disable it for external clients that want write
507 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
508 if (r600_texture_disable_dcc(rctx
, rtex
))
509 update_metadata
= true;
512 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
513 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
514 /* Eliminate fast clear (both CMASK and DCC) */
515 r600_eliminate_fast_color_clear(rctx
, rtex
);
517 /* Disable CMASK if flush_resource isn't going
520 if (rtex
->cmask
.size
)
521 r600_texture_discard_cmask(rscreen
, rtex
);
525 if (!res
->is_shared
|| update_metadata
) {
526 r600_texture_init_metadata(rtex
, &metadata
);
527 if (rscreen
->query_opaque_metadata
)
528 rscreen
->query_opaque_metadata(rscreen
, rtex
,
531 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
535 if (res
->is_shared
) {
536 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
539 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
540 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
541 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 res
->is_shared
= true;
544 res
->external_usage
= usage
;
547 return rscreen
->ws
->buffer_get_handle(res
->buf
,
548 rtex
->surface
.level
[0].nblk_x
*
550 rtex
->surface
.level
[0].offset
,
551 rtex
->surface
.level
[0].slice_size
,
555 static void r600_texture_destroy(struct pipe_screen
*screen
,
556 struct pipe_resource
*ptex
)
558 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
559 struct r600_resource
*resource
= &rtex
->resource
;
561 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
563 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
564 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
565 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
567 pb_reference(&resource
->buf
, NULL
);
568 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
569 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
573 static const struct u_resource_vtbl r600_texture_vtbl
;
575 /* The number of samples can be specified independently of the texture. */
576 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
577 struct r600_texture
*rtex
,
579 struct r600_fmask_info
*out
)
581 /* FMASK is allocated like an ordinary texture. */
582 struct pipe_resource templ
= rtex
->resource
.b
.b
;
583 struct radeon_surf fmask
= {};
586 memset(out
, 0, sizeof(*out
));
588 templ
.nr_samples
= 1;
589 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
591 if (rscreen
->chip_class
<= CAYMAN
) {
592 /* Use the same parameters and tile mode. */
593 fmask
.bankw
= rtex
->surface
.bankw
;
594 fmask
.bankh
= rtex
->surface
.bankh
;
595 fmask
.mtilea
= rtex
->surface
.mtilea
;
596 fmask
.tile_split
= rtex
->surface
.tile_split
;
602 switch (nr_samples
) {
611 R600_ERR("Invalid sample count for FMASK allocation.\n");
615 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
616 * This can be fixed by writing a separate FMASK allocator specifically
617 * for R600-R700 asics. */
618 if (rscreen
->chip_class
<= R700
) {
622 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
623 RADEON_SURF_MODE_2D
, &fmask
)) {
624 R600_ERR("Got error in surface_init while allocating FMASK.\n");
628 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
630 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
631 if (out
->slice_tile_max
)
632 out
->slice_tile_max
-= 1;
634 out
->tile_mode_index
= fmask
.tiling_index
[0];
635 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
636 out
->bank_height
= fmask
.bankh
;
637 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
638 out
->size
= fmask
.surf_size
;
641 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
642 struct r600_texture
*rtex
)
644 r600_texture_get_fmask_info(rscreen
, rtex
,
645 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
647 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
648 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
651 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
652 struct r600_texture
*rtex
,
653 struct r600_cmask_info
*out
)
655 unsigned cmask_tile_width
= 8;
656 unsigned cmask_tile_height
= 8;
657 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
658 unsigned element_bits
= 4;
659 unsigned cmask_cache_bits
= 1024;
660 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
661 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
663 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
664 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
665 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
666 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
667 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
669 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
670 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
672 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
673 unsigned slice_bytes
=
674 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
676 assert(macro_tile_width
% 128 == 0);
677 assert(macro_tile_height
% 128 == 0);
679 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
680 out
->alignment
= MAX2(256, base_align
);
681 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
682 align(slice_bytes
, base_align
);
685 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
686 struct r600_texture
*rtex
,
687 struct r600_cmask_info
*out
)
689 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
690 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
691 unsigned cl_width
, cl_height
;
706 case 16: /* Hawaii */
715 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
717 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
718 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
719 unsigned slice_elements
= (width
* height
) / (8*8);
721 /* Each element of CMASK is a nibble. */
722 unsigned slice_bytes
= slice_elements
/ 2;
724 out
->slice_tile_max
= (width
* height
) / (128*128);
725 if (out
->slice_tile_max
)
726 out
->slice_tile_max
-= 1;
728 out
->alignment
= MAX2(256, base_align
);
729 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
730 align(slice_bytes
, base_align
);
733 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
734 struct r600_texture
*rtex
)
736 if (rscreen
->chip_class
>= SI
) {
737 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
739 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
742 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
743 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
745 if (rscreen
->chip_class
>= SI
)
746 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
748 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
751 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
752 struct r600_texture
*rtex
)
754 if (rtex
->cmask_buffer
)
757 assert(rtex
->cmask
.size
== 0);
759 if (rscreen
->chip_class
>= SI
) {
760 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
762 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
765 rtex
->cmask_buffer
= (struct r600_resource
*)
766 r600_aligned_buffer_create(&rscreen
->b
,
767 R600_RESOURCE_FLAG_UNMAPPABLE
,
770 rtex
->cmask
.alignment
);
771 if (rtex
->cmask_buffer
== NULL
) {
772 rtex
->cmask
.size
= 0;
776 /* update colorbuffer state bits */
777 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
779 if (rscreen
->chip_class
>= SI
)
780 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
782 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
784 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
787 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
788 struct r600_texture
*rtex
)
790 unsigned cl_width
, cl_height
, width
, height
;
791 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
792 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
794 rtex
->surface
.htile_size
= 0;
796 if (rscreen
->chip_class
<= EVERGREEN
&&
797 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
800 /* HW bug on R6xx. */
801 if (rscreen
->chip_class
== R600
&&
802 (rtex
->resource
.b
.b
.width0
> 7680 ||
803 rtex
->resource
.b
.b
.height0
> 7680))
806 /* HTILE is broken with 1D tiling on old kernels and CIK. */
807 if (rscreen
->chip_class
>= CIK
&&
808 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
809 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
812 /* Overalign HTILE on P2 configs to work around GPU hangs in
813 * piglit/depthstencil-render-miplevels 585.
815 * This has been confirmed to help Kabini & Stoney, where the hangs
816 * are always reproducible. I think I have seen the test hang
817 * on Carrizo too, though it was very rare there.
819 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
848 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
849 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
851 slice_elements
= (width
* height
) / (8 * 8);
852 slice_bytes
= slice_elements
* 4;
854 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
855 base_align
= num_pipes
* pipe_interleave_bytes
;
857 rtex
->surface
.htile_alignment
= base_align
;
858 rtex
->surface
.htile_size
=
859 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
860 align(slice_bytes
, base_align
);
863 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
864 struct r600_texture
*rtex
)
866 uint32_t clear_value
;
868 if (rtex
->tc_compatible_htile
) {
869 clear_value
= 0x0000030F;
871 r600_texture_get_htile_size(rscreen
, rtex
);
875 if (!rtex
->surface
.htile_size
)
878 rtex
->htile_buffer
= (struct r600_resource
*)
879 r600_aligned_buffer_create(&rscreen
->b
,
880 R600_RESOURCE_FLAG_UNMAPPABLE
,
882 rtex
->surface
.htile_size
,
883 rtex
->surface
.htile_alignment
);
884 if (rtex
->htile_buffer
== NULL
) {
885 /* this is not a fatal error as we can still keep rendering
886 * without htile buffer */
887 R600_ERR("Failed to create buffer object for htile buffer.\n");
889 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
890 0, rtex
->surface
.htile_size
,
895 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
899 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
900 "blk_h=%u, array_size=%u, last_level=%u, "
901 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
902 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
903 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
905 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
906 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
907 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
909 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
910 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
911 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.bankw
,
912 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
913 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
914 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
916 if (rtex
->fmask
.size
)
917 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
918 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
919 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
920 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
921 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
923 if (rtex
->cmask
.size
)
924 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
925 "slice_tile_max=%u\n",
926 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
927 rtex
->cmask
.slice_tile_max
);
929 if (rtex
->htile_buffer
)
930 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
931 rtex
->htile_buffer
->b
.b
.width0
,
932 rtex
->htile_buffer
->buf
->alignment
,
933 rtex
->tc_compatible_htile
);
935 if (rtex
->dcc_offset
) {
936 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
937 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
938 rtex
->surface
.dcc_alignment
);
939 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
940 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
941 "fast_clear_size=%"PRIu64
"\n",
942 i
, i
< rtex
->surface
.num_dcc_levels
,
943 rtex
->surface
.level
[i
].dcc_offset
,
944 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
947 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
948 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
949 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
950 "mode=%u, tiling_index = %u\n",
951 i
, rtex
->surface
.level
[i
].offset
,
952 rtex
->surface
.level
[i
].slice_size
,
953 u_minify(rtex
->resource
.b
.b
.width0
, i
),
954 u_minify(rtex
->resource
.b
.b
.height0
, i
),
955 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
956 rtex
->surface
.level
[i
].nblk_x
,
957 rtex
->surface
.level
[i
].nblk_y
,
958 rtex
->surface
.level
[i
].mode
,
959 rtex
->surface
.tiling_index
[i
]);
961 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
962 fprintf(f
, " StencilLayout: tilesplit=%u\n",
963 rtex
->surface
.stencil_tile_split
);
964 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
965 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
966 "slice_size=%"PRIu64
", npix_x=%u, "
967 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
968 "mode=%u, tiling_index = %u\n",
969 i
, rtex
->surface
.stencil_level
[i
].offset
,
970 rtex
->surface
.stencil_level
[i
].slice_size
,
971 u_minify(rtex
->resource
.b
.b
.width0
, i
),
972 u_minify(rtex
->resource
.b
.b
.height0
, i
),
973 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
974 rtex
->surface
.stencil_level
[i
].nblk_x
,
975 rtex
->surface
.stencil_level
[i
].nblk_y
,
976 rtex
->surface
.stencil_level
[i
].mode
,
977 rtex
->surface
.stencil_tiling_index
[i
]);
982 /* Common processing for r600_texture_create and r600_texture_from_handle */
983 static struct r600_texture
*
984 r600_texture_create_object(struct pipe_screen
*screen
,
985 const struct pipe_resource
*base
,
986 struct pb_buffer
*buf
,
987 struct radeon_surf
*surface
)
989 struct r600_texture
*rtex
;
990 struct r600_resource
*resource
;
991 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
993 rtex
= CALLOC_STRUCT(r600_texture
);
997 resource
= &rtex
->resource
;
998 resource
->b
.b
= *base
;
999 resource
->b
.b
.next
= NULL
;
1000 resource
->b
.vtbl
= &r600_texture_vtbl
;
1001 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1002 resource
->b
.b
.screen
= screen
;
1004 /* don't include stencil-only formats which we don't support for rendering */
1005 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1007 rtex
->surface
= *surface
;
1008 rtex
->size
= rtex
->surface
.surf_size
;
1010 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1011 (rtex
->surface
.flags
&
1012 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1014 /* TC-compatible HTILE only supports Z32_FLOAT. */
1015 if (rtex
->tc_compatible_htile
)
1016 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1018 rtex
->db_render_format
= base
->format
;
1020 /* Tiled depth textures utilize the non-displayable tile order.
1021 * This must be done after r600_setup_surface.
1022 * Applies to R600-Cayman. */
1023 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1024 /* Applies to GCN. */
1025 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1027 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1028 * between frames, so the only thing that can enable separate DCC
1029 * with DRI2 is multiple slow clears within a frame.
1031 rtex
->ps_draw_ratio
= 0;
1033 if (rtex
->is_depth
) {
1034 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1035 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1036 rscreen
->chip_class
>= EVERGREEN
) {
1037 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1038 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1040 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1041 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1042 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1043 rtex
->can_sample_z
= true;
1046 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1047 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1048 rtex
->db_compatible
= true;
1050 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1051 r600_texture_allocate_htile(rscreen
, rtex
);
1054 if (base
->nr_samples
> 1) {
1056 r600_texture_allocate_fmask(rscreen
, rtex
);
1057 r600_texture_allocate_cmask(rscreen
, rtex
);
1058 rtex
->cmask_buffer
= &rtex
->resource
;
1060 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1066 /* Shared textures must always set up DCC here.
1067 * If it's not present, it will be disabled by
1068 * apply_opaque_metadata later.
1070 if (rtex
->surface
.dcc_size
&&
1071 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1072 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1073 /* Reserve space for the DCC buffer. */
1074 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1075 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1079 /* Now create the backing buffer. */
1081 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1082 rtex
->surface
.surf_alignment
);
1084 resource
->flags
|= RADEON_FLAG_HANDLE
;
1086 if (!r600_alloc_resource(rscreen
, resource
)) {
1091 resource
->buf
= buf
;
1092 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1093 resource
->bo_size
= buf
->size
;
1094 resource
->bo_alignment
= buf
->alignment
;
1095 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1096 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1097 resource
->vram_usage
= buf
->size
;
1098 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1099 resource
->gart_usage
= buf
->size
;
1102 if (rtex
->cmask
.size
) {
1103 /* Initialize the cmask to 0xCC (= compressed state). */
1104 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1105 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1109 /* Initialize DCC only if the texture is not being imported. */
1110 if (!buf
&& rtex
->dcc_offset
) {
1111 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1113 rtex
->surface
.dcc_size
,
1117 /* Initialize the CMASK base register value. */
1118 rtex
->cmask
.base_address_reg
=
1119 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1121 if (rscreen
->debug_flags
& DBG_VM
) {
1122 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1123 rtex
->resource
.gpu_address
,
1124 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1125 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1126 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1129 if (rscreen
->debug_flags
& DBG_TEX
) {
1131 r600_print_texture_info(rtex
, stdout
);
1138 static enum radeon_surf_mode
1139 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1140 const struct pipe_resource
*templ
)
1142 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1143 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1145 /* MSAA resources must be 2D tiled. */
1146 if (templ
->nr_samples
> 1)
1147 return RADEON_SURF_MODE_2D
;
1149 /* Transfer resources should be linear. */
1150 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1151 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1153 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1154 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1155 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1156 (templ
->target
== PIPE_TEXTURE_2D
||
1157 templ
->target
== PIPE_TEXTURE_3D
))
1158 force_tiling
= true;
1160 /* Handle common candidates for the linear mode.
1161 * Compressed textures and DB surfaces must always be tiled.
1163 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1164 (!util_format_is_depth_or_stencil(templ
->format
) ||
1165 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1166 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1167 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1169 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1170 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1171 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1173 /* Cursors are linear on SI.
1174 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1175 if (rscreen
->chip_class
>= SI
&&
1176 (templ
->bind
& PIPE_BIND_CURSOR
))
1177 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1179 if (templ
->bind
& PIPE_BIND_LINEAR
)
1180 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1182 /* Textures with a very small height are recommended to be linear. */
1183 if (templ
->target
== PIPE_TEXTURE_1D
||
1184 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1185 /* Only very thin and long 2D textures should benefit from
1186 * linear_aligned. */
1187 (templ
->width0
> 8 && templ
->height0
<= 2))
1188 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1190 /* Textures likely to be mapped often. */
1191 if (templ
->usage
== PIPE_USAGE_STAGING
||
1192 templ
->usage
== PIPE_USAGE_STREAM
)
1193 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1196 /* Make small textures 1D tiled. */
1197 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1198 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1199 return RADEON_SURF_MODE_1D
;
1201 /* The allocator will switch to 1D if needed. */
1202 return RADEON_SURF_MODE_2D
;
1205 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1206 const struct pipe_resource
*templ
)
1208 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1209 struct radeon_surf surface
= {0};
1210 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1211 bool tc_compatible_htile
=
1212 rscreen
->chip_class
>= VI
&&
1213 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1214 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1215 !is_flushed_depth
&&
1216 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1217 util_format_is_depth_or_stencil(templ
->format
);
1221 r
= r600_init_surface(rscreen
, &surface
, templ
,
1222 r600_choose_tiling(rscreen
, templ
), 0, 0,
1223 false, false, is_flushed_depth
,
1224 tc_compatible_htile
);
1229 return (struct pipe_resource
*)
1230 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1233 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1234 const struct pipe_resource
*templ
,
1235 struct winsys_handle
*whandle
,
1238 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1239 struct pb_buffer
*buf
= NULL
;
1240 unsigned stride
= 0, offset
= 0;
1241 unsigned array_mode
;
1242 struct radeon_surf surface
;
1244 struct radeon_bo_metadata metadata
= {};
1245 struct r600_texture
*rtex
;
1247 /* Support only 2D textures without mipmaps */
1248 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1249 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1252 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1256 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1258 surface
.pipe_config
= metadata
.pipe_config
;
1259 surface
.bankw
= metadata
.bankw
;
1260 surface
.bankh
= metadata
.bankh
;
1261 surface
.tile_split
= metadata
.tile_split
;
1262 surface
.mtilea
= metadata
.mtilea
;
1263 surface
.num_banks
= metadata
.num_banks
;
1265 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1266 array_mode
= RADEON_SURF_MODE_2D
;
1267 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1268 array_mode
= RADEON_SURF_MODE_1D
;
1270 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1272 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1273 offset
, true, metadata
.scanout
, false, false);
1278 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1282 rtex
->resource
.is_shared
= true;
1283 rtex
->resource
.external_usage
= usage
;
1285 if (rscreen
->apply_opaque_metadata
)
1286 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1288 return &rtex
->resource
.b
.b
;
1291 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1292 struct pipe_resource
*texture
,
1293 struct r600_texture
**staging
)
1295 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1296 struct pipe_resource resource
;
1297 struct r600_texture
**flushed_depth_texture
= staging
?
1298 staging
: &rtex
->flushed_depth_texture
;
1299 enum pipe_format pipe_format
= texture
->format
;
1302 if (rtex
->flushed_depth_texture
)
1303 return true; /* it's ready */
1305 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1306 switch (pipe_format
) {
1307 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1308 /* Save memory by not allocating the S plane. */
1309 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1311 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1312 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1313 /* Save memory bandwidth by not copying the
1314 * stencil part during flush.
1316 * This potentially increases memory bandwidth
1317 * if an application uses both Z and S texturing
1318 * simultaneously (a flushed Z24S8 texture
1319 * would be stored compactly), but how often
1320 * does that really happen?
1322 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1326 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1327 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1329 /* DB->CB copies to an 8bpp surface don't work. */
1330 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1334 memset(&resource
, 0, sizeof(resource
));
1335 resource
.target
= texture
->target
;
1336 resource
.format
= pipe_format
;
1337 resource
.width0
= texture
->width0
;
1338 resource
.height0
= texture
->height0
;
1339 resource
.depth0
= texture
->depth0
;
1340 resource
.array_size
= texture
->array_size
;
1341 resource
.last_level
= texture
->last_level
;
1342 resource
.nr_samples
= texture
->nr_samples
;
1343 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1344 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1345 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1348 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1350 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1351 if (*flushed_depth_texture
== NULL
) {
1352 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1356 (*flushed_depth_texture
)->non_disp_tiling
= false;
1361 * Initialize the pipe_resource descriptor to be of the same size as the box,
1362 * which is supposed to hold a subregion of the texture "orig" at the given
1365 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1366 struct pipe_resource
*orig
,
1367 const struct pipe_box
*box
,
1368 unsigned level
, unsigned flags
)
1370 memset(res
, 0, sizeof(*res
));
1371 res
->format
= orig
->format
;
1372 res
->width0
= box
->width
;
1373 res
->height0
= box
->height
;
1375 res
->array_size
= 1;
1376 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1379 /* We must set the correct texture target and dimensions for a 3D box. */
1380 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1381 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1382 res
->array_size
= box
->depth
;
1384 res
->target
= PIPE_TEXTURE_2D
;
1388 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1389 struct r600_texture
*rtex
,
1390 unsigned transfer_usage
,
1391 const struct pipe_box
*box
)
1393 /* r600g doesn't react to dirty_tex_descriptor_counter */
1394 return rscreen
->chip_class
>= SI
&&
1395 !rtex
->resource
.is_shared
&&
1396 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1397 rtex
->resource
.b
.b
.last_level
== 0 &&
1398 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1399 box
->x
, box
->y
, box
->z
,
1400 box
->width
, box
->height
,
1404 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1405 struct r600_texture
*rtex
)
1407 struct r600_common_screen
*rscreen
= rctx
->screen
;
1409 /* There is no point in discarding depth and tiled buffers. */
1410 assert(!rtex
->is_depth
);
1411 assert(rtex
->surface
.is_linear
);
1413 /* Reallocate the buffer in the same pipe_resource. */
1414 r600_alloc_resource(rscreen
, &rtex
->resource
);
1416 /* Initialize the CMASK base address (needed even without CMASK). */
1417 rtex
->cmask
.base_address_reg
=
1418 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1420 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1422 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1425 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1426 struct pipe_resource
*texture
,
1429 const struct pipe_box
*box
,
1430 struct pipe_transfer
**ptransfer
)
1432 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1433 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1434 struct r600_transfer
*trans
;
1435 struct r600_resource
*buf
;
1436 unsigned offset
= 0;
1438 bool use_staging_texture
= false;
1440 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1441 assert(box
->width
&& box
->height
&& box
->depth
);
1443 /* Depth textures use staging unconditionally. */
1444 if (!rtex
->is_depth
) {
1445 /* Degrade the tile mode if we get too many transfers on APUs.
1446 * On dGPUs, the staging texture is always faster.
1447 * Only count uploads that are at least 4x4 pixels large.
1449 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1451 box
->width
>= 4 && box
->height
>= 4 &&
1452 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1453 bool can_invalidate
=
1454 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1457 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1461 /* Tiled textures need to be converted into a linear texture for CPU
1462 * access. The staging texture is always linear and is placed in GART.
1464 * Reading from VRAM or GTT WC is slow, always use the staging
1465 * texture in this case.
1467 * Use the staging texture for uploads if the underlying BO
1470 if (!rtex
->surface
.is_linear
)
1471 use_staging_texture
= true;
1472 else if (usage
& PIPE_TRANSFER_READ
)
1473 use_staging_texture
=
1474 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1475 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1476 /* Write & linear only: */
1477 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1478 RADEON_USAGE_READWRITE
) ||
1479 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1480 RADEON_USAGE_READWRITE
)) {
1482 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1484 r600_texture_invalidate_storage(rctx
, rtex
);
1486 use_staging_texture
= true;
1490 trans
= CALLOC_STRUCT(r600_transfer
);
1493 trans
->transfer
.resource
= texture
;
1494 trans
->transfer
.level
= level
;
1495 trans
->transfer
.usage
= usage
;
1496 trans
->transfer
.box
= *box
;
1498 if (rtex
->is_depth
) {
1499 struct r600_texture
*staging_depth
;
1501 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1502 /* MSAA depth buffers need to be converted to single sample buffers.
1504 * Mapping MSAA depth buffers can occur if ReadPixels is called
1505 * with a multisample GLX visual.
1507 * First downsample the depth buffer to a temporary texture,
1508 * then decompress the temporary one to staging.
1510 * Only the region being mapped is transfered.
1512 struct pipe_resource resource
;
1514 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1516 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1517 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1522 if (usage
& PIPE_TRANSFER_READ
) {
1523 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1525 R600_ERR("failed to create a temporary depth texture\n");
1530 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1531 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1532 0, 0, 0, box
->depth
, 0, 0);
1533 pipe_resource_reference(&temp
, NULL
);
1537 /* XXX: only readback the rectangle which is being mapped? */
1538 /* XXX: when discard is true, no need to read back from depth texture */
1539 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1540 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1545 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1547 box
->z
, box
->z
+ box
->depth
- 1,
1550 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1553 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].nblk_x
*
1554 staging_depth
->surface
.bpe
;
1555 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1556 trans
->staging
= (struct r600_resource
*)staging_depth
;
1557 buf
= trans
->staging
;
1558 } else if (use_staging_texture
) {
1559 struct pipe_resource resource
;
1560 struct r600_texture
*staging
;
1562 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1563 R600_RESOURCE_FLAG_TRANSFER
);
1564 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1565 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1567 /* Create the temporary texture. */
1568 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1570 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1574 trans
->staging
= &staging
->resource
;
1575 trans
->transfer
.stride
= staging
->surface
.level
[0].nblk_x
*
1576 staging
->surface
.bpe
;
1577 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1579 if (usage
& PIPE_TRANSFER_READ
)
1580 r600_copy_to_staging_texture(ctx
, trans
);
1582 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1584 buf
= trans
->staging
;
1586 /* the resource is mapped directly */
1587 trans
->transfer
.stride
= rtex
->surface
.level
[level
].nblk_x
*
1589 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1590 offset
= r600_texture_get_offset(rtex
, level
, box
);
1591 buf
= &rtex
->resource
;
1594 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1595 r600_resource_reference(&trans
->staging
, NULL
);
1600 *ptransfer
= &trans
->transfer
;
1601 return map
+ offset
;
1604 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1605 struct pipe_transfer
* transfer
)
1607 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1608 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1609 struct pipe_resource
*texture
= transfer
->resource
;
1610 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1612 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1613 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1614 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1615 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1616 &rtransfer
->staging
->b
.b
, transfer
->level
,
1619 r600_copy_from_staging_texture(ctx
, rtransfer
);
1623 if (rtransfer
->staging
) {
1624 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1625 r600_resource_reference(&rtransfer
->staging
, NULL
);
1628 /* Heuristic for {upload, draw, upload, draw, ..}:
1630 * Flush the gfx IB if we've allocated too much texture storage.
1632 * The idea is that we don't want to build IBs that use too much
1633 * memory and put pressure on the kernel memory manager and we also
1634 * want to make temporary and invalidated buffers go idle ASAP to
1635 * decrease the total memory usage or make them reusable. The memory
1636 * usage will be slightly higher than given here because of the buffer
1637 * cache in the winsys.
1639 * The result is that the kernel memory manager is never a bottleneck.
1641 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1642 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1643 rctx
->num_alloc_tex_transfer_bytes
= 0;
1649 static const struct u_resource_vtbl r600_texture_vtbl
=
1651 NULL
, /* get_handle */
1652 r600_texture_destroy
, /* resource_destroy */
1653 r600_texture_transfer_map
, /* transfer_map */
1654 u_default_transfer_flush_region
, /* transfer_flush_region */
1655 r600_texture_transfer_unmap
, /* transfer_unmap */
1658 /* DCC channel type categories within which formats can be reinterpreted
1659 * while keeping the same DCC encoding. The swizzle must also match. */
1660 enum dcc_channel_type
{
1661 dcc_channel_float32
,
1664 dcc_channel_float16
,
1667 dcc_channel_uint_10_10_10_2
,
1670 dcc_channel_incompatible
,
1673 /* Return the type of DCC encoding. */
1674 static enum dcc_channel_type
1675 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1679 /* Find the first non-void channel. */
1680 for (i
= 0; i
< desc
->nr_channels
; i
++)
1681 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1683 if (i
== desc
->nr_channels
)
1684 return dcc_channel_incompatible
;
1686 switch (desc
->channel
[i
].size
) {
1688 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1689 return dcc_channel_float32
;
1690 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1691 return dcc_channel_uint32
;
1692 return dcc_channel_sint32
;
1694 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1695 return dcc_channel_float16
;
1696 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1697 return dcc_channel_uint16
;
1698 return dcc_channel_sint16
;
1700 return dcc_channel_uint_10_10_10_2
;
1702 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1703 return dcc_channel_uint8
;
1704 return dcc_channel_sint8
;
1706 return dcc_channel_incompatible
;
1710 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1711 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1712 enum pipe_format format2
)
1714 const struct util_format_description
*desc1
, *desc2
;
1715 enum dcc_channel_type type1
, type2
;
1718 if (format1
== format2
)
1721 desc1
= util_format_description(format1
);
1722 desc2
= util_format_description(format2
);
1724 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1727 /* Swizzles must be the same. */
1728 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1729 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1730 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1731 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1734 type1
= vi_get_dcc_channel_type(desc1
);
1735 type2
= vi_get_dcc_channel_type(desc2
);
1737 return type1
!= dcc_channel_incompatible
&&
1738 type2
!= dcc_channel_incompatible
&&
1742 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1743 struct pipe_resource
*tex
,
1745 enum pipe_format view_format
)
1747 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1749 if (rtex
->dcc_offset
&&
1750 level
< rtex
->surface
.num_dcc_levels
&&
1751 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1752 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1753 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1756 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1757 struct pipe_resource
*texture
,
1758 const struct pipe_surface
*templ
,
1759 unsigned width
, unsigned height
)
1761 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1762 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1767 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1768 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1770 pipe_reference_init(&surface
->base
.reference
, 1);
1771 pipe_resource_reference(&surface
->base
.texture
, texture
);
1772 surface
->base
.context
= pipe
;
1773 surface
->base
.format
= templ
->format
;
1774 surface
->base
.width
= width
;
1775 surface
->base
.height
= height
;
1776 surface
->base
.u
= templ
->u
;
1778 if (texture
->target
!= PIPE_BUFFER
)
1779 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1783 return &surface
->base
;
1786 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1787 struct pipe_resource
*tex
,
1788 const struct pipe_surface
*templ
)
1790 unsigned level
= templ
->u
.tex
.level
;
1791 unsigned width
= u_minify(tex
->width0
, level
);
1792 unsigned height
= u_minify(tex
->height0
, level
);
1794 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1795 const struct util_format_description
*tex_desc
1796 = util_format_description(tex
->format
);
1797 const struct util_format_description
*templ_desc
1798 = util_format_description(templ
->format
);
1800 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1802 /* Adjust size of surface if and only if the block width or
1803 * height is changed. */
1804 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1805 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1806 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1807 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1809 width
= nblks_x
* templ_desc
->block
.width
;
1810 height
= nblks_y
* templ_desc
->block
.height
;
1814 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1817 static void r600_surface_destroy(struct pipe_context
*pipe
,
1818 struct pipe_surface
*surface
)
1820 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1821 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1822 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1823 pipe_resource_reference(&surface
->texture
, NULL
);
1827 static void r600_clear_texture(struct pipe_context
*pipe
,
1828 struct pipe_resource
*tex
,
1830 const struct pipe_box
*box
,
1833 struct pipe_screen
*screen
= pipe
->screen
;
1834 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1835 struct pipe_surface tmpl
= {{0}};
1836 struct pipe_surface
*sf
;
1837 const struct util_format_description
*desc
=
1838 util_format_description(tex
->format
);
1840 tmpl
.format
= tex
->format
;
1841 tmpl
.u
.tex
.first_layer
= box
->z
;
1842 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1843 tmpl
.u
.tex
.level
= level
;
1844 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1848 if (rtex
->is_depth
) {
1851 uint8_t stencil
= 0;
1853 /* Depth is always present. */
1854 clear
= PIPE_CLEAR_DEPTH
;
1855 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1857 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1858 clear
|= PIPE_CLEAR_STENCIL
;
1859 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1862 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1864 box
->width
, box
->height
, false);
1866 union pipe_color_union color
;
1868 /* pipe_color_union requires the full vec4 representation. */
1869 if (util_format_is_pure_uint(tex
->format
))
1870 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1871 else if (util_format_is_pure_sint(tex
->format
))
1872 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1874 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1876 if (screen
->is_format_supported(screen
, tex
->format
,
1878 PIPE_BIND_RENDER_TARGET
)) {
1879 pipe
->clear_render_target(pipe
, sf
, &color
,
1881 box
->width
, box
->height
, false);
1883 /* Software fallback - just for R9G9B9E5_FLOAT */
1884 util_clear_render_target(pipe
, sf
, &color
,
1886 box
->width
, box
->height
);
1889 pipe_surface_reference(&sf
, NULL
);
1892 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1894 const struct util_format_description
*desc
= util_format_description(format
);
1896 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1898 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1899 return V_0280A0_SWAP_STD
;
1901 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1904 switch (desc
->nr_channels
) {
1906 if (HAS_SWIZZLE(0,X
))
1907 return V_0280A0_SWAP_STD
; /* X___ */
1908 else if (HAS_SWIZZLE(3,X
))
1909 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1912 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1913 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1914 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1915 return V_0280A0_SWAP_STD
; /* XY__ */
1916 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1917 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1918 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1920 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1921 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1922 return V_0280A0_SWAP_ALT
; /* X__Y */
1923 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1924 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1927 if (HAS_SWIZZLE(0,X
))
1928 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1929 else if (HAS_SWIZZLE(0,Z
))
1930 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1933 /* check the middle channels, the 1st and 4th channel can be NONE */
1934 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1935 return V_0280A0_SWAP_STD
; /* XYZW */
1936 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1937 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1938 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1939 return V_0280A0_SWAP_ALT
; /* ZYXW */
1940 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1943 return V_0280A0_SWAP_ALT_REV
;
1945 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1952 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1954 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1959 if (rctx
->dcc_stats
[slot
].query_active
)
1960 vi_separate_dcc_stop_query(&rctx
->b
,
1961 rctx
->dcc_stats
[slot
].tex
);
1963 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1964 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1965 rctx
->b
.destroy_query(&rctx
->b
,
1966 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1967 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1970 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1974 * Return the per-context slot where DCC statistics queries for the texture live.
1976 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1977 struct r600_texture
*tex
)
1979 int i
, empty_slot
= -1;
1981 /* Remove zombie textures (textures kept alive by this array only). */
1982 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1983 if (rctx
->dcc_stats
[i
].tex
&&
1984 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1985 vi_dcc_clean_up_context_slot(rctx
, i
);
1987 /* Find the texture. */
1988 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1989 /* Return if found. */
1990 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1991 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1995 /* Record the first seen empty slot. */
1996 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2000 /* Not found. Remove the oldest member to make space in the array. */
2001 if (empty_slot
== -1) {
2002 int oldest_slot
= 0;
2004 /* Find the oldest slot. */
2005 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2006 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2007 rctx
->dcc_stats
[i
].last_use_timestamp
)
2010 /* Clean up the oldest slot. */
2011 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2012 empty_slot
= oldest_slot
;
2015 /* Add the texture to the new slot. */
2016 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2017 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2021 static struct pipe_query
*
2022 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2024 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2025 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2027 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2028 return (struct pipe_query
*)query
;
2032 * Called when binding a color buffer.
2034 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2035 struct r600_texture
*tex
)
2037 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2038 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2040 assert(!rctx
->dcc_stats
[i
].query_active
);
2042 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2043 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2045 /* begin or resume the query */
2046 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2047 rctx
->dcc_stats
[i
].query_active
= true;
2051 * Called when unbinding a color buffer.
2053 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2054 struct r600_texture
*tex
)
2056 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2057 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2059 assert(rctx
->dcc_stats
[i
].query_active
);
2060 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2062 /* pause or end the query */
2063 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2064 rctx
->dcc_stats
[i
].query_active
= false;
2067 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2069 /* The minimum number of fullscreen draws per frame that is required
2071 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2074 /* Called by fast clear. */
2075 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2076 struct r600_texture
*tex
)
2078 /* The intent is to use this with shared displayable back buffers,
2079 * but it's not strictly limited only to them.
2081 if (!tex
->resource
.is_shared
||
2082 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2083 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2084 tex
->resource
.b
.b
.last_level
> 0 ||
2085 !tex
->surface
.dcc_size
)
2088 if (tex
->dcc_offset
)
2089 return; /* already enabled */
2091 /* Enable the DCC stat gathering. */
2092 if (!tex
->dcc_gather_statistics
) {
2093 tex
->dcc_gather_statistics
= true;
2094 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2097 if (!vi_should_enable_separate_dcc(tex
))
2098 return; /* stats show that DCC decompression is too expensive */
2100 assert(tex
->surface
.num_dcc_levels
);
2101 assert(!tex
->dcc_separate_buffer
);
2103 r600_texture_discard_cmask(rctx
->screen
, tex
);
2105 /* Get a DCC buffer. */
2106 if (tex
->last_dcc_separate_buffer
) {
2107 assert(tex
->dcc_gather_statistics
);
2108 assert(!tex
->dcc_separate_buffer
);
2109 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2110 tex
->last_dcc_separate_buffer
= NULL
;
2112 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2113 r600_aligned_buffer_create(rctx
->b
.screen
,
2114 R600_RESOURCE_FLAG_UNMAPPABLE
,
2116 tex
->surface
.dcc_size
,
2117 tex
->surface
.dcc_alignment
);
2118 if (!tex
->dcc_separate_buffer
)
2122 /* dcc_offset is the absolute GPUVM address. */
2123 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2125 /* no need to flag anything since this is called by fast clear that
2126 * flags framebuffer state
2131 * Called by pipe_context::flush_resource, the place where DCC decompression
2134 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2135 struct r600_texture
*tex
)
2137 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2138 struct pipe_query
*tmp
;
2139 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2140 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2141 bool disable
= false;
2143 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2144 union pipe_query_result result
;
2146 /* Read the results. */
2147 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2149 r600_query_hw_reset_buffers(rctx
,
2150 (struct r600_query_hw
*)
2151 rctx
->dcc_stats
[i
].ps_stats
[2]);
2153 /* Compute the approximate number of fullscreen draws. */
2154 tex
->ps_draw_ratio
=
2155 result
.pipeline_statistics
.ps_invocations
/
2156 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2157 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2159 disable
= tex
->dcc_separate_buffer
&&
2160 !vi_should_enable_separate_dcc(tex
);
2163 tex
->num_slow_clears
= 0;
2165 /* stop the statistics query for ps_stats[0] */
2167 vi_separate_dcc_stop_query(ctx
, tex
);
2169 /* Move the queries in the queue by one. */
2170 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2171 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2172 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2173 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2175 /* create and start a new query as ps_stats[0] */
2177 vi_separate_dcc_start_query(ctx
, tex
);
2180 assert(!tex
->last_dcc_separate_buffer
);
2181 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2182 tex
->dcc_separate_buffer
= NULL
;
2183 tex
->dcc_offset
= 0;
2184 /* no need to flag anything since this is called after
2185 * decompression that re-sets framebuffer state
2190 /* FAST COLOR CLEAR */
2192 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2193 enum pipe_format surface_format
,
2194 const union pipe_color_union
*color
)
2196 union util_color uc
;
2198 memset(&uc
, 0, sizeof(uc
));
2200 if (rtex
->surface
.bpe
== 16) {
2201 /* DCC fast clear only:
2202 * CLEAR_WORD0 = R = G = B
2205 assert(color
->ui
[0] == color
->ui
[1] &&
2206 color
->ui
[0] == color
->ui
[2]);
2207 uc
.ui
[0] = color
->ui
[0];
2208 uc
.ui
[1] = color
->ui
[3];
2209 } else if (util_format_is_pure_uint(surface_format
)) {
2210 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2211 } else if (util_format_is_pure_sint(surface_format
)) {
2212 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2214 util_pack_color(color
->f
, surface_format
, &uc
);
2217 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2220 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2221 const union pipe_color_union
*color
,
2222 uint32_t* reset_value
,
2223 bool* clear_words_needed
)
2225 bool values
[4] = {};
2227 bool main_value
= false;
2228 bool extra_value
= false;
2230 const struct util_format_description
*desc
= util_format_description(surface_format
);
2232 if (desc
->block
.bits
== 128 &&
2233 (color
->ui
[0] != color
->ui
[1] ||
2234 color
->ui
[0] != color
->ui
[2]))
2237 *clear_words_needed
= true;
2238 *reset_value
= 0x20202020U
;
2240 /* If we want to clear without needing a fast clear eliminate step, we
2241 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2242 * have two sets of flags, one for the last or first channel(extra) and
2243 * one for the other channels(main).
2246 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2247 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2248 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2250 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2251 if(r600_translate_colorswap(surface_format
, false) <= 1)
2252 extra_channel
= desc
->nr_channels
- 1;
2258 for (i
= 0; i
< 4; ++i
) {
2259 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2261 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2262 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2265 if (desc
->channel
[i
].pure_integer
&&
2266 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2267 /* Use the maximum value for clamping the clear color. */
2268 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2270 values
[i
] = color
->i
[i
] != 0;
2271 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2273 } else if (desc
->channel
[i
].pure_integer
&&
2274 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2275 /* Use the maximum value for clamping the clear color. */
2276 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2278 values
[i
] = color
->ui
[i
] != 0U;
2279 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2282 values
[i
] = color
->f
[i
] != 0.0F
;
2283 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2287 if (index
== extra_channel
)
2288 extra_value
= values
[i
];
2290 main_value
= values
[i
];
2293 for (int i
= 0; i
< 4; ++i
)
2294 if (values
[i
] != main_value
&&
2295 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2296 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2297 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2300 *clear_words_needed
= false;
2302 *reset_value
|= 0x80808080U
;
2305 *reset_value
|= 0x40404040U
;
2309 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2310 struct r600_texture
*rtex
,
2311 unsigned level
, unsigned clear_value
)
2313 struct pipe_resource
*dcc_buffer
;
2314 uint64_t dcc_offset
;
2316 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2318 if (rtex
->dcc_separate_buffer
) {
2319 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2322 dcc_buffer
= &rtex
->resource
.b
.b
;
2323 dcc_offset
= rtex
->dcc_offset
;
2326 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2328 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2329 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2330 clear_value
, R600_COHERENCY_CB_META
);
2333 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2334 * This allows hitting the MSAA resolve fast path, which requires that both
2335 * src and dst micro tile modes match.
2337 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2338 struct r600_texture
*rtex
)
2340 if (rtex
->resource
.is_shared
||
2341 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2342 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2345 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2346 assert(rtex
->resource
.b
.b
.last_level
== 0);
2348 /* These magic numbers were copied from addrlib. It doesn't use any
2349 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2350 * different bpp and micro tile mode.
2352 if (rscreen
->chip_class
>= CIK
) {
2353 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2354 case RADEON_MICRO_MODE_DISPLAY
:
2355 rtex
->surface
.tiling_index
[0] = 10;
2357 case RADEON_MICRO_MODE_THIN
:
2358 rtex
->surface
.tiling_index
[0] = 14;
2360 case RADEON_MICRO_MODE_ROTATED
:
2361 rtex
->surface
.tiling_index
[0] = 28;
2363 default: /* depth, thick */
2364 assert(!"unexpected micro mode");
2368 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2369 case RADEON_MICRO_MODE_DISPLAY
:
2370 switch (rtex
->surface
.bpe
) {
2372 rtex
->surface
.tiling_index
[0] = 10;
2375 rtex
->surface
.tiling_index
[0] = 11;
2378 rtex
->surface
.tiling_index
[0] = 12;
2382 case RADEON_MICRO_MODE_THIN
:
2383 switch (rtex
->surface
.bpe
) {
2385 rtex
->surface
.tiling_index
[0] = 14;
2388 rtex
->surface
.tiling_index
[0] = 15;
2391 rtex
->surface
.tiling_index
[0] = 16;
2393 default: /* 8, 16 */
2394 rtex
->surface
.tiling_index
[0] = 17;
2398 default: /* depth, thick */
2399 assert(!"unexpected micro mode");
2404 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2406 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2409 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2410 struct pipe_framebuffer_state
*fb
,
2411 struct r600_atom
*fb_state
,
2412 unsigned *buffers
, unsigned *dirty_cbufs
,
2413 const union pipe_color_union
*color
)
2417 /* This function is broken in BE, so just disable this path for now */
2418 #ifdef PIPE_ARCH_BIG_ENDIAN
2422 if (rctx
->render_cond
)
2425 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2426 struct r600_texture
*tex
;
2427 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2432 /* if this colorbuffer is not being cleared */
2433 if (!(*buffers
& clear_bit
))
2436 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2438 /* the clear is allowed if all layers are bound */
2439 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2440 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2444 /* cannot clear mipmapped textures */
2445 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2449 /* only supported on tiled surfaces */
2450 if (tex
->surface
.is_linear
) {
2454 /* shared textures can't use fast clear without an explicit flush,
2455 * because there is no way to communicate the clear color among
2458 if (tex
->resource
.is_shared
&&
2459 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2462 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2463 if (rctx
->chip_class
== CIK
&&
2464 tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2465 rctx
->screen
->info
.drm_major
== 2 &&
2466 rctx
->screen
->info
.drm_minor
< 38) {
2470 /* Fast clear is the most appropriate place to enable DCC for
2471 * displayable surfaces.
2473 if (rctx
->chip_class
>= VI
&&
2474 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2475 vi_separate_dcc_try_enable(rctx
, tex
);
2477 /* Stoney can't do a CMASK-based clear, so all clears are
2478 * considered to be hypothetically slow clears, which
2479 * is weighed when determining to enable separate DCC.
2481 if (tex
->dcc_gather_statistics
&&
2482 rctx
->family
== CHIP_STONEY
)
2483 tex
->num_slow_clears
++;
2486 /* Try to clear DCC first, otherwise try CMASK. */
2487 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2488 uint32_t reset_value
;
2489 bool clear_words_needed
;
2491 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2494 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2495 color
, &reset_value
,
2496 &clear_words_needed
))
2499 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2501 if (clear_words_needed
)
2502 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2503 tex
->separate_dcc_dirty
= true;
2505 /* 128-bit formats are unusupported */
2506 if (tex
->surface
.bpe
> 8) {
2510 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2511 if (rctx
->family
== CHIP_STONEY
)
2514 /* ensure CMASK is enabled */
2515 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2516 if (tex
->cmask
.size
== 0) {
2520 /* Do the fast clear. */
2521 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2522 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2523 R600_COHERENCY_CB_META
);
2525 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2528 /* We can change the micro tile mode before a full clear. */
2529 if (rctx
->screen
->chip_class
>= SI
)
2530 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2532 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2535 *dirty_cbufs
|= 1 << i
;
2536 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2537 *buffers
&= ~clear_bit
;
2541 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2543 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2544 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2547 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2549 rctx
->b
.create_surface
= r600_create_surface
;
2550 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2551 rctx
->b
.clear_texture
= r600_clear_texture
;