2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "radeonsi/si_pipe.h"
26 #include "r600_query.h"
27 #include "util/u_format.h"
28 #include "util/u_log.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_resource.h"
32 #include "util/u_surface.h"
33 #include "util/os_time.h"
36 #include "state_tracker/drm_driver.h"
37 #include "amd/common/sid.h"
39 static enum radeon_surf_mode
40 r600_choose_tiling(struct si_screen
*sscreen
,
41 const struct pipe_resource
*templ
);
44 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(rsrc
, src_level
) ||
75 vi_dcc_enabled(rdst
, dst_level
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 si_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct si_screen
*sscreen
,
180 struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
,
183 unsigned *layer_stride
)
185 if (sscreen
->info
.chip_class
>= GFX9
) {
186 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
187 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
195 rtex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ rtex
->surface
.blk_h
*
197 rtex
->surface
.u
.gfx9
.surf_pitch
+
198 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
200 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
202 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
203 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct si_screen
*sscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (!is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two_or_zero(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (sscreen
->info
.chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (sscreen
->info
.chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (sscreen
->info
.chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
270 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
271 (ptex
->nr_samples
>= 2 &&
272 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
276 /* This should catch bugs in gallium users setting incorrect flags. */
277 assert(ptex
->nr_samples
<= 1 &&
278 ptex
->array_size
== 1 &&
280 ptex
->last_level
== 0 &&
281 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
283 flags
|= RADEON_SURF_SCANOUT
;
286 if (ptex
->bind
& PIPE_BIND_SHARED
)
287 flags
|= RADEON_SURF_SHAREABLE
;
289 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
290 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
291 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
293 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
294 array_mode
, surface
);
299 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
301 if (sscreen
->info
.chip_class
>= GFX9
) {
303 surface
->u
.gfx9
.surf_pitch
= pitch
;
304 surface
->u
.gfx9
.surf_slice_size
=
305 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
307 surface
->u
.gfx9
.surf_offset
= offset
;
310 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
311 surface
->u
.legacy
.level
[0].slice_size_dw
=
312 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
315 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
316 surface
->u
.legacy
.level
[i
].offset
+= offset
;
322 static void r600_texture_init_metadata(struct si_screen
*sscreen
,
323 struct r600_texture
*rtex
,
324 struct radeon_bo_metadata
*metadata
)
326 struct radeon_surf
*surface
= &rtex
->surface
;
328 memset(metadata
, 0, sizeof(*metadata
));
330 if (sscreen
->info
.chip_class
>= GFX9
) {
331 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
333 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
334 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
335 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
336 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
337 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
338 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
339 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
340 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
341 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
342 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
343 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
344 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
348 static void r600_surface_import_metadata(struct si_screen
*sscreen
,
349 struct radeon_surf
*surf
,
350 struct radeon_bo_metadata
*metadata
,
351 enum radeon_surf_mode
*array_mode
,
354 if (sscreen
->info
.chip_class
>= GFX9
) {
355 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
356 *array_mode
= RADEON_SURF_MODE_2D
;
358 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
360 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
361 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
363 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
365 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
366 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
367 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
368 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
369 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
370 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
372 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
373 *array_mode
= RADEON_SURF_MODE_2D
;
374 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
375 *array_mode
= RADEON_SURF_MODE_1D
;
377 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
379 *is_scanout
= metadata
->u
.legacy
.scanout
;
383 void si_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
384 struct r600_texture
*rtex
)
386 struct si_screen
*sscreen
= rctx
->screen
;
387 struct pipe_context
*ctx
= &rctx
->b
;
389 if (ctx
== sscreen
->aux_context
)
390 mtx_lock(&sscreen
->aux_context_lock
);
392 unsigned n
= rctx
->num_decompress_calls
;
393 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
395 /* Flush only if any fast clear elimination took place. */
396 if (n
!= rctx
->num_decompress_calls
)
397 ctx
->flush(ctx
, NULL
, 0);
399 if (ctx
== sscreen
->aux_context
)
400 mtx_unlock(&sscreen
->aux_context_lock
);
403 void si_texture_discard_cmask(struct si_screen
*sscreen
,
404 struct r600_texture
*rtex
)
406 if (!rtex
->cmask
.size
)
409 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
412 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
413 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
414 rtex
->dirty_level_mask
= 0;
416 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
418 if (rtex
->cmask_buffer
!= &rtex
->resource
)
419 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
421 /* Notify all contexts about the change. */
422 p_atomic_inc(&sscreen
->dirty_tex_counter
);
423 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
426 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
428 /* We can't disable DCC if it can be written by another process. */
429 return rtex
->dcc_offset
&&
430 (!rtex
->resource
.b
.is_shared
||
431 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
434 static bool r600_texture_discard_dcc(struct si_screen
*sscreen
,
435 struct r600_texture
*rtex
)
437 if (!r600_can_disable_dcc(rtex
))
440 assert(rtex
->dcc_separate_buffer
== NULL
);
443 rtex
->dcc_offset
= 0;
445 /* Notify all contexts about the change. */
446 p_atomic_inc(&sscreen
->dirty_tex_counter
);
451 * Disable DCC for the texture. (first decompress, then discard metadata).
453 * There is unresolved multi-context synchronization issue between
454 * screen::aux_context and the current context. If applications do this with
455 * multiple contexts, it's already undefined behavior for them and we don't
456 * have to worry about that. The scenario is:
458 * If context 1 disables DCC and context 2 has queued commands that write
459 * to the texture via CB with DCC enabled, and the order of operations is
461 * context 2 queues draw calls rendering to the texture, but doesn't flush
462 * context 1 disables DCC and flushes
463 * context 1 & 2 reset descriptors and FB state
464 * context 2 flushes (new compressed tiles written by the draw calls)
465 * context 1 & 2 read garbage, because DCC is disabled, yet there are
468 * \param rctx the current context if you have one, or rscreen->aux_context
471 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
472 struct r600_texture
*rtex
)
474 struct si_screen
*sscreen
= rctx
->screen
;
476 if (!r600_can_disable_dcc(rtex
))
479 if (&rctx
->b
== sscreen
->aux_context
)
480 mtx_lock(&sscreen
->aux_context_lock
);
482 /* Decompress DCC. */
483 rctx
->decompress_dcc(&rctx
->b
, rtex
);
484 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
486 if (&rctx
->b
== sscreen
->aux_context
)
487 mtx_unlock(&sscreen
->aux_context_lock
);
489 return r600_texture_discard_dcc(sscreen
, rtex
);
492 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
493 struct r600_texture
*rtex
,
494 unsigned new_bind_flag
,
495 bool invalidate_storage
)
497 struct pipe_screen
*screen
= rctx
->b
.screen
;
498 struct r600_texture
*new_tex
;
499 struct pipe_resource templ
= rtex
->resource
.b
.b
;
502 templ
.bind
|= new_bind_flag
;
504 if (rtex
->resource
.b
.is_shared
)
507 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
508 if (rtex
->surface
.is_linear
)
511 /* This fails with MSAA, depth, and compressed textures. */
512 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
513 RADEON_SURF_MODE_LINEAR_ALIGNED
)
517 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
521 /* Copy the pixels to the new texture. */
522 if (!invalidate_storage
) {
523 for (i
= 0; i
<= templ
.last_level
; i
++) {
527 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
528 util_num_layers(&templ
, i
), &box
);
530 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
531 &rtex
->resource
.b
.b
, i
, &box
);
535 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
536 si_texture_discard_cmask(rctx
->screen
, rtex
);
537 r600_texture_discard_dcc(rctx
->screen
, rtex
);
540 /* Replace the structure fields of rtex. */
541 rtex
->resource
.b
.b
.bind
= templ
.bind
;
542 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
543 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
544 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
545 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
546 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
547 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
548 rtex
->resource
.domains
= new_tex
->resource
.domains
;
549 rtex
->resource
.flags
= new_tex
->resource
.flags
;
550 rtex
->size
= new_tex
->size
;
551 rtex
->db_render_format
= new_tex
->db_render_format
;
552 rtex
->db_compatible
= new_tex
->db_compatible
;
553 rtex
->can_sample_z
= new_tex
->can_sample_z
;
554 rtex
->can_sample_s
= new_tex
->can_sample_s
;
555 rtex
->surface
= new_tex
->surface
;
556 rtex
->fmask
= new_tex
->fmask
;
557 rtex
->cmask
= new_tex
->cmask
;
558 rtex
->cb_color_info
= new_tex
->cb_color_info
;
559 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
560 rtex
->htile_offset
= new_tex
->htile_offset
;
561 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
562 rtex
->depth_cleared
= new_tex
->depth_cleared
;
563 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
564 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
565 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
567 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
568 assert(!rtex
->htile_offset
);
569 assert(!rtex
->cmask
.size
);
570 assert(!rtex
->fmask
.size
);
571 assert(!rtex
->dcc_offset
);
572 assert(!rtex
->is_depth
);
575 r600_texture_reference(&new_tex
, NULL
);
577 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
580 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
582 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
585 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
586 struct r600_texture
*rtex
,
587 struct radeon_bo_metadata
*md
)
589 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
590 static const unsigned char swizzle
[] = {
597 bool is_array
= util_texture_is_array(res
->target
);
599 /* DRM 2.x.x doesn't support this. */
600 if (sscreen
->info
.drm_major
!= 3)
603 assert(rtex
->dcc_separate_buffer
== NULL
);
604 assert(rtex
->fmask
.size
== 0);
606 /* Metadata image format format version 1:
607 * [0] = 1 (metadata format identifier)
608 * [1] = (VENDOR_ID << 16) | PCI_ID
609 * [2:9] = image descriptor for the whole resource
610 * [2] is always 0, because the base address is cleared
611 * [9] is the DCC offset bits [39:8] from the beginning of
613 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
616 md
->metadata
[0] = 1; /* metadata image format version 1 */
618 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
619 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
621 si_make_texture_descriptor(sscreen
, rtex
, true,
622 res
->target
, res
->format
,
623 swizzle
, 0, res
->last_level
, 0,
624 is_array
? res
->array_size
- 1 : 0,
625 res
->width0
, res
->height0
, res
->depth0
,
628 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
629 0, 0, rtex
->surface
.blk_w
, false, desc
);
631 /* Clear the base address and set the relative DCC offset. */
633 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
634 desc
[7] = rtex
->dcc_offset
>> 8;
636 /* Dwords [2:9] contain the image descriptor. */
637 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
638 md
->size_metadata
= 10 * 4;
640 /* Dwords [10:..] contain the mipmap level offsets. */
641 if (sscreen
->info
.chip_class
<= VI
) {
642 for (i
= 0; i
<= res
->last_level
; i
++)
643 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
645 md
->size_metadata
+= (1 + res
->last_level
) * 4;
649 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
650 struct r600_texture
*rtex
,
651 struct radeon_bo_metadata
*md
)
653 uint32_t *desc
= &md
->metadata
[2];
655 if (sscreen
->info
.chip_class
< VI
)
658 /* Return if DCC is enabled. The texture should be set up with it
661 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
662 md
->metadata
[0] != 0 &&
663 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
664 G_008F28_COMPRESSION_EN(desc
[6])) {
665 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
669 /* Disable DCC. These are always set by texture_from_handle and must
672 rtex
->dcc_offset
= 0;
675 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
676 struct pipe_context
*ctx
,
677 struct pipe_resource
*resource
,
678 struct winsys_handle
*whandle
,
681 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
682 struct r600_common_context
*rctx
;
683 struct r600_resource
*res
= (struct r600_resource
*)resource
;
684 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
685 struct radeon_bo_metadata metadata
;
686 bool update_metadata
= false;
687 unsigned stride
, offset
, slice_size
;
690 ctx
= threaded_context_unwrap_sync(ctx
);
691 rctx
= (struct r600_common_context
*)(ctx
? ctx
: sscreen
->aux_context
);
693 if (resource
->target
!= PIPE_BUFFER
) {
694 /* This is not supported now, but it might be required for OpenCL
695 * interop in the future.
697 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
700 /* Move a suballocated texture into a non-suballocated allocation. */
701 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
702 rtex
->surface
.tile_swizzle
||
703 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
704 sscreen
->info
.has_local_buffers
&&
705 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
706 assert(!res
->b
.is_shared
);
707 r600_reallocate_texture_inplace(rctx
, rtex
,
708 PIPE_BIND_SHARED
, false);
710 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
711 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
712 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
713 assert(rtex
->surface
.tile_swizzle
== 0);
716 /* Since shader image stores don't support DCC on VI,
717 * disable it for external clients that want write
720 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
721 if (si_texture_disable_dcc(rctx
, rtex
)) {
722 update_metadata
= true;
723 /* si_texture_disable_dcc flushes the context */
728 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
729 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
730 /* Eliminate fast clear (both CMASK and DCC) */
731 si_eliminate_fast_color_clear(rctx
, rtex
);
732 /* eliminate_fast_color_clear flushes the context */
735 /* Disable CMASK if flush_resource isn't going
738 if (rtex
->cmask
.size
)
739 si_texture_discard_cmask(sscreen
, rtex
);
743 if (!res
->b
.is_shared
|| update_metadata
) {
744 r600_texture_init_metadata(sscreen
, rtex
, &metadata
);
745 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
747 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
750 if (sscreen
->info
.chip_class
>= GFX9
) {
751 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
752 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
754 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
756 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
757 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
759 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
762 /* Buffer exports are for the OpenCL interop. */
763 /* Move a suballocated buffer into a non-suballocated allocation. */
764 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
765 /* A DMABUF export always fails if the BO is local. */
766 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
767 sscreen
->info
.has_local_buffers
)) {
768 assert(!res
->b
.is_shared
);
770 /* Allocate a new buffer with PIPE_BIND_SHARED. */
771 struct pipe_resource templ
= res
->b
.b
;
772 templ
.bind
|= PIPE_BIND_SHARED
;
774 struct pipe_resource
*newb
=
775 screen
->resource_create(screen
, &templ
);
779 /* Copy the old buffer contents to the new one. */
781 u_box_1d(0, newb
->width0
, &box
);
782 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
785 /* Move the new buffer storage to the old pipe_resource. */
786 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
787 pipe_resource_reference(&newb
, NULL
);
789 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
790 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
800 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
802 if (res
->b
.is_shared
) {
803 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
806 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
807 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
808 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
810 res
->b
.is_shared
= true;
811 res
->external_usage
= usage
;
814 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
815 slice_size
, whandle
);
818 static void r600_texture_destroy(struct pipe_screen
*screen
,
819 struct pipe_resource
*ptex
)
821 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
822 struct r600_resource
*resource
= &rtex
->resource
;
824 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
826 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
827 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
829 pb_reference(&resource
->buf
, NULL
);
830 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
831 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
835 static const struct u_resource_vtbl r600_texture_vtbl
;
837 /* The number of samples can be specified independently of the texture. */
838 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
839 struct r600_texture
*rtex
,
841 struct r600_fmask_info
*out
)
843 /* FMASK is allocated like an ordinary texture. */
844 struct pipe_resource templ
= rtex
->resource
.b
.b
;
845 struct radeon_surf fmask
= {};
848 memset(out
, 0, sizeof(*out
));
850 if (sscreen
->info
.chip_class
>= GFX9
) {
851 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
852 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
853 out
->tile_swizzle
= rtex
->surface
.u
.gfx9
.fmask_tile_swizzle
;
857 templ
.nr_samples
= 1;
858 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
860 switch (nr_samples
) {
869 R600_ERR("Invalid sample count for FMASK allocation.\n");
873 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
874 RADEON_SURF_MODE_2D
, &fmask
)) {
875 R600_ERR("Got error in surface_init while allocating FMASK.\n");
879 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
881 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
882 if (out
->slice_tile_max
)
883 out
->slice_tile_max
-= 1;
885 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
886 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
887 out
->bank_height
= fmask
.u
.legacy
.bankh
;
888 out
->tile_swizzle
= fmask
.tile_swizzle
;
889 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
890 out
->size
= fmask
.surf_size
;
893 static void r600_texture_allocate_fmask(struct si_screen
*sscreen
,
894 struct r600_texture
*rtex
)
896 si_texture_get_fmask_info(sscreen
, rtex
,
897 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
899 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
900 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
903 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
904 struct r600_texture
*rtex
,
905 struct r600_cmask_info
*out
)
907 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
908 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
909 unsigned cl_width
, cl_height
;
911 if (sscreen
->info
.chip_class
>= GFX9
) {
912 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
913 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
930 case 16: /* Hawaii */
939 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
941 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
942 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
943 unsigned slice_elements
= (width
* height
) / (8*8);
945 /* Each element of CMASK is a nibble. */
946 unsigned slice_bytes
= slice_elements
/ 2;
948 out
->slice_tile_max
= (width
* height
) / (128*128);
949 if (out
->slice_tile_max
)
950 out
->slice_tile_max
-= 1;
952 out
->alignment
= MAX2(256, base_align
);
953 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
954 align(slice_bytes
, base_align
);
957 static void r600_texture_allocate_cmask(struct si_screen
*sscreen
,
958 struct r600_texture
*rtex
)
960 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
962 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
963 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
965 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
968 static void r600_texture_get_htile_size(struct si_screen
*sscreen
,
969 struct r600_texture
*rtex
)
971 unsigned cl_width
, cl_height
, width
, height
;
972 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
973 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
975 assert(sscreen
->info
.chip_class
<= VI
);
977 rtex
->surface
.htile_size
= 0;
979 /* HTILE is broken with 1D tiling on old kernels and CIK. */
980 if (sscreen
->info
.chip_class
>= CIK
&&
981 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
982 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
985 /* Overalign HTILE on P2 configs to work around GPU hangs in
986 * piglit/depthstencil-render-miplevels 585.
988 * This has been confirmed to help Kabini & Stoney, where the hangs
989 * are always reproducible. I think I have seen the test hang
990 * on Carrizo too, though it was very rare there.
992 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1021 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1022 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1024 slice_elements
= (width
* height
) / (8 * 8);
1025 slice_bytes
= slice_elements
* 4;
1027 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1028 base_align
= num_pipes
* pipe_interleave_bytes
;
1030 rtex
->surface
.htile_alignment
= base_align
;
1031 rtex
->surface
.htile_size
=
1032 util_num_layers(&rtex
->resource
.b
.b
, 0) *
1033 align(slice_bytes
, base_align
);
1036 static void r600_texture_allocate_htile(struct si_screen
*sscreen
,
1037 struct r600_texture
*rtex
)
1039 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1040 r600_texture_get_htile_size(sscreen
, rtex
);
1042 if (!rtex
->surface
.htile_size
)
1045 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1046 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1049 void si_print_texture_info(struct si_screen
*sscreen
,
1050 struct r600_texture
*rtex
, struct u_log_context
*log
)
1054 /* Common parameters. */
1055 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1056 "blk_h=%u, array_size=%u, last_level=%u, "
1057 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1058 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1059 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1060 rtex
->surface
.blk_h
,
1061 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1062 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1063 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1065 if (sscreen
->info
.chip_class
>= GFX9
) {
1066 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1067 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1068 rtex
->surface
.surf_size
,
1069 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1070 rtex
->surface
.surf_alignment
,
1071 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1072 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1073 rtex
->surface
.u
.gfx9
.surf_pitch
);
1075 if (rtex
->fmask
.size
) {
1076 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1077 "alignment=%u, swmode=%u, epitch=%u\n",
1079 rtex
->surface
.u
.gfx9
.fmask_size
,
1080 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1081 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1082 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1085 if (rtex
->cmask
.size
) {
1086 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1087 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1089 rtex
->surface
.u
.gfx9
.cmask_size
,
1090 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1091 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1092 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1095 if (rtex
->htile_offset
) {
1096 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1097 "rb_aligned=%u, pipe_aligned=%u\n",
1099 rtex
->surface
.htile_size
,
1100 rtex
->surface
.htile_alignment
,
1101 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1102 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1105 if (rtex
->dcc_offset
) {
1106 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1107 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1108 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1109 rtex
->surface
.dcc_alignment
,
1110 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1111 rtex
->surface
.num_dcc_levels
);
1114 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1115 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1116 rtex
->surface
.u
.gfx9
.stencil_offset
,
1117 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1118 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1123 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1124 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1125 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1126 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1127 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1128 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1130 if (rtex
->fmask
.size
)
1131 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1132 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1133 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1134 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1135 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1137 if (rtex
->cmask
.size
)
1138 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1139 "slice_tile_max=%u\n",
1140 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1141 rtex
->cmask
.slice_tile_max
);
1143 if (rtex
->htile_offset
)
1144 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1145 "alignment=%u, TC_compatible = %u\n",
1146 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1147 rtex
->surface
.htile_alignment
,
1148 rtex
->tc_compatible_htile
);
1150 if (rtex
->dcc_offset
) {
1151 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1152 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1153 rtex
->surface
.dcc_alignment
);
1154 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1155 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1156 "fast_clear_size=%u\n",
1157 i
, i
< rtex
->surface
.num_dcc_levels
,
1158 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1159 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1162 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1163 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1164 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1165 "mode=%u, tiling_index = %u\n",
1166 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1167 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1168 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1169 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1170 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1171 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1172 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1173 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1174 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1176 if (rtex
->surface
.has_stencil
) {
1177 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1178 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1179 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1180 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1181 "slice_size=%"PRIu64
", npix_x=%u, "
1182 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1183 "mode=%u, tiling_index = %u\n",
1184 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1185 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1186 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1187 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1188 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1189 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1190 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1191 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1192 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1197 /* Common processing for r600_texture_create and r600_texture_from_handle */
1198 static struct r600_texture
*
1199 r600_texture_create_object(struct pipe_screen
*screen
,
1200 const struct pipe_resource
*base
,
1201 struct pb_buffer
*buf
,
1202 struct radeon_surf
*surface
)
1204 struct r600_texture
*rtex
;
1205 struct r600_resource
*resource
;
1206 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1208 rtex
= CALLOC_STRUCT(r600_texture
);
1212 resource
= &rtex
->resource
;
1213 resource
->b
.b
= *base
;
1214 resource
->b
.b
.next
= NULL
;
1215 resource
->b
.vtbl
= &r600_texture_vtbl
;
1216 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1217 resource
->b
.b
.screen
= screen
;
1219 /* don't include stencil-only formats which we don't support for rendering */
1220 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1222 rtex
->surface
= *surface
;
1223 rtex
->size
= rtex
->surface
.surf_size
;
1225 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1226 (rtex
->surface
.flags
&
1227 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1229 /* TC-compatible HTILE:
1230 * - VI only supports Z32_FLOAT.
1231 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1232 if (rtex
->tc_compatible_htile
) {
1233 if (sscreen
->info
.chip_class
>= GFX9
&&
1234 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1235 rtex
->db_render_format
= base
->format
;
1237 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1238 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1239 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1242 rtex
->db_render_format
= base
->format
;
1245 /* Applies to GCN. */
1246 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1248 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1249 * between frames, so the only thing that can enable separate DCC
1250 * with DRI2 is multiple slow clears within a frame.
1252 rtex
->ps_draw_ratio
= 0;
1254 if (rtex
->is_depth
) {
1255 if (sscreen
->info
.chip_class
>= GFX9
) {
1256 rtex
->can_sample_z
= true;
1257 rtex
->can_sample_s
= true;
1259 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1260 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1263 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1264 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1265 rtex
->db_compatible
= true;
1267 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1268 r600_texture_allocate_htile(sscreen
, rtex
);
1271 if (base
->nr_samples
> 1 &&
1273 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1274 r600_texture_allocate_fmask(sscreen
, rtex
);
1275 r600_texture_allocate_cmask(sscreen
, rtex
);
1276 rtex
->cmask_buffer
= &rtex
->resource
;
1278 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1284 /* Shared textures must always set up DCC here.
1285 * If it's not present, it will be disabled by
1286 * apply_opaque_metadata later.
1288 if (rtex
->surface
.dcc_size
&&
1289 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1290 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1291 /* Reserve space for the DCC buffer. */
1292 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1293 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1297 /* Now create the backing buffer. */
1299 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1300 rtex
->surface
.surf_alignment
);
1302 if (!si_alloc_resource(sscreen
, resource
)) {
1307 resource
->buf
= buf
;
1308 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1309 resource
->bo_size
= buf
->size
;
1310 resource
->bo_alignment
= buf
->alignment
;
1311 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1312 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1313 resource
->vram_usage
= buf
->size
;
1314 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1315 resource
->gart_usage
= buf
->size
;
1318 if (rtex
->cmask
.size
) {
1319 /* Initialize the cmask to 0xCC (= compressed state). */
1320 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1321 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1324 if (rtex
->htile_offset
) {
1325 uint32_t clear_value
= 0;
1327 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1328 clear_value
= 0x0000030F;
1330 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1332 rtex
->surface
.htile_size
,
1336 /* Initialize DCC only if the texture is not being imported. */
1337 if (!buf
&& rtex
->dcc_offset
) {
1338 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1340 rtex
->surface
.dcc_size
,
1344 /* Initialize the CMASK base register value. */
1345 rtex
->cmask
.base_address_reg
=
1346 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1348 if (sscreen
->debug_flags
& DBG(VM
)) {
1349 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1350 rtex
->resource
.gpu_address
,
1351 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1352 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1353 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1356 if (sscreen
->debug_flags
& DBG(TEX
)) {
1358 struct u_log_context log
;
1359 u_log_context_init(&log
);
1360 si_print_texture_info(sscreen
, rtex
, &log
);
1361 u_log_new_page_print(&log
, stdout
);
1363 u_log_context_destroy(&log
);
1369 static enum radeon_surf_mode
1370 r600_choose_tiling(struct si_screen
*sscreen
,
1371 const struct pipe_resource
*templ
)
1373 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1374 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1375 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1376 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1378 /* MSAA resources must be 2D tiled. */
1379 if (templ
->nr_samples
> 1)
1380 return RADEON_SURF_MODE_2D
;
1382 /* Transfer resources should be linear. */
1383 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1384 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1386 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1387 * which requires 2D tiling.
1389 if (sscreen
->info
.chip_class
== VI
&&
1391 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1392 return RADEON_SURF_MODE_2D
;
1394 /* Handle common candidates for the linear mode.
1395 * Compressed textures and DB surfaces must always be tiled.
1397 if (!force_tiling
&&
1398 !is_depth_stencil
&&
1399 !util_format_is_compressed(templ
->format
)) {
1400 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1401 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1403 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1404 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1405 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1407 /* Cursors are linear on SI.
1408 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1409 if (templ
->bind
& PIPE_BIND_CURSOR
)
1410 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1412 if (templ
->bind
& PIPE_BIND_LINEAR
)
1413 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1415 /* Textures with a very small height are recommended to be linear. */
1416 if (templ
->target
== PIPE_TEXTURE_1D
||
1417 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1418 /* Only very thin and long 2D textures should benefit from
1419 * linear_aligned. */
1420 (templ
->width0
> 8 && templ
->height0
<= 2))
1421 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1423 /* Textures likely to be mapped often. */
1424 if (templ
->usage
== PIPE_USAGE_STAGING
||
1425 templ
->usage
== PIPE_USAGE_STREAM
)
1426 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1429 /* Make small textures 1D tiled. */
1430 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1431 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1432 return RADEON_SURF_MODE_1D
;
1434 /* The allocator will switch to 1D if needed. */
1435 return RADEON_SURF_MODE_2D
;
1438 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1439 const struct pipe_resource
*templ
)
1441 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1442 struct radeon_surf surface
= {0};
1443 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1444 bool tc_compatible_htile
=
1445 sscreen
->info
.chip_class
>= VI
&&
1446 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1447 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1448 !is_flushed_depth
&&
1449 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1450 util_format_is_depth_or_stencil(templ
->format
);
1454 r
= r600_init_surface(sscreen
, &surface
, templ
,
1455 r600_choose_tiling(sscreen
, templ
), 0, 0,
1456 false, false, is_flushed_depth
,
1457 tc_compatible_htile
);
1462 return (struct pipe_resource
*)
1463 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1466 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1467 const struct pipe_resource
*templ
,
1468 struct winsys_handle
*whandle
,
1471 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1472 struct pb_buffer
*buf
= NULL
;
1473 unsigned stride
= 0, offset
= 0;
1474 enum radeon_surf_mode array_mode
;
1475 struct radeon_surf surface
= {};
1477 struct radeon_bo_metadata metadata
= {};
1478 struct r600_texture
*rtex
;
1481 /* Support only 2D textures without mipmaps */
1482 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1483 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1486 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1490 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1491 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
1492 &array_mode
, &is_scanout
);
1494 r
= r600_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1495 offset
, true, is_scanout
, false, false);
1500 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1504 rtex
->resource
.b
.is_shared
= true;
1505 rtex
->resource
.external_usage
= usage
;
1507 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1509 assert(rtex
->surface
.tile_swizzle
== 0);
1510 return &rtex
->resource
.b
.b
;
1513 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1514 struct pipe_resource
*texture
,
1515 struct r600_texture
**staging
)
1517 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1518 struct pipe_resource resource
;
1519 struct r600_texture
**flushed_depth_texture
= staging
?
1520 staging
: &rtex
->flushed_depth_texture
;
1521 enum pipe_format pipe_format
= texture
->format
;
1524 if (rtex
->flushed_depth_texture
)
1525 return true; /* it's ready */
1527 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1528 switch (pipe_format
) {
1529 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1530 /* Save memory by not allocating the S plane. */
1531 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1533 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1534 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1535 /* Save memory bandwidth by not copying the
1536 * stencil part during flush.
1538 * This potentially increases memory bandwidth
1539 * if an application uses both Z and S texturing
1540 * simultaneously (a flushed Z24S8 texture
1541 * would be stored compactly), but how often
1542 * does that really happen?
1544 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1548 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1549 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1551 /* DB->CB copies to an 8bpp surface don't work. */
1552 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1556 memset(&resource
, 0, sizeof(resource
));
1557 resource
.target
= texture
->target
;
1558 resource
.format
= pipe_format
;
1559 resource
.width0
= texture
->width0
;
1560 resource
.height0
= texture
->height0
;
1561 resource
.depth0
= texture
->depth0
;
1562 resource
.array_size
= texture
->array_size
;
1563 resource
.last_level
= texture
->last_level
;
1564 resource
.nr_samples
= texture
->nr_samples
;
1565 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1566 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1567 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1570 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1572 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1573 if (*flushed_depth_texture
== NULL
) {
1574 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1581 * Initialize the pipe_resource descriptor to be of the same size as the box,
1582 * which is supposed to hold a subregion of the texture "orig" at the given
1585 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1586 struct pipe_resource
*orig
,
1587 const struct pipe_box
*box
,
1588 unsigned level
, unsigned flags
)
1590 memset(res
, 0, sizeof(*res
));
1591 res
->format
= orig
->format
;
1592 res
->width0
= box
->width
;
1593 res
->height0
= box
->height
;
1595 res
->array_size
= 1;
1596 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1599 /* We must set the correct texture target and dimensions for a 3D box. */
1600 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1601 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1602 res
->array_size
= box
->depth
;
1604 res
->target
= PIPE_TEXTURE_2D
;
1608 static bool r600_can_invalidate_texture(struct si_screen
*sscreen
,
1609 struct r600_texture
*rtex
,
1610 unsigned transfer_usage
,
1611 const struct pipe_box
*box
)
1613 return !rtex
->resource
.b
.is_shared
&&
1614 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1615 rtex
->resource
.b
.b
.last_level
== 0 &&
1616 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1617 box
->x
, box
->y
, box
->z
,
1618 box
->width
, box
->height
,
1622 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1623 struct r600_texture
*rtex
)
1625 struct si_screen
*sscreen
= rctx
->screen
;
1627 /* There is no point in discarding depth and tiled buffers. */
1628 assert(!rtex
->is_depth
);
1629 assert(rtex
->surface
.is_linear
);
1631 /* Reallocate the buffer in the same pipe_resource. */
1632 si_alloc_resource(sscreen
, &rtex
->resource
);
1634 /* Initialize the CMASK base address (needed even without CMASK). */
1635 rtex
->cmask
.base_address_reg
=
1636 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1638 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1640 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1643 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1644 struct pipe_resource
*texture
,
1647 const struct pipe_box
*box
,
1648 struct pipe_transfer
**ptransfer
)
1650 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1651 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1652 struct r600_transfer
*trans
;
1653 struct r600_resource
*buf
;
1654 unsigned offset
= 0;
1656 bool use_staging_texture
= false;
1658 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1659 assert(box
->width
&& box
->height
&& box
->depth
);
1661 /* Depth textures use staging unconditionally. */
1662 if (!rtex
->is_depth
) {
1663 /* Degrade the tile mode if we get too many transfers on APUs.
1664 * On dGPUs, the staging texture is always faster.
1665 * Only count uploads that are at least 4x4 pixels large.
1667 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1669 box
->width
>= 4 && box
->height
>= 4 &&
1670 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1671 bool can_invalidate
=
1672 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1675 r600_reallocate_texture_inplace(rctx
, rtex
,
1680 /* Tiled textures need to be converted into a linear texture for CPU
1681 * access. The staging texture is always linear and is placed in GART.
1683 * Reading from VRAM or GTT WC is slow, always use the staging
1684 * texture in this case.
1686 * Use the staging texture for uploads if the underlying BO
1689 if (!rtex
->surface
.is_linear
)
1690 use_staging_texture
= true;
1691 else if (usage
& PIPE_TRANSFER_READ
)
1692 use_staging_texture
=
1693 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1694 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1695 /* Write & linear only: */
1696 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1697 RADEON_USAGE_READWRITE
) ||
1698 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1699 RADEON_USAGE_READWRITE
)) {
1701 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1703 r600_texture_invalidate_storage(rctx
, rtex
);
1705 use_staging_texture
= true;
1709 trans
= CALLOC_STRUCT(r600_transfer
);
1712 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1713 trans
->b
.b
.level
= level
;
1714 trans
->b
.b
.usage
= usage
;
1715 trans
->b
.b
.box
= *box
;
1717 if (rtex
->is_depth
) {
1718 struct r600_texture
*staging_depth
;
1720 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1721 /* MSAA depth buffers need to be converted to single sample buffers.
1723 * Mapping MSAA depth buffers can occur if ReadPixels is called
1724 * with a multisample GLX visual.
1726 * First downsample the depth buffer to a temporary texture,
1727 * then decompress the temporary one to staging.
1729 * Only the region being mapped is transfered.
1731 struct pipe_resource resource
;
1733 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1735 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1736 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1741 if (usage
& PIPE_TRANSFER_READ
) {
1742 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1744 R600_ERR("failed to create a temporary depth texture\n");
1749 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1750 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1751 0, 0, 0, box
->depth
, 0, 0);
1752 pipe_resource_reference(&temp
, NULL
);
1755 /* Just get the strides. */
1756 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1758 &trans
->b
.b
.layer_stride
);
1760 /* XXX: only readback the rectangle which is being mapped? */
1761 /* XXX: when discard is true, no need to read back from depth texture */
1762 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1763 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1768 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1770 box
->z
, box
->z
+ box
->depth
- 1,
1773 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1776 &trans
->b
.b
.layer_stride
);
1779 trans
->staging
= (struct r600_resource
*)staging_depth
;
1780 buf
= trans
->staging
;
1781 } else if (use_staging_texture
) {
1782 struct pipe_resource resource
;
1783 struct r600_texture
*staging
;
1785 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1786 R600_RESOURCE_FLAG_TRANSFER
);
1787 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1788 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1790 /* Create the temporary texture. */
1791 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1793 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1797 trans
->staging
= &staging
->resource
;
1799 /* Just get the strides. */
1800 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1802 &trans
->b
.b
.layer_stride
);
1804 if (usage
& PIPE_TRANSFER_READ
)
1805 r600_copy_to_staging_texture(ctx
, trans
);
1807 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1809 buf
= trans
->staging
;
1811 /* the resource is mapped directly */
1812 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1814 &trans
->b
.b
.layer_stride
);
1815 buf
= &rtex
->resource
;
1818 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1819 r600_resource_reference(&trans
->staging
, NULL
);
1824 *ptransfer
= &trans
->b
.b
;
1825 return map
+ offset
;
1828 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1829 struct pipe_transfer
* transfer
)
1831 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1832 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1833 struct pipe_resource
*texture
= transfer
->resource
;
1834 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1836 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1837 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1838 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1839 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1840 &rtransfer
->staging
->b
.b
, transfer
->level
,
1843 r600_copy_from_staging_texture(ctx
, rtransfer
);
1847 if (rtransfer
->staging
) {
1848 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1849 r600_resource_reference(&rtransfer
->staging
, NULL
);
1852 /* Heuristic for {upload, draw, upload, draw, ..}:
1854 * Flush the gfx IB if we've allocated too much texture storage.
1856 * The idea is that we don't want to build IBs that use too much
1857 * memory and put pressure on the kernel memory manager and we also
1858 * want to make temporary and invalidated buffers go idle ASAP to
1859 * decrease the total memory usage or make them reusable. The memory
1860 * usage will be slightly higher than given here because of the buffer
1861 * cache in the winsys.
1863 * The result is that the kernel memory manager is never a bottleneck.
1865 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1866 si_flush_gfx_cs(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1867 rctx
->num_alloc_tex_transfer_bytes
= 0;
1870 pipe_resource_reference(&transfer
->resource
, NULL
);
1874 static const struct u_resource_vtbl r600_texture_vtbl
=
1876 NULL
, /* get_handle */
1877 r600_texture_destroy
, /* resource_destroy */
1878 r600_texture_transfer_map
, /* transfer_map */
1879 u_default_transfer_flush_region
, /* transfer_flush_region */
1880 r600_texture_transfer_unmap
, /* transfer_unmap */
1883 /* DCC channel type categories within which formats can be reinterpreted
1884 * while keeping the same DCC encoding. The swizzle must also match. */
1885 enum dcc_channel_type
{
1887 /* uint and sint can be merged if we never use TC-compatible DCC clear
1888 * encoding with the clear value of 1. */
1891 dcc_channel_uint_10_10_10_2
,
1892 dcc_channel_incompatible
,
1895 /* Return the type of DCC encoding. */
1896 static enum dcc_channel_type
1897 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1901 /* Find the first non-void channel. */
1902 for (i
= 0; i
< desc
->nr_channels
; i
++)
1903 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1905 if (i
== desc
->nr_channels
)
1906 return dcc_channel_incompatible
;
1908 switch (desc
->channel
[i
].size
) {
1912 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1913 return dcc_channel_float
;
1914 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1915 return dcc_channel_uint
;
1916 return dcc_channel_sint
;
1918 return dcc_channel_uint_10_10_10_2
;
1920 return dcc_channel_incompatible
;
1924 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1925 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1926 enum pipe_format format2
)
1928 const struct util_format_description
*desc1
, *desc2
;
1929 enum dcc_channel_type type1
, type2
;
1932 if (format1
== format2
)
1935 desc1
= util_format_description(format1
);
1936 desc2
= util_format_description(format2
);
1938 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1941 /* Swizzles must be the same. */
1942 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1943 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1944 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1945 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1948 type1
= vi_get_dcc_channel_type(desc1
);
1949 type2
= vi_get_dcc_channel_type(desc2
);
1951 return type1
!= dcc_channel_incompatible
&&
1952 type2
!= dcc_channel_incompatible
&&
1956 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1958 enum pipe_format view_format
)
1960 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1962 return vi_dcc_enabled(rtex
, level
) &&
1963 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1966 /* This can't be merged with the above function, because
1967 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1968 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1969 struct pipe_resource
*tex
,
1971 enum pipe_format view_format
)
1973 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1975 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1976 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1977 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1980 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1981 struct pipe_resource
*texture
,
1982 const struct pipe_surface
*templ
,
1983 unsigned width0
, unsigned height0
,
1984 unsigned width
, unsigned height
)
1986 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1991 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1992 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1994 pipe_reference_init(&surface
->base
.reference
, 1);
1995 pipe_resource_reference(&surface
->base
.texture
, texture
);
1996 surface
->base
.context
= pipe
;
1997 surface
->base
.format
= templ
->format
;
1998 surface
->base
.width
= width
;
1999 surface
->base
.height
= height
;
2000 surface
->base
.u
= templ
->u
;
2002 surface
->width0
= width0
;
2003 surface
->height0
= height0
;
2005 surface
->dcc_incompatible
=
2006 texture
->target
!= PIPE_BUFFER
&&
2007 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2009 return &surface
->base
;
2012 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2013 struct pipe_resource
*tex
,
2014 const struct pipe_surface
*templ
)
2016 unsigned level
= templ
->u
.tex
.level
;
2017 unsigned width
= u_minify(tex
->width0
, level
);
2018 unsigned height
= u_minify(tex
->height0
, level
);
2019 unsigned width0
= tex
->width0
;
2020 unsigned height0
= tex
->height0
;
2022 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2023 const struct util_format_description
*tex_desc
2024 = util_format_description(tex
->format
);
2025 const struct util_format_description
*templ_desc
2026 = util_format_description(templ
->format
);
2028 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2030 /* Adjust size of surface if and only if the block width or
2031 * height is changed. */
2032 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2033 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2034 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2035 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2037 width
= nblks_x
* templ_desc
->block
.width
;
2038 height
= nblks_y
* templ_desc
->block
.height
;
2040 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2041 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2045 return si_create_surface_custom(pipe
, tex
, templ
,
2050 static void r600_surface_destroy(struct pipe_context
*pipe
,
2051 struct pipe_surface
*surface
)
2053 pipe_resource_reference(&surface
->texture
, NULL
);
2057 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2059 const struct util_format_description
*desc
= util_format_description(format
);
2061 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2063 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2064 return V_028C70_SWAP_STD
;
2066 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2069 switch (desc
->nr_channels
) {
2071 if (HAS_SWIZZLE(0,X
))
2072 return V_028C70_SWAP_STD
; /* X___ */
2073 else if (HAS_SWIZZLE(3,X
))
2074 return V_028C70_SWAP_ALT_REV
; /* ___X */
2077 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2078 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2079 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2080 return V_028C70_SWAP_STD
; /* XY__ */
2081 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2082 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2083 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2085 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2086 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2087 return V_028C70_SWAP_ALT
; /* X__Y */
2088 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2089 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2092 if (HAS_SWIZZLE(0,X
))
2093 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2094 else if (HAS_SWIZZLE(0,Z
))
2095 return V_028C70_SWAP_STD_REV
; /* ZYX */
2098 /* check the middle channels, the 1st and 4th channel can be NONE */
2099 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2100 return V_028C70_SWAP_STD
; /* XYZW */
2101 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2102 return V_028C70_SWAP_STD_REV
; /* WZYX */
2103 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2104 return V_028C70_SWAP_ALT
; /* ZYXW */
2105 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2108 return V_028C70_SWAP_ALT_REV
;
2110 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2117 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2119 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2124 if (rctx
->dcc_stats
[slot
].query_active
)
2125 vi_separate_dcc_stop_query(&rctx
->b
,
2126 rctx
->dcc_stats
[slot
].tex
);
2128 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2129 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2130 rctx
->b
.destroy_query(&rctx
->b
,
2131 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2132 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2135 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2139 * Return the per-context slot where DCC statistics queries for the texture live.
2141 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2142 struct r600_texture
*tex
)
2144 int i
, empty_slot
= -1;
2146 /* Remove zombie textures (textures kept alive by this array only). */
2147 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2148 if (rctx
->dcc_stats
[i
].tex
&&
2149 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2150 vi_dcc_clean_up_context_slot(rctx
, i
);
2152 /* Find the texture. */
2153 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2154 /* Return if found. */
2155 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2156 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2160 /* Record the first seen empty slot. */
2161 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2165 /* Not found. Remove the oldest member to make space in the array. */
2166 if (empty_slot
== -1) {
2167 int oldest_slot
= 0;
2169 /* Find the oldest slot. */
2170 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2171 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2172 rctx
->dcc_stats
[i
].last_use_timestamp
)
2175 /* Clean up the oldest slot. */
2176 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2177 empty_slot
= oldest_slot
;
2180 /* Add the texture to the new slot. */
2181 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2182 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2186 static struct pipe_query
*
2187 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2189 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2190 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2192 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2193 return (struct pipe_query
*)query
;
2197 * Called when binding a color buffer.
2199 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2200 struct r600_texture
*tex
)
2202 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2203 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2205 assert(!rctx
->dcc_stats
[i
].query_active
);
2207 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2208 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2210 /* begin or resume the query */
2211 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2212 rctx
->dcc_stats
[i
].query_active
= true;
2216 * Called when unbinding a color buffer.
2218 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2219 struct r600_texture
*tex
)
2221 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2222 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2224 assert(rctx
->dcc_stats
[i
].query_active
);
2225 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2227 /* pause or end the query */
2228 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2229 rctx
->dcc_stats
[i
].query_active
= false;
2232 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2234 /* The minimum number of fullscreen draws per frame that is required
2236 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2239 /* Called by fast clear. */
2240 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2241 struct r600_texture
*tex
)
2243 /* The intent is to use this with shared displayable back buffers,
2244 * but it's not strictly limited only to them.
2246 if (!tex
->resource
.b
.is_shared
||
2247 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2248 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2249 tex
->resource
.b
.b
.last_level
> 0 ||
2250 !tex
->surface
.dcc_size
)
2253 if (tex
->dcc_offset
)
2254 return; /* already enabled */
2256 /* Enable the DCC stat gathering. */
2257 if (!tex
->dcc_gather_statistics
) {
2258 tex
->dcc_gather_statistics
= true;
2259 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2262 if (!vi_should_enable_separate_dcc(tex
))
2263 return; /* stats show that DCC decompression is too expensive */
2265 assert(tex
->surface
.num_dcc_levels
);
2266 assert(!tex
->dcc_separate_buffer
);
2268 si_texture_discard_cmask(rctx
->screen
, tex
);
2270 /* Get a DCC buffer. */
2271 if (tex
->last_dcc_separate_buffer
) {
2272 assert(tex
->dcc_gather_statistics
);
2273 assert(!tex
->dcc_separate_buffer
);
2274 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2275 tex
->last_dcc_separate_buffer
= NULL
;
2277 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2278 si_aligned_buffer_create(rctx
->b
.screen
,
2279 R600_RESOURCE_FLAG_UNMAPPABLE
,
2281 tex
->surface
.dcc_size
,
2282 tex
->surface
.dcc_alignment
);
2283 if (!tex
->dcc_separate_buffer
)
2287 /* dcc_offset is the absolute GPUVM address. */
2288 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2290 /* no need to flag anything since this is called by fast clear that
2291 * flags framebuffer state
2296 * Called by pipe_context::flush_resource, the place where DCC decompression
2299 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2300 struct r600_texture
*tex
)
2302 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2303 struct pipe_query
*tmp
;
2304 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2305 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2306 bool disable
= false;
2308 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2309 union pipe_query_result result
;
2311 /* Read the results. */
2312 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2314 si_query_hw_reset_buffers(rctx
,
2315 (struct r600_query_hw
*)
2316 rctx
->dcc_stats
[i
].ps_stats
[2]);
2318 /* Compute the approximate number of fullscreen draws. */
2319 tex
->ps_draw_ratio
=
2320 result
.pipeline_statistics
.ps_invocations
/
2321 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2322 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2324 disable
= tex
->dcc_separate_buffer
&&
2325 !vi_should_enable_separate_dcc(tex
);
2328 tex
->num_slow_clears
= 0;
2330 /* stop the statistics query for ps_stats[0] */
2332 vi_separate_dcc_stop_query(ctx
, tex
);
2334 /* Move the queries in the queue by one. */
2335 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2336 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2337 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2338 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2340 /* create and start a new query as ps_stats[0] */
2342 vi_separate_dcc_start_query(ctx
, tex
);
2345 assert(!tex
->last_dcc_separate_buffer
);
2346 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2347 tex
->dcc_separate_buffer
= NULL
;
2348 tex
->dcc_offset
= 0;
2349 /* no need to flag anything since this is called after
2350 * decompression that re-sets framebuffer state
2355 static struct pipe_memory_object
*
2356 r600_memobj_from_handle(struct pipe_screen
*screen
,
2357 struct winsys_handle
*whandle
,
2360 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2361 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2362 struct pb_buffer
*buf
= NULL
;
2363 uint32_t stride
, offset
;
2368 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2375 memobj
->b
.dedicated
= dedicated
;
2377 memobj
->stride
= stride
;
2378 memobj
->offset
= offset
;
2380 return (struct pipe_memory_object
*)memobj
;
2385 r600_memobj_destroy(struct pipe_screen
*screen
,
2386 struct pipe_memory_object
*_memobj
)
2388 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2390 pb_reference(&memobj
->buf
, NULL
);
2394 static struct pipe_resource
*
2395 r600_texture_from_memobj(struct pipe_screen
*screen
,
2396 const struct pipe_resource
*templ
,
2397 struct pipe_memory_object
*_memobj
,
2401 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2402 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2403 struct r600_texture
*rtex
;
2404 struct radeon_surf surface
= {};
2405 struct radeon_bo_metadata metadata
= {};
2406 enum radeon_surf_mode array_mode
;
2408 struct pb_buffer
*buf
= NULL
;
2410 if (memobj
->b
.dedicated
) {
2411 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2412 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
2413 &array_mode
, &is_scanout
);
2416 * The bo metadata is unset for un-dedicated images. So we fall
2417 * back to linear. See answer to question 5 of the
2418 * VK_KHX_external_memory spec for some details.
2420 * It is possible that this case isn't going to work if the
2421 * surface pitch isn't correctly aligned by default.
2423 * In order to support it correctly we require multi-image
2424 * metadata to be syncrhonized between radv and radeonsi. The
2425 * semantics of associating multiple image metadata to a memory
2426 * object on the vulkan export side are not concretely defined
2429 * All the use cases we are aware of at the moment for memory
2430 * objects use dedicated allocations. So lets keep the initial
2431 * implementation simple.
2433 * A possible alternative is to attempt to reconstruct the
2434 * tiling information when the TexParameter TEXTURE_TILING_EXT
2437 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2442 r
= r600_init_surface(sscreen
, &surface
, templ
,
2443 array_mode
, memobj
->stride
,
2444 offset
, true, is_scanout
,
2449 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2453 /* r600_texture_create_object doesn't increment refcount of
2454 * memobj->buf, so increment it here.
2456 pb_reference(&buf
, memobj
->buf
);
2458 rtex
->resource
.b
.is_shared
= true;
2459 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2461 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2463 return &rtex
->resource
.b
.b
;
2466 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2467 struct pipe_resource
*resource
,
2470 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2472 /* Buffers only support the linear flag. */
2473 if (resource
->target
== PIPE_BUFFER
)
2474 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2476 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2479 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2482 /* TODO: PIPE_BIND_CURSOR - do we care? */
2486 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2488 sscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2489 sscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2490 sscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2491 sscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2492 sscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2493 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2496 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2498 rctx
->b
.create_surface
= r600_create_surface
;
2499 rctx
->b
.surface_destroy
= r600_surface_destroy
;