2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (rscreen
->chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 rtex
->surface
.u
.gfx9
.offset
[level
] +
197 (box
->y
/ rtex
->surface
.blk_h
*
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (rscreen
->chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (rscreen
->chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(ptex
->nr_samples
<= 1 &&
275 ptex
->array_size
== 1 &&
277 ptex
->last_level
== 0 &&
278 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 flags
|= RADEON_SURF_SCANOUT
;
284 flags
|= RADEON_SURF_IMPORTED
;
285 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
286 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
288 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
289 array_mode
, surface
);
294 if (rscreen
->chip_class
>= GFX9
) {
295 assert(!pitch_in_bytes_override
||
296 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
297 surface
->u
.gfx9
.surf_offset
= offset
;
299 if (pitch_in_bytes_override
&&
300 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
301 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
304 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
305 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
306 surface
->u
.legacy
.level
[0].nblk_y
;
310 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
311 surface
->u
.legacy
.level
[i
].offset
+= offset
;
317 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
318 struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
325 if (rscreen
->chip_class
>= GFX9
) {
326 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
328 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
329 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
330 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
331 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
332 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
333 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
334 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
335 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
336 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
337 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
338 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
339 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
343 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
344 struct r600_texture
*rtex
)
346 struct r600_common_screen
*rscreen
= rctx
->screen
;
347 struct pipe_context
*ctx
= &rctx
->b
;
349 if (ctx
== rscreen
->aux_context
)
350 mtx_lock(&rscreen
->aux_context_lock
);
352 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
353 ctx
->flush(ctx
, NULL
, 0);
355 if (ctx
== rscreen
->aux_context
)
356 mtx_unlock(&rscreen
->aux_context_lock
);
359 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 if (!rtex
->cmask
.size
)
365 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
368 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
369 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
370 rtex
->dirty_level_mask
= 0;
372 if (rscreen
->chip_class
>= SI
)
373 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
375 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
377 if (rtex
->cmask_buffer
!= &rtex
->resource
)
378 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
380 /* Notify all contexts about the change. */
381 p_atomic_inc(&rscreen
->dirty_tex_counter
);
382 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
385 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
387 /* We can't disable DCC if it can be written by another process. */
388 return rtex
->dcc_offset
&&
389 (!rtex
->resource
.b
.is_shared
||
390 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
393 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
)
396 if (!r600_can_disable_dcc(rtex
))
399 assert(rtex
->dcc_separate_buffer
== NULL
);
402 rtex
->dcc_offset
= 0;
404 /* Notify all contexts about the change. */
405 p_atomic_inc(&rscreen
->dirty_tex_counter
);
410 * Disable DCC for the texture. (first decompress, then discard metadata).
412 * There is unresolved multi-context synchronization issue between
413 * screen::aux_context and the current context. If applications do this with
414 * multiple contexts, it's already undefined behavior for them and we don't
415 * have to worry about that. The scenario is:
417 * If context 1 disables DCC and context 2 has queued commands that write
418 * to the texture via CB with DCC enabled, and the order of operations is
420 * context 2 queues draw calls rendering to the texture, but doesn't flush
421 * context 1 disables DCC and flushes
422 * context 1 & 2 reset descriptors and FB state
423 * context 2 flushes (new compressed tiles written by the draw calls)
424 * context 1 & 2 read garbage, because DCC is disabled, yet there are
427 * \param rctx the current context if you have one, or rscreen->aux_context
430 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
431 struct r600_texture
*rtex
)
433 struct r600_common_screen
*rscreen
= rctx
->screen
;
435 if (!r600_can_disable_dcc(rtex
))
438 if (&rctx
->b
== rscreen
->aux_context
)
439 mtx_lock(&rscreen
->aux_context_lock
);
441 /* Decompress DCC. */
442 rctx
->decompress_dcc(&rctx
->b
, rtex
);
443 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
445 if (&rctx
->b
== rscreen
->aux_context
)
446 mtx_unlock(&rscreen
->aux_context_lock
);
448 return r600_texture_discard_dcc(rscreen
, rtex
);
451 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
452 struct r600_texture
*rtex
,
453 unsigned new_bind_flag
,
454 bool invalidate_storage
)
456 struct pipe_screen
*screen
= rctx
->b
.screen
;
457 struct r600_texture
*new_tex
;
458 struct pipe_resource templ
= rtex
->resource
.b
.b
;
461 templ
.bind
|= new_bind_flag
;
463 /* r600g doesn't react to dirty_tex_descriptor_counter */
464 if (rctx
->chip_class
< SI
)
467 if (rtex
->resource
.b
.is_shared
)
470 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
471 if (rtex
->surface
.is_linear
)
474 /* This fails with MSAA, depth, and compressed textures. */
475 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
476 RADEON_SURF_MODE_LINEAR_ALIGNED
)
480 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
484 /* Copy the pixels to the new texture. */
485 if (!invalidate_storage
) {
486 for (i
= 0; i
<= templ
.last_level
; i
++) {
490 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
491 util_max_layer(&templ
, i
) + 1, &box
);
493 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
494 &rtex
->resource
.b
.b
, i
, &box
);
498 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
499 r600_texture_discard_cmask(rctx
->screen
, rtex
);
500 r600_texture_discard_dcc(rctx
->screen
, rtex
);
503 /* Replace the structure fields of rtex. */
504 rtex
->resource
.b
.b
.bind
= templ
.bind
;
505 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
506 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
507 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
508 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
509 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
510 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
511 rtex
->resource
.domains
= new_tex
->resource
.domains
;
512 rtex
->resource
.flags
= new_tex
->resource
.flags
;
513 rtex
->size
= new_tex
->size
;
514 rtex
->db_render_format
= new_tex
->db_render_format
;
515 rtex
->db_compatible
= new_tex
->db_compatible
;
516 rtex
->can_sample_z
= new_tex
->can_sample_z
;
517 rtex
->can_sample_s
= new_tex
->can_sample_s
;
518 rtex
->surface
= new_tex
->surface
;
519 rtex
->fmask
= new_tex
->fmask
;
520 rtex
->cmask
= new_tex
->cmask
;
521 rtex
->cb_color_info
= new_tex
->cb_color_info
;
522 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
523 rtex
->htile_offset
= new_tex
->htile_offset
;
524 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
525 rtex
->depth_cleared
= new_tex
->depth_cleared
;
526 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
527 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
528 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
529 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
531 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
532 assert(!rtex
->htile_offset
);
533 assert(!rtex
->cmask
.size
);
534 assert(!rtex
->fmask
.size
);
535 assert(!rtex
->dcc_offset
);
536 assert(!rtex
->is_depth
);
539 r600_texture_reference(&new_tex
, NULL
);
541 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
544 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
545 struct pipe_context
*ctx
,
546 struct pipe_resource
*resource
,
547 struct winsys_handle
*whandle
,
550 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
551 struct r600_common_context
*rctx
;
552 struct r600_resource
*res
= (struct r600_resource
*)resource
;
553 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
554 struct radeon_bo_metadata metadata
;
555 bool update_metadata
= false;
556 unsigned stride
, offset
, slice_size
;
558 ctx
= threaded_context_unwrap_sync(ctx
);
559 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
561 if (resource
->target
!= PIPE_BUFFER
) {
562 /* This is not supported now, but it might be required for OpenCL
563 * interop in the future.
565 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
568 /* Move a suballocated texture into a non-suballocated allocation. */
569 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
570 assert(!res
->b
.is_shared
);
571 r600_reallocate_texture_inplace(rctx
, rtex
,
572 PIPE_BIND_SHARED
, false);
573 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
574 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
575 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
578 /* Since shader image stores don't support DCC on VI,
579 * disable it for external clients that want write
582 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
583 if (r600_texture_disable_dcc(rctx
, rtex
))
584 update_metadata
= true;
587 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
588 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
589 /* Eliminate fast clear (both CMASK and DCC) */
590 r600_eliminate_fast_color_clear(rctx
, rtex
);
592 /* Disable CMASK if flush_resource isn't going
595 if (rtex
->cmask
.size
)
596 r600_texture_discard_cmask(rscreen
, rtex
);
600 if (!res
->b
.is_shared
|| update_metadata
) {
601 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
602 if (rscreen
->query_opaque_metadata
)
603 rscreen
->query_opaque_metadata(rscreen
, rtex
,
606 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
609 if (rscreen
->chip_class
>= GFX9
) {
610 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
611 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
613 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
615 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
616 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
618 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
627 if (res
->b
.is_shared
) {
628 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
631 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
632 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
633 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
635 res
->b
.is_shared
= true;
636 res
->external_usage
= usage
;
639 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
640 slice_size
, whandle
);
643 static void r600_texture_destroy(struct pipe_screen
*screen
,
644 struct pipe_resource
*ptex
)
646 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
647 struct r600_resource
*resource
= &rtex
->resource
;
649 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
651 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
652 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
654 pb_reference(&resource
->buf
, NULL
);
655 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
656 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
660 static const struct u_resource_vtbl r600_texture_vtbl
;
662 /* The number of samples can be specified independently of the texture. */
663 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
664 struct r600_texture
*rtex
,
666 struct r600_fmask_info
*out
)
668 /* FMASK is allocated like an ordinary texture. */
669 struct pipe_resource templ
= rtex
->resource
.b
.b
;
670 struct radeon_surf fmask
= {};
673 memset(out
, 0, sizeof(*out
));
675 if (rscreen
->chip_class
>= GFX9
) {
676 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
677 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
681 templ
.nr_samples
= 1;
682 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
684 if (rscreen
->chip_class
<= CAYMAN
) {
685 /* Use the same parameters and tile mode. */
686 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
687 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
688 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
689 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
692 fmask
.u
.legacy
.bankh
= 4;
695 switch (nr_samples
) {
704 R600_ERR("Invalid sample count for FMASK allocation.\n");
708 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
709 * This can be fixed by writing a separate FMASK allocator specifically
710 * for R600-R700 asics. */
711 if (rscreen
->chip_class
<= R700
) {
715 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
716 RADEON_SURF_MODE_2D
, &fmask
)) {
717 R600_ERR("Got error in surface_init while allocating FMASK.\n");
721 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
723 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
724 if (out
->slice_tile_max
)
725 out
->slice_tile_max
-= 1;
727 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
728 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
729 out
->bank_height
= fmask
.u
.legacy
.bankh
;
730 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
731 out
->size
= fmask
.surf_size
;
734 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
735 struct r600_texture
*rtex
)
737 r600_texture_get_fmask_info(rscreen
, rtex
,
738 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
740 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
741 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
744 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
745 struct r600_texture
*rtex
,
746 struct r600_cmask_info
*out
)
748 unsigned cmask_tile_width
= 8;
749 unsigned cmask_tile_height
= 8;
750 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
751 unsigned element_bits
= 4;
752 unsigned cmask_cache_bits
= 1024;
753 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
754 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
756 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
757 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
758 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
759 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
760 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
762 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
763 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
765 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
766 unsigned slice_bytes
=
767 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
769 assert(macro_tile_width
% 128 == 0);
770 assert(macro_tile_height
% 128 == 0);
772 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
773 out
->alignment
= MAX2(256, base_align
);
774 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
775 align(slice_bytes
, base_align
);
778 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
779 struct r600_texture
*rtex
,
780 struct r600_cmask_info
*out
)
782 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
783 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
784 unsigned cl_width
, cl_height
;
786 if (rscreen
->chip_class
>= GFX9
) {
787 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
788 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
805 case 16: /* Hawaii */
814 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
816 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
817 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
818 unsigned slice_elements
= (width
* height
) / (8*8);
820 /* Each element of CMASK is a nibble. */
821 unsigned slice_bytes
= slice_elements
/ 2;
823 out
->slice_tile_max
= (width
* height
) / (128*128);
824 if (out
->slice_tile_max
)
825 out
->slice_tile_max
-= 1;
827 out
->alignment
= MAX2(256, base_align
);
828 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
829 align(slice_bytes
, base_align
);
832 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
833 struct r600_texture
*rtex
)
835 if (rscreen
->chip_class
>= SI
) {
836 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
838 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
841 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
842 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
844 if (rscreen
->chip_class
>= SI
)
845 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
847 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
850 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
851 struct r600_texture
*rtex
)
853 if (rtex
->cmask_buffer
)
856 assert(rtex
->cmask
.size
== 0);
858 if (rscreen
->chip_class
>= SI
) {
859 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
861 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
864 rtex
->cmask_buffer
= (struct r600_resource
*)
865 r600_aligned_buffer_create(&rscreen
->b
,
866 R600_RESOURCE_FLAG_UNMAPPABLE
,
869 rtex
->cmask
.alignment
);
870 if (rtex
->cmask_buffer
== NULL
) {
871 rtex
->cmask
.size
= 0;
875 /* update colorbuffer state bits */
876 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
878 if (rscreen
->chip_class
>= SI
)
879 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
881 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
883 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
886 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
887 struct r600_texture
*rtex
)
889 unsigned cl_width
, cl_height
, width
, height
;
890 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
891 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
893 assert(rscreen
->chip_class
<= VI
);
895 rtex
->surface
.htile_size
= 0;
897 if (rscreen
->chip_class
<= EVERGREEN
&&
898 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
901 /* HW bug on R6xx. */
902 if (rscreen
->chip_class
== R600
&&
903 (rtex
->resource
.b
.b
.width0
> 7680 ||
904 rtex
->resource
.b
.b
.height0
> 7680))
907 /* HTILE is broken with 1D tiling on old kernels and CIK. */
908 if (rscreen
->chip_class
>= CIK
&&
909 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
910 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
913 /* Overalign HTILE on P2 configs to work around GPU hangs in
914 * piglit/depthstencil-render-miplevels 585.
916 * This has been confirmed to help Kabini & Stoney, where the hangs
917 * are always reproducible. I think I have seen the test hang
918 * on Carrizo too, though it was very rare there.
920 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
949 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
950 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
952 slice_elements
= (width
* height
) / (8 * 8);
953 slice_bytes
= slice_elements
* 4;
955 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
956 base_align
= num_pipes
* pipe_interleave_bytes
;
958 rtex
->surface
.htile_alignment
= base_align
;
959 rtex
->surface
.htile_size
=
960 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
961 align(slice_bytes
, base_align
);
964 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
965 struct r600_texture
*rtex
)
967 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
968 r600_texture_get_htile_size(rscreen
, rtex
);
970 if (!rtex
->surface
.htile_size
)
973 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
974 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
977 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
978 struct r600_texture
*rtex
, FILE *f
)
982 /* Common parameters. */
983 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
984 "blk_h=%u, array_size=%u, last_level=%u, "
985 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
986 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
987 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
989 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
990 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
991 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
993 if (rscreen
->chip_class
>= GFX9
) {
994 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
995 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
996 rtex
->surface
.surf_size
,
997 rtex
->surface
.u
.gfx9
.surf_slice_size
,
998 rtex
->surface
.surf_alignment
,
999 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1000 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1001 rtex
->surface
.u
.gfx9
.surf_pitch
);
1003 if (rtex
->fmask
.size
) {
1004 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1005 "alignment=%u, swmode=%u, epitch=%u\n",
1007 rtex
->surface
.u
.gfx9
.fmask_size
,
1008 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1009 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1010 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1013 if (rtex
->cmask
.size
) {
1014 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1015 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1017 rtex
->surface
.u
.gfx9
.cmask_size
,
1018 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1019 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1020 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1023 if (rtex
->htile_offset
) {
1024 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1025 "rb_aligned=%u, pipe_aligned=%u\n",
1027 rtex
->surface
.htile_size
,
1028 rtex
->surface
.htile_alignment
,
1029 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1030 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1033 if (rtex
->dcc_offset
) {
1034 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1035 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1036 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1037 rtex
->surface
.dcc_alignment
,
1038 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1039 rtex
->surface
.num_dcc_levels
);
1042 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1043 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1044 rtex
->surface
.u
.gfx9
.stencil_offset
,
1045 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1046 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1051 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1052 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1053 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1054 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1055 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1056 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1058 if (rtex
->fmask
.size
)
1059 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1060 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1061 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1062 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1063 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1065 if (rtex
->cmask
.size
)
1066 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1067 "slice_tile_max=%u\n",
1068 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1069 rtex
->cmask
.slice_tile_max
);
1071 if (rtex
->htile_offset
)
1072 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1073 "alignment=%u, TC_compatible = %u\n",
1074 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1075 rtex
->surface
.htile_alignment
,
1076 rtex
->tc_compatible_htile
);
1078 if (rtex
->dcc_offset
) {
1079 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1080 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1081 rtex
->surface
.dcc_alignment
);
1082 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1083 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1084 "fast_clear_size=%"PRIu64
"\n",
1085 i
, i
< rtex
->surface
.num_dcc_levels
,
1086 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1087 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1090 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1091 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1092 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1093 "mode=%u, tiling_index = %u\n",
1094 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1095 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1096 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1097 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1098 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1099 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1100 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1101 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1102 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1104 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1105 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1106 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1107 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1108 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1109 "slice_size=%"PRIu64
", npix_x=%u, "
1110 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1111 "mode=%u, tiling_index = %u\n",
1112 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1113 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1114 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1115 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1116 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1117 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1118 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1119 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1120 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1125 /* Common processing for r600_texture_create and r600_texture_from_handle */
1126 static struct r600_texture
*
1127 r600_texture_create_object(struct pipe_screen
*screen
,
1128 const struct pipe_resource
*base
,
1129 struct pb_buffer
*buf
,
1130 struct radeon_surf
*surface
)
1132 struct r600_texture
*rtex
;
1133 struct r600_resource
*resource
;
1134 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1136 rtex
= CALLOC_STRUCT(r600_texture
);
1140 resource
= &rtex
->resource
;
1141 resource
->b
.b
= *base
;
1142 resource
->b
.b
.next
= NULL
;
1143 resource
->b
.vtbl
= &r600_texture_vtbl
;
1144 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1145 resource
->b
.b
.screen
= screen
;
1147 /* don't include stencil-only formats which we don't support for rendering */
1148 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1150 rtex
->surface
= *surface
;
1151 rtex
->size
= rtex
->surface
.surf_size
;
1153 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1154 (rtex
->surface
.flags
&
1155 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1157 /* TC-compatible HTILE:
1158 * - VI only supports Z32_FLOAT.
1159 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1160 if (rtex
->tc_compatible_htile
) {
1161 if (rscreen
->chip_class
>= GFX9
&&
1162 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1163 rtex
->db_render_format
= base
->format
;
1165 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1167 rtex
->db_render_format
= base
->format
;
1170 /* Tiled depth textures utilize the non-displayable tile order.
1171 * This must be done after r600_setup_surface.
1172 * Applies to R600-Cayman. */
1173 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1174 /* Applies to GCN. */
1175 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1177 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1178 * between frames, so the only thing that can enable separate DCC
1179 * with DRI2 is multiple slow clears within a frame.
1181 rtex
->ps_draw_ratio
= 0;
1183 if (rtex
->is_depth
) {
1184 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1185 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1186 rscreen
->chip_class
>= EVERGREEN
) {
1187 if (rscreen
->chip_class
>= GFX9
) {
1188 rtex
->can_sample_z
= true;
1189 rtex
->can_sample_s
= true;
1191 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1192 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1195 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1196 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1197 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1198 rtex
->can_sample_z
= true;
1201 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1202 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1203 rtex
->db_compatible
= true;
1205 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1206 r600_texture_allocate_htile(rscreen
, rtex
);
1209 if (base
->nr_samples
> 1) {
1211 r600_texture_allocate_fmask(rscreen
, rtex
);
1212 r600_texture_allocate_cmask(rscreen
, rtex
);
1213 rtex
->cmask_buffer
= &rtex
->resource
;
1215 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1221 /* Shared textures must always set up DCC here.
1222 * If it's not present, it will be disabled by
1223 * apply_opaque_metadata later.
1225 if (rtex
->surface
.dcc_size
&&
1226 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1227 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1228 /* Reserve space for the DCC buffer. */
1229 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1230 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1234 /* Now create the backing buffer. */
1236 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1237 rtex
->surface
.surf_alignment
);
1239 /* Displayable surfaces are not suballocated. */
1240 if (resource
->b
.b
.bind
& PIPE_BIND_SCANOUT
)
1241 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
1243 if (!r600_alloc_resource(rscreen
, resource
)) {
1248 resource
->buf
= buf
;
1249 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1250 resource
->bo_size
= buf
->size
;
1251 resource
->bo_alignment
= buf
->alignment
;
1252 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1253 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1254 resource
->vram_usage
= buf
->size
;
1255 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1256 resource
->gart_usage
= buf
->size
;
1259 if (rtex
->cmask
.size
) {
1260 /* Initialize the cmask to 0xCC (= compressed state). */
1261 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1262 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1265 if (rtex
->htile_offset
) {
1266 uint32_t clear_value
= 0;
1268 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1269 clear_value
= 0x0000030F;
1271 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1273 rtex
->surface
.htile_size
,
1277 /* Initialize DCC only if the texture is not being imported. */
1278 if (!buf
&& rtex
->dcc_offset
) {
1279 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1281 rtex
->surface
.dcc_size
,
1285 /* Initialize the CMASK base register value. */
1286 rtex
->cmask
.base_address_reg
=
1287 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1289 if (rscreen
->debug_flags
& DBG_VM
) {
1290 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1291 rtex
->resource
.gpu_address
,
1292 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1293 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1294 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1297 if (rscreen
->debug_flags
& DBG_TEX
) {
1299 r600_print_texture_info(rscreen
, rtex
, stdout
);
1306 static enum radeon_surf_mode
1307 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1308 const struct pipe_resource
*templ
)
1310 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1311 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1312 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1313 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1315 /* MSAA resources must be 2D tiled. */
1316 if (templ
->nr_samples
> 1)
1317 return RADEON_SURF_MODE_2D
;
1319 /* Transfer resources should be linear. */
1320 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1321 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1323 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1324 * which requires 2D tiling.
1326 if (rscreen
->chip_class
== VI
&&
1328 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1329 return RADEON_SURF_MODE_2D
;
1331 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1332 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1333 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1334 (templ
->target
== PIPE_TEXTURE_2D
||
1335 templ
->target
== PIPE_TEXTURE_3D
))
1336 force_tiling
= true;
1338 /* Handle common candidates for the linear mode.
1339 * Compressed textures and DB surfaces must always be tiled.
1341 if (!force_tiling
&&
1342 !is_depth_stencil
&&
1343 !util_format_is_compressed(templ
->format
)) {
1344 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1345 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1347 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1348 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1349 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1351 /* Cursors are linear on SI.
1352 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1353 if (rscreen
->chip_class
>= SI
&&
1354 (templ
->bind
& PIPE_BIND_CURSOR
))
1355 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1357 if (templ
->bind
& PIPE_BIND_LINEAR
)
1358 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1360 /* Textures with a very small height are recommended to be linear. */
1361 if (templ
->target
== PIPE_TEXTURE_1D
||
1362 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1363 /* Only very thin and long 2D textures should benefit from
1364 * linear_aligned. */
1365 (templ
->width0
> 8 && templ
->height0
<= 2))
1366 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1368 /* Textures likely to be mapped often. */
1369 if (templ
->usage
== PIPE_USAGE_STAGING
||
1370 templ
->usage
== PIPE_USAGE_STREAM
)
1371 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1374 /* Make small textures 1D tiled. */
1375 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1376 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1377 return RADEON_SURF_MODE_1D
;
1379 /* The allocator will switch to 1D if needed. */
1380 return RADEON_SURF_MODE_2D
;
1383 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1384 const struct pipe_resource
*templ
)
1386 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1387 struct radeon_surf surface
= {0};
1388 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1389 bool tc_compatible_htile
=
1390 rscreen
->chip_class
>= VI
&&
1391 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1392 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1393 !is_flushed_depth
&&
1394 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1395 util_format_is_depth_or_stencil(templ
->format
);
1399 r
= r600_init_surface(rscreen
, &surface
, templ
,
1400 r600_choose_tiling(rscreen
, templ
), 0, 0,
1401 false, false, is_flushed_depth
,
1402 tc_compatible_htile
);
1407 return (struct pipe_resource
*)
1408 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1411 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1412 const struct pipe_resource
*templ
,
1413 struct winsys_handle
*whandle
,
1416 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1417 struct pb_buffer
*buf
= NULL
;
1418 unsigned stride
= 0, offset
= 0;
1419 unsigned array_mode
;
1420 struct radeon_surf surface
;
1422 struct radeon_bo_metadata metadata
= {};
1423 struct r600_texture
*rtex
;
1426 /* Support only 2D textures without mipmaps */
1427 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1428 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1431 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1435 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1437 if (rscreen
->chip_class
>= GFX9
) {
1438 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1439 array_mode
= RADEON_SURF_MODE_2D
;
1441 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1443 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1444 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1446 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1447 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1448 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1449 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1450 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1451 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1453 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1454 array_mode
= RADEON_SURF_MODE_2D
;
1455 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1456 array_mode
= RADEON_SURF_MODE_1D
;
1458 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1460 is_scanout
= metadata
.u
.legacy
.scanout
;
1463 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1464 offset
, true, is_scanout
, false, false);
1469 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1473 rtex
->resource
.b
.is_shared
= true;
1474 rtex
->resource
.external_usage
= usage
;
1476 if (rscreen
->apply_opaque_metadata
)
1477 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1479 /* Validate that addrlib arrived at the same surface parameters. */
1480 if (rscreen
->chip_class
>= GFX9
) {
1481 assert(metadata
.u
.gfx9
.swizzle_mode
== surface
.u
.gfx9
.surf
.swizzle_mode
);
1484 return &rtex
->resource
.b
.b
;
1487 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1488 struct pipe_resource
*texture
,
1489 struct r600_texture
**staging
)
1491 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1492 struct pipe_resource resource
;
1493 struct r600_texture
**flushed_depth_texture
= staging
?
1494 staging
: &rtex
->flushed_depth_texture
;
1495 enum pipe_format pipe_format
= texture
->format
;
1498 if (rtex
->flushed_depth_texture
)
1499 return true; /* it's ready */
1501 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1502 switch (pipe_format
) {
1503 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1504 /* Save memory by not allocating the S plane. */
1505 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1507 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1508 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1509 /* Save memory bandwidth by not copying the
1510 * stencil part during flush.
1512 * This potentially increases memory bandwidth
1513 * if an application uses both Z and S texturing
1514 * simultaneously (a flushed Z24S8 texture
1515 * would be stored compactly), but how often
1516 * does that really happen?
1518 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1522 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1523 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1525 /* DB->CB copies to an 8bpp surface don't work. */
1526 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1530 memset(&resource
, 0, sizeof(resource
));
1531 resource
.target
= texture
->target
;
1532 resource
.format
= pipe_format
;
1533 resource
.width0
= texture
->width0
;
1534 resource
.height0
= texture
->height0
;
1535 resource
.depth0
= texture
->depth0
;
1536 resource
.array_size
= texture
->array_size
;
1537 resource
.last_level
= texture
->last_level
;
1538 resource
.nr_samples
= texture
->nr_samples
;
1539 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1540 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1541 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1544 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1546 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1547 if (*flushed_depth_texture
== NULL
) {
1548 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1552 (*flushed_depth_texture
)->non_disp_tiling
= false;
1557 * Initialize the pipe_resource descriptor to be of the same size as the box,
1558 * which is supposed to hold a subregion of the texture "orig" at the given
1561 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1562 struct pipe_resource
*orig
,
1563 const struct pipe_box
*box
,
1564 unsigned level
, unsigned flags
)
1566 memset(res
, 0, sizeof(*res
));
1567 res
->format
= orig
->format
;
1568 res
->width0
= box
->width
;
1569 res
->height0
= box
->height
;
1571 res
->array_size
= 1;
1572 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1575 /* We must set the correct texture target and dimensions for a 3D box. */
1576 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1577 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1578 res
->array_size
= box
->depth
;
1580 res
->target
= PIPE_TEXTURE_2D
;
1584 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1585 struct r600_texture
*rtex
,
1586 unsigned transfer_usage
,
1587 const struct pipe_box
*box
)
1589 /* r600g doesn't react to dirty_tex_descriptor_counter */
1590 return rscreen
->chip_class
>= SI
&&
1591 !rtex
->resource
.b
.is_shared
&&
1592 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1593 rtex
->resource
.b
.b
.last_level
== 0 &&
1594 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1595 box
->x
, box
->y
, box
->z
,
1596 box
->width
, box
->height
,
1600 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1601 struct r600_texture
*rtex
)
1603 struct r600_common_screen
*rscreen
= rctx
->screen
;
1605 /* There is no point in discarding depth and tiled buffers. */
1606 assert(!rtex
->is_depth
);
1607 assert(rtex
->surface
.is_linear
);
1609 /* Reallocate the buffer in the same pipe_resource. */
1610 r600_alloc_resource(rscreen
, &rtex
->resource
);
1612 /* Initialize the CMASK base address (needed even without CMASK). */
1613 rtex
->cmask
.base_address_reg
=
1614 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1616 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1618 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1621 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1622 struct pipe_resource
*texture
,
1625 const struct pipe_box
*box
,
1626 struct pipe_transfer
**ptransfer
)
1628 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1629 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1630 struct r600_transfer
*trans
;
1631 struct r600_resource
*buf
;
1632 unsigned offset
= 0;
1634 bool use_staging_texture
= false;
1636 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1637 assert(box
->width
&& box
->height
&& box
->depth
);
1639 /* Depth textures use staging unconditionally. */
1640 if (!rtex
->is_depth
) {
1641 /* Degrade the tile mode if we get too many transfers on APUs.
1642 * On dGPUs, the staging texture is always faster.
1643 * Only count uploads that are at least 4x4 pixels large.
1645 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1647 box
->width
>= 4 && box
->height
>= 4 &&
1648 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1649 bool can_invalidate
=
1650 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1653 r600_reallocate_texture_inplace(rctx
, rtex
,
1658 /* Tiled textures need to be converted into a linear texture for CPU
1659 * access. The staging texture is always linear and is placed in GART.
1661 * Reading from VRAM or GTT WC is slow, always use the staging
1662 * texture in this case.
1664 * Use the staging texture for uploads if the underlying BO
1667 if (!rtex
->surface
.is_linear
)
1668 use_staging_texture
= true;
1669 else if (usage
& PIPE_TRANSFER_READ
)
1670 use_staging_texture
=
1671 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1672 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1673 /* Write & linear only: */
1674 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1675 RADEON_USAGE_READWRITE
) ||
1676 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1677 RADEON_USAGE_READWRITE
)) {
1679 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1681 r600_texture_invalidate_storage(rctx
, rtex
);
1683 use_staging_texture
= true;
1687 trans
= CALLOC_STRUCT(r600_transfer
);
1690 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1691 trans
->b
.b
.level
= level
;
1692 trans
->b
.b
.usage
= usage
;
1693 trans
->b
.b
.box
= *box
;
1695 if (rtex
->is_depth
) {
1696 struct r600_texture
*staging_depth
;
1698 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1699 /* MSAA depth buffers need to be converted to single sample buffers.
1701 * Mapping MSAA depth buffers can occur if ReadPixels is called
1702 * with a multisample GLX visual.
1704 * First downsample the depth buffer to a temporary texture,
1705 * then decompress the temporary one to staging.
1707 * Only the region being mapped is transfered.
1709 struct pipe_resource resource
;
1711 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1713 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1714 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1719 if (usage
& PIPE_TRANSFER_READ
) {
1720 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1722 R600_ERR("failed to create a temporary depth texture\n");
1727 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1728 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1729 0, 0, 0, box
->depth
, 0, 0);
1730 pipe_resource_reference(&temp
, NULL
);
1733 /* Just get the strides. */
1734 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1736 &trans
->b
.b
.layer_stride
);
1738 /* XXX: only readback the rectangle which is being mapped? */
1739 /* XXX: when discard is true, no need to read back from depth texture */
1740 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1741 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1746 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1748 box
->z
, box
->z
+ box
->depth
- 1,
1751 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1754 &trans
->b
.b
.layer_stride
);
1757 trans
->staging
= (struct r600_resource
*)staging_depth
;
1758 buf
= trans
->staging
;
1759 } else if (use_staging_texture
) {
1760 struct pipe_resource resource
;
1761 struct r600_texture
*staging
;
1763 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1764 R600_RESOURCE_FLAG_TRANSFER
);
1765 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1766 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1768 /* Create the temporary texture. */
1769 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1771 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1775 trans
->staging
= &staging
->resource
;
1777 /* Just get the strides. */
1778 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1780 &trans
->b
.b
.layer_stride
);
1782 if (usage
& PIPE_TRANSFER_READ
)
1783 r600_copy_to_staging_texture(ctx
, trans
);
1785 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1787 buf
= trans
->staging
;
1789 /* the resource is mapped directly */
1790 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1792 &trans
->b
.b
.layer_stride
);
1793 buf
= &rtex
->resource
;
1796 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1797 r600_resource_reference(&trans
->staging
, NULL
);
1802 *ptransfer
= &trans
->b
.b
;
1803 return map
+ offset
;
1806 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1807 struct pipe_transfer
* transfer
)
1809 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1810 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1811 struct pipe_resource
*texture
= transfer
->resource
;
1812 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1814 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1815 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1816 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1817 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1818 &rtransfer
->staging
->b
.b
, transfer
->level
,
1821 r600_copy_from_staging_texture(ctx
, rtransfer
);
1825 if (rtransfer
->staging
) {
1826 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1827 r600_resource_reference(&rtransfer
->staging
, NULL
);
1830 /* Heuristic for {upload, draw, upload, draw, ..}:
1832 * Flush the gfx IB if we've allocated too much texture storage.
1834 * The idea is that we don't want to build IBs that use too much
1835 * memory and put pressure on the kernel memory manager and we also
1836 * want to make temporary and invalidated buffers go idle ASAP to
1837 * decrease the total memory usage or make them reusable. The memory
1838 * usage will be slightly higher than given here because of the buffer
1839 * cache in the winsys.
1841 * The result is that the kernel memory manager is never a bottleneck.
1843 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1844 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1845 rctx
->num_alloc_tex_transfer_bytes
= 0;
1848 pipe_resource_reference(&transfer
->resource
, NULL
);
1852 static const struct u_resource_vtbl r600_texture_vtbl
=
1854 NULL
, /* get_handle */
1855 r600_texture_destroy
, /* resource_destroy */
1856 r600_texture_transfer_map
, /* transfer_map */
1857 u_default_transfer_flush_region
, /* transfer_flush_region */
1858 r600_texture_transfer_unmap
, /* transfer_unmap */
1861 /* DCC channel type categories within which formats can be reinterpreted
1862 * while keeping the same DCC encoding. The swizzle must also match. */
1863 enum dcc_channel_type
{
1864 dcc_channel_float32
,
1867 dcc_channel_float16
,
1870 dcc_channel_uint_10_10_10_2
,
1873 dcc_channel_incompatible
,
1876 /* Return the type of DCC encoding. */
1877 static enum dcc_channel_type
1878 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1882 /* Find the first non-void channel. */
1883 for (i
= 0; i
< desc
->nr_channels
; i
++)
1884 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1886 if (i
== desc
->nr_channels
)
1887 return dcc_channel_incompatible
;
1889 switch (desc
->channel
[i
].size
) {
1891 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1892 return dcc_channel_float32
;
1893 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1894 return dcc_channel_uint32
;
1895 return dcc_channel_sint32
;
1897 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1898 return dcc_channel_float16
;
1899 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1900 return dcc_channel_uint16
;
1901 return dcc_channel_sint16
;
1903 return dcc_channel_uint_10_10_10_2
;
1905 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1906 return dcc_channel_uint8
;
1907 return dcc_channel_sint8
;
1909 return dcc_channel_incompatible
;
1913 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1914 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1915 enum pipe_format format2
)
1917 const struct util_format_description
*desc1
, *desc2
;
1918 enum dcc_channel_type type1
, type2
;
1921 if (format1
== format2
)
1924 desc1
= util_format_description(format1
);
1925 desc2
= util_format_description(format2
);
1927 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1930 /* Swizzles must be the same. */
1931 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1932 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1933 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1934 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1937 type1
= vi_get_dcc_channel_type(desc1
);
1938 type2
= vi_get_dcc_channel_type(desc2
);
1940 return type1
!= dcc_channel_incompatible
&&
1941 type2
!= dcc_channel_incompatible
&&
1945 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1947 enum pipe_format view_format
)
1949 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1951 return vi_dcc_enabled(rtex
, level
) &&
1952 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1955 /* This can't be merged with the above function, because
1956 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1957 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1958 struct pipe_resource
*tex
,
1960 enum pipe_format view_format
)
1962 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1964 if (vi_dcc_enabled(rtex
, level
) &&
1965 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1966 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1967 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1970 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1971 struct pipe_resource
*texture
,
1972 const struct pipe_surface
*templ
,
1973 unsigned width0
, unsigned height0
,
1974 unsigned width
, unsigned height
)
1976 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1981 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1982 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1984 pipe_reference_init(&surface
->base
.reference
, 1);
1985 pipe_resource_reference(&surface
->base
.texture
, texture
);
1986 surface
->base
.context
= pipe
;
1987 surface
->base
.format
= templ
->format
;
1988 surface
->base
.width
= width
;
1989 surface
->base
.height
= height
;
1990 surface
->base
.u
= templ
->u
;
1992 surface
->width0
= width0
;
1993 surface
->height0
= height0
;
1995 surface
->dcc_incompatible
=
1996 texture
->target
!= PIPE_BUFFER
&&
1997 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1999 return &surface
->base
;
2002 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2003 struct pipe_resource
*tex
,
2004 const struct pipe_surface
*templ
)
2006 unsigned level
= templ
->u
.tex
.level
;
2007 unsigned width
= u_minify(tex
->width0
, level
);
2008 unsigned height
= u_minify(tex
->height0
, level
);
2009 unsigned width0
= tex
->width0
;
2010 unsigned height0
= tex
->height0
;
2012 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2013 const struct util_format_description
*tex_desc
2014 = util_format_description(tex
->format
);
2015 const struct util_format_description
*templ_desc
2016 = util_format_description(templ
->format
);
2018 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2020 /* Adjust size of surface if and only if the block width or
2021 * height is changed. */
2022 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2023 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2024 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2025 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2027 width
= nblks_x
* templ_desc
->block
.width
;
2028 height
= nblks_y
* templ_desc
->block
.height
;
2030 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2031 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2035 return r600_create_surface_custom(pipe
, tex
, templ
,
2040 static void r600_surface_destroy(struct pipe_context
*pipe
,
2041 struct pipe_surface
*surface
)
2043 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
2044 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
2045 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
2046 pipe_resource_reference(&surface
->texture
, NULL
);
2050 static void r600_clear_texture(struct pipe_context
*pipe
,
2051 struct pipe_resource
*tex
,
2053 const struct pipe_box
*box
,
2056 struct pipe_screen
*screen
= pipe
->screen
;
2057 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2058 struct pipe_surface tmpl
= {{0}};
2059 struct pipe_surface
*sf
;
2060 const struct util_format_description
*desc
=
2061 util_format_description(tex
->format
);
2063 tmpl
.format
= tex
->format
;
2064 tmpl
.u
.tex
.first_layer
= box
->z
;
2065 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2066 tmpl
.u
.tex
.level
= level
;
2067 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2071 if (rtex
->is_depth
) {
2074 uint8_t stencil
= 0;
2076 /* Depth is always present. */
2077 clear
= PIPE_CLEAR_DEPTH
;
2078 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2080 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2081 clear
|= PIPE_CLEAR_STENCIL
;
2082 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2085 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2087 box
->width
, box
->height
, false);
2089 union pipe_color_union color
;
2091 /* pipe_color_union requires the full vec4 representation. */
2092 if (util_format_is_pure_uint(tex
->format
))
2093 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2094 else if (util_format_is_pure_sint(tex
->format
))
2095 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2097 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2099 if (screen
->is_format_supported(screen
, tex
->format
,
2101 PIPE_BIND_RENDER_TARGET
)) {
2102 pipe
->clear_render_target(pipe
, sf
, &color
,
2104 box
->width
, box
->height
, false);
2106 /* Software fallback - just for R9G9B9E5_FLOAT */
2107 util_clear_render_target(pipe
, sf
, &color
,
2109 box
->width
, box
->height
);
2112 pipe_surface_reference(&sf
, NULL
);
2115 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2117 const struct util_format_description
*desc
= util_format_description(format
);
2119 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2121 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2122 return V_0280A0_SWAP_STD
;
2124 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2127 switch (desc
->nr_channels
) {
2129 if (HAS_SWIZZLE(0,X
))
2130 return V_0280A0_SWAP_STD
; /* X___ */
2131 else if (HAS_SWIZZLE(3,X
))
2132 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2135 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2136 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2137 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2138 return V_0280A0_SWAP_STD
; /* XY__ */
2139 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2140 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2141 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2143 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2144 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2145 return V_0280A0_SWAP_ALT
; /* X__Y */
2146 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2147 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2150 if (HAS_SWIZZLE(0,X
))
2151 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2152 else if (HAS_SWIZZLE(0,Z
))
2153 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2156 /* check the middle channels, the 1st and 4th channel can be NONE */
2157 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2158 return V_0280A0_SWAP_STD
; /* XYZW */
2159 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2160 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2161 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2162 return V_0280A0_SWAP_ALT
; /* ZYXW */
2163 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2166 return V_0280A0_SWAP_ALT_REV
;
2168 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2175 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2177 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2182 if (rctx
->dcc_stats
[slot
].query_active
)
2183 vi_separate_dcc_stop_query(&rctx
->b
,
2184 rctx
->dcc_stats
[slot
].tex
);
2186 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2187 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2188 rctx
->b
.destroy_query(&rctx
->b
,
2189 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2190 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2193 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2197 * Return the per-context slot where DCC statistics queries for the texture live.
2199 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2200 struct r600_texture
*tex
)
2202 int i
, empty_slot
= -1;
2204 /* Remove zombie textures (textures kept alive by this array only). */
2205 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2206 if (rctx
->dcc_stats
[i
].tex
&&
2207 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2208 vi_dcc_clean_up_context_slot(rctx
, i
);
2210 /* Find the texture. */
2211 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2212 /* Return if found. */
2213 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2214 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2218 /* Record the first seen empty slot. */
2219 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2223 /* Not found. Remove the oldest member to make space in the array. */
2224 if (empty_slot
== -1) {
2225 int oldest_slot
= 0;
2227 /* Find the oldest slot. */
2228 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2229 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2230 rctx
->dcc_stats
[i
].last_use_timestamp
)
2233 /* Clean up the oldest slot. */
2234 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2235 empty_slot
= oldest_slot
;
2238 /* Add the texture to the new slot. */
2239 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2240 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2244 static struct pipe_query
*
2245 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2247 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2248 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2250 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2251 return (struct pipe_query
*)query
;
2255 * Called when binding a color buffer.
2257 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2258 struct r600_texture
*tex
)
2260 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2261 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2263 assert(!rctx
->dcc_stats
[i
].query_active
);
2265 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2266 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2268 /* begin or resume the query */
2269 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2270 rctx
->dcc_stats
[i
].query_active
= true;
2274 * Called when unbinding a color buffer.
2276 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2277 struct r600_texture
*tex
)
2279 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2280 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2282 assert(rctx
->dcc_stats
[i
].query_active
);
2283 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2285 /* pause or end the query */
2286 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2287 rctx
->dcc_stats
[i
].query_active
= false;
2290 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2292 /* The minimum number of fullscreen draws per frame that is required
2294 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2297 /* Called by fast clear. */
2298 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2299 struct r600_texture
*tex
)
2301 /* The intent is to use this with shared displayable back buffers,
2302 * but it's not strictly limited only to them.
2304 if (!tex
->resource
.b
.is_shared
||
2305 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2306 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2307 tex
->resource
.b
.b
.last_level
> 0 ||
2308 !tex
->surface
.dcc_size
)
2311 if (tex
->dcc_offset
)
2312 return; /* already enabled */
2314 /* Enable the DCC stat gathering. */
2315 if (!tex
->dcc_gather_statistics
) {
2316 tex
->dcc_gather_statistics
= true;
2317 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2320 if (!vi_should_enable_separate_dcc(tex
))
2321 return; /* stats show that DCC decompression is too expensive */
2323 assert(tex
->surface
.num_dcc_levels
);
2324 assert(!tex
->dcc_separate_buffer
);
2326 r600_texture_discard_cmask(rctx
->screen
, tex
);
2328 /* Get a DCC buffer. */
2329 if (tex
->last_dcc_separate_buffer
) {
2330 assert(tex
->dcc_gather_statistics
);
2331 assert(!tex
->dcc_separate_buffer
);
2332 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2333 tex
->last_dcc_separate_buffer
= NULL
;
2335 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2336 r600_aligned_buffer_create(rctx
->b
.screen
,
2337 R600_RESOURCE_FLAG_UNMAPPABLE
,
2339 tex
->surface
.dcc_size
,
2340 tex
->surface
.dcc_alignment
);
2341 if (!tex
->dcc_separate_buffer
)
2345 /* dcc_offset is the absolute GPUVM address. */
2346 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2348 /* no need to flag anything since this is called by fast clear that
2349 * flags framebuffer state
2354 * Called by pipe_context::flush_resource, the place where DCC decompression
2357 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2358 struct r600_texture
*tex
)
2360 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2361 struct pipe_query
*tmp
;
2362 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2363 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2364 bool disable
= false;
2366 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2367 union pipe_query_result result
;
2369 /* Read the results. */
2370 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2372 r600_query_hw_reset_buffers(rctx
,
2373 (struct r600_query_hw
*)
2374 rctx
->dcc_stats
[i
].ps_stats
[2]);
2376 /* Compute the approximate number of fullscreen draws. */
2377 tex
->ps_draw_ratio
=
2378 result
.pipeline_statistics
.ps_invocations
/
2379 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2380 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2382 disable
= tex
->dcc_separate_buffer
&&
2383 !vi_should_enable_separate_dcc(tex
);
2386 tex
->num_slow_clears
= 0;
2388 /* stop the statistics query for ps_stats[0] */
2390 vi_separate_dcc_stop_query(ctx
, tex
);
2392 /* Move the queries in the queue by one. */
2393 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2394 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2395 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2396 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2398 /* create and start a new query as ps_stats[0] */
2400 vi_separate_dcc_start_query(ctx
, tex
);
2403 assert(!tex
->last_dcc_separate_buffer
);
2404 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2405 tex
->dcc_separate_buffer
= NULL
;
2406 tex
->dcc_offset
= 0;
2407 /* no need to flag anything since this is called after
2408 * decompression that re-sets framebuffer state
2413 /* FAST COLOR CLEAR */
2415 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2416 enum pipe_format surface_format
,
2417 const union pipe_color_union
*color
)
2419 union util_color uc
;
2421 memset(&uc
, 0, sizeof(uc
));
2423 if (rtex
->surface
.bpe
== 16) {
2424 /* DCC fast clear only:
2425 * CLEAR_WORD0 = R = G = B
2428 assert(color
->ui
[0] == color
->ui
[1] &&
2429 color
->ui
[0] == color
->ui
[2]);
2430 uc
.ui
[0] = color
->ui
[0];
2431 uc
.ui
[1] = color
->ui
[3];
2432 } else if (util_format_is_pure_uint(surface_format
)) {
2433 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2434 } else if (util_format_is_pure_sint(surface_format
)) {
2435 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2437 util_pack_color(color
->f
, surface_format
, &uc
);
2440 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2443 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2444 const union pipe_color_union
*color
,
2445 uint32_t* reset_value
,
2446 bool* clear_words_needed
)
2448 bool values
[4] = {};
2450 bool main_value
= false;
2451 bool extra_value
= false;
2454 /* This is needed to get the correct DCC clear value for luminance formats.
2455 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2456 * 2) Convert luminance to red. (the real hw format for luminance)
2458 surface_format
= util_format_linear(surface_format
);
2459 surface_format
= util_format_luminance_to_red(surface_format
);
2461 const struct util_format_description
*desc
= util_format_description(surface_format
);
2463 if (desc
->block
.bits
== 128 &&
2464 (color
->ui
[0] != color
->ui
[1] ||
2465 color
->ui
[0] != color
->ui
[2]))
2468 *clear_words_needed
= true;
2469 *reset_value
= 0x20202020U
;
2471 /* If we want to clear without needing a fast clear eliminate step, we
2472 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2473 * have two sets of flags, one for the last or first channel(extra) and
2474 * one for the other channels(main).
2477 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2478 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2479 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2480 util_format_is_alpha(surface_format
)) {
2482 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2483 if(r600_translate_colorswap(surface_format
, false) <= 1)
2484 extra_channel
= desc
->nr_channels
- 1;
2490 for (i
= 0; i
< 4; ++i
) {
2491 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2493 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2494 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2497 if (desc
->channel
[i
].pure_integer
&&
2498 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2499 /* Use the maximum value for clamping the clear color. */
2500 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2502 values
[i
] = color
->i
[i
] != 0;
2503 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2505 } else if (desc
->channel
[i
].pure_integer
&&
2506 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2507 /* Use the maximum value for clamping the clear color. */
2508 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2510 values
[i
] = color
->ui
[i
] != 0U;
2511 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2514 values
[i
] = color
->f
[i
] != 0.0F
;
2515 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2519 if (index
== extra_channel
)
2520 extra_value
= values
[i
];
2522 main_value
= values
[i
];
2525 for (int i
= 0; i
< 4; ++i
)
2526 if (values
[i
] != main_value
&&
2527 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2528 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2529 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2532 *clear_words_needed
= false;
2534 *reset_value
|= 0x80808080U
;
2537 *reset_value
|= 0x40404040U
;
2541 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2542 struct r600_texture
*rtex
,
2543 unsigned level
, unsigned clear_value
)
2545 struct pipe_resource
*dcc_buffer
;
2546 uint64_t dcc_offset
, clear_size
;
2548 assert(vi_dcc_enabled(rtex
, level
));
2550 if (rtex
->dcc_separate_buffer
) {
2551 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2554 dcc_buffer
= &rtex
->resource
.b
.b
;
2555 dcc_offset
= rtex
->dcc_offset
;
2558 if (rctx
->chip_class
>= GFX9
) {
2559 /* Mipmap level clears aren't implemented. */
2560 assert(rtex
->resource
.b
.b
.last_level
== 0);
2561 /* MSAA needs a different clear size. */
2562 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2563 clear_size
= rtex
->surface
.dcc_size
;
2565 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2566 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2569 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2570 clear_value
, R600_COHERENCY_CB_META
);
2573 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2574 * This allows hitting the MSAA resolve fast path, which requires that both
2575 * src and dst micro tile modes match.
2577 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2578 struct r600_texture
*rtex
)
2580 if (rtex
->resource
.b
.is_shared
||
2581 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2582 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2585 assert(rscreen
->chip_class
>= GFX9
||
2586 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2587 assert(rtex
->resource
.b
.b
.last_level
== 0);
2589 if (rscreen
->chip_class
>= GFX9
) {
2590 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2591 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2593 /* If you do swizzle_mode % 4, you'll get:
2599 * Depth-sample order isn't allowed:
2601 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2603 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2604 case RADEON_MICRO_MODE_DISPLAY
:
2605 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2606 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2608 case RADEON_MICRO_MODE_THIN
:
2609 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2610 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2612 case RADEON_MICRO_MODE_ROTATED
:
2613 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2614 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2616 default: /* depth */
2617 assert(!"unexpected micro mode");
2620 } else if (rscreen
->chip_class
>= CIK
) {
2621 /* These magic numbers were copied from addrlib. It doesn't use
2622 * any definitions for them either. They are all 2D_TILED_THIN1
2623 * modes with different bpp and micro tile mode.
2625 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2626 case RADEON_MICRO_MODE_DISPLAY
:
2627 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2629 case RADEON_MICRO_MODE_THIN
:
2630 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2632 case RADEON_MICRO_MODE_ROTATED
:
2633 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2635 default: /* depth, thick */
2636 assert(!"unexpected micro mode");
2640 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2641 case RADEON_MICRO_MODE_DISPLAY
:
2642 switch (rtex
->surface
.bpe
) {
2644 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2647 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2650 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2654 case RADEON_MICRO_MODE_THIN
:
2655 switch (rtex
->surface
.bpe
) {
2657 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2660 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2663 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2665 default: /* 8, 16 */
2666 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2670 default: /* depth, thick */
2671 assert(!"unexpected micro mode");
2676 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2678 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2681 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2682 struct pipe_framebuffer_state
*fb
,
2683 struct r600_atom
*fb_state
,
2684 unsigned *buffers
, ubyte
*dirty_cbufs
,
2685 const union pipe_color_union
*color
)
2689 /* This function is broken in BE, so just disable this path for now */
2690 #ifdef PIPE_ARCH_BIG_ENDIAN
2694 if (rctx
->render_cond
)
2697 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2698 struct r600_texture
*tex
;
2699 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2704 /* if this colorbuffer is not being cleared */
2705 if (!(*buffers
& clear_bit
))
2708 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2710 /* the clear is allowed if all layers are bound */
2711 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2712 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2716 /* cannot clear mipmapped textures */
2717 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2721 /* only supported on tiled surfaces */
2722 if (tex
->surface
.is_linear
) {
2726 /* shared textures can't use fast clear without an explicit flush,
2727 * because there is no way to communicate the clear color among
2730 if (tex
->resource
.b
.is_shared
&&
2731 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2734 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2735 if (rctx
->chip_class
== CIK
&&
2736 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2737 rctx
->screen
->info
.drm_major
== 2 &&
2738 rctx
->screen
->info
.drm_minor
< 38) {
2742 /* Fast clear is the most appropriate place to enable DCC for
2743 * displayable surfaces.
2745 if (rctx
->chip_class
>= VI
&&
2746 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2747 vi_separate_dcc_try_enable(rctx
, tex
);
2749 /* RB+ isn't supported with a CMASK clear only on Stoney,
2750 * so all clears are considered to be hypothetically slow
2751 * clears, which is weighed when determining whether to
2752 * enable separate DCC.
2754 if (tex
->dcc_gather_statistics
&&
2755 rctx
->family
== CHIP_STONEY
)
2756 tex
->num_slow_clears
++;
2759 /* Try to clear DCC first, otherwise try CMASK. */
2760 if (vi_dcc_enabled(tex
, 0)) {
2761 uint32_t reset_value
;
2762 bool clear_words_needed
;
2764 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2767 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2768 color
, &reset_value
,
2769 &clear_words_needed
))
2772 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2774 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2775 if (clear_words_needed
) {
2776 bool need_compressed_update
= !tex
->dirty_level_mask
;
2778 tex
->dirty_level_mask
|= level_bit
;
2780 if (need_compressed_update
)
2781 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2783 tex
->separate_dcc_dirty
= true;
2785 /* 128-bit formats are unusupported */
2786 if (tex
->surface
.bpe
> 8) {
2790 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2791 if (rctx
->family
== CHIP_STONEY
)
2794 /* ensure CMASK is enabled */
2795 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2796 if (tex
->cmask
.size
== 0) {
2800 /* Do the fast clear. */
2801 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2802 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2803 R600_COHERENCY_CB_META
);
2805 bool need_compressed_update
= !tex
->dirty_level_mask
;
2807 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2809 if (need_compressed_update
)
2810 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2813 /* We can change the micro tile mode before a full clear. */
2814 if (rctx
->screen
->chip_class
>= SI
)
2815 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2817 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2820 *dirty_cbufs
|= 1 << i
;
2821 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2822 *buffers
&= ~clear_bit
;
2826 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2828 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2829 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2832 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2834 rctx
->b
.create_surface
= r600_create_surface
;
2835 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2836 rctx
->b
.clear_texture
= r600_clear_texture
;