src/gallium/drivers/radeon/radeon_uvd.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2011 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef RADEON_UVD_H
  29 #define RADEON_UVD_H
  30
  31 #include "radeon/radeon_winsys.h"
  32 #include "vl/vl_video_buffer.h"
  33
  34 /* UVD uses PM4 packet type 0 and 2 */
  35 #define RUVD_PKT_TYPE_S(x)              (((unsigned)(x) & 0x3) << 30)
  36 #define RUVD_PKT_TYPE_G(x)              (((x) >> 30) & 0x3)
  37 #define RUVD_PKT_TYPE_C                 0x3FFFFFFF
  38 #define RUVD_PKT_COUNT_S(x)             (((unsigned)(x) & 0x3FFF) << 16)
  39 #define RUVD_PKT_COUNT_G(x)             (((x) >> 16) & 0x3FFF)
  40 #define RUVD_PKT_COUNT_C                0xC000FFFF
  41 #define RUVD_PKT0_BASE_INDEX_S(x)       (((unsigned)(x) & 0xFFFF) << 0)
  42 #define RUVD_PKT0_BASE_INDEX_G(x)       (((x) >> 0) & 0xFFFF)
  43 #define RUVD_PKT0_BASE_INDEX_C          0xFFFF0000
  44 #define RUVD_PKT0(index, count)         (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
  45 #define RUVD_PKT2()                     (RUVD_PKT_TYPE_S(2))
  46
  47 /* registers involved with UVD */
  48 #define RUVD_GPCOM_VCPU_CMD             0xEF0C
  49 #define RUVD_GPCOM_VCPU_DATA0           0xEF10
  50 #define RUVD_GPCOM_VCPU_DATA1           0xEF14
  51 #define RUVD_ENGINE_CNTL                0xEF18
  52
  53 #define RUVD_GPCOM_VCPU_CMD_SOC15               0x2070c
  54 #define RUVD_GPCOM_VCPU_DATA0_SOC15             0x20710
  55 #define RUVD_GPCOM_VCPU_DATA1_SOC15             0x20714
  56 #define RUVD_ENGINE_CNTL_SOC15                  0x20718
  57
  58 /* UVD commands to VCPU */
  59 #define RUVD_CMD_MSG_BUFFER             0x00000000
  60 #define RUVD_CMD_DPB_BUFFER             0x00000001
  61 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
  62 #define RUVD_CMD_FEEDBACK_BUFFER        0x00000003
  63 #define RUVD_CMD_SESSION_CONTEXT_BUFFER 0x00000005
  64 #define RUVD_CMD_BITSTREAM_BUFFER       0x00000100
  65 #define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204
  66 #define RUVD_CMD_CONTEXT_BUFFER         0x00000206
  67
  68 /* UVD message types */
  69 #define RUVD_MSG_CREATE         0
  70 #define RUVD_MSG_DECODE         1
  71 #define RUVD_MSG_DESTROY        2
  72
  73 /* UVD stream types */
  74 #define RUVD_CODEC_H264         0x00000000
  75 #define RUVD_CODEC_VC1          0x00000001
  76 #define RUVD_CODEC_MPEG2        0x00000003
  77 #define RUVD_CODEC_MPEG4        0x00000004
  78 #define RUVD_CODEC_H264_PERF    0x00000007
  79 #define RUVD_CODEC_MJPEG        0x00000008
  80 #define RUVD_CODEC_H265         0x00000010
  81
  82 /* UVD decode target buffer tiling mode */
  83 #define RUVD_TILE_LINEAR        0x00000000
  84 #define RUVD_TILE_8X4           0x00000001
  85 #define RUVD_TILE_8X8           0x00000002
  86 #define RUVD_TILE_32AS8         0x00000003
  87
  88 /* UVD decode target buffer array mode */
  89 #define RUVD_ARRAY_MODE_LINEAR                          0x00000000
  90 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED        0x00000001
  91 #define RUVD_ARRAY_MODE_1D_THIN                         0x00000002
  92 #define RUVD_ARRAY_MODE_2D_THIN                         0x00000004
  93 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR        0x00000004
  94 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED         0x00000005
  95
  96 /* UVD tile config */
  97 #define RUVD_BANK_WIDTH(x)              ((x) << 0)
  98 #define RUVD_BANK_HEIGHT(x)             ((x) << 3)
  99 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
 100 #define RUVD_NUM_BANKS(x)               ((x) << 9)
 101
 102 /* H.264 profile definitions */
 103 #define RUVD_H264_PROFILE_BASELINE      0x00000000
 104 #define RUVD_H264_PROFILE_MAIN          0x00000001
 105 #define RUVD_H264_PROFILE_HIGH          0x00000002
 106 #define RUVD_H264_PROFILE_STEREO_HIGH   0x00000003
 107 #define RUVD_H264_PROFILE_MVC           0x00000004
 108
 109 /* VC-1 profile definitions */
 110 #define RUVD_VC1_PROFILE_SIMPLE         0x00000000
 111 #define RUVD_VC1_PROFILE_MAIN           0x00000001
 112 #define RUVD_VC1_PROFILE_ADVANCED       0x00000002
 113
 114 enum ruvd_surface_type {
 115         RUVD_SURFACE_TYPE_LEGACY = 0,
 116         RUVD_SURFACE_TYPE_GFX9
 117 };
 118
 119 struct ruvd_mvc_element {
 120         uint16_t        viewOrderIndex;
 121         uint16_t        viewId;
 122         uint16_t        numOfAnchorRefsInL0;
 123         uint16_t        viewIdOfAnchorRefsInL0[15];
 124         uint16_t        numOfAnchorRefsInL1;
 125         uint16_t        viewIdOfAnchorRefsInL1[15];
 126         uint16_t        numOfNonAnchorRefsInL0;
 127         uint16_t        viewIdOfNonAnchorRefsInL0[15];
 128         uint16_t        numOfNonAnchorRefsInL1;
 129         uint16_t        viewIdOfNonAnchorRefsInL1[15];
 130 };
 131
 132 struct ruvd_h264 {
 133         uint32_t        profile;
 134         uint32_t        level;
 135
 136         uint32_t        sps_info_flags;
 137         uint32_t        pps_info_flags;
 138         uint8_t         chroma_format;
 139         uint8_t         bit_depth_luma_minus8;
 140         uint8_t         bit_depth_chroma_minus8;
 141         uint8_t         log2_max_frame_num_minus4;
 142
 143         uint8_t         pic_order_cnt_type;
 144         uint8_t         log2_max_pic_order_cnt_lsb_minus4;
 145         uint8_t         num_ref_frames;
 146         uint8_t         reserved_8bit;
 147
 148         int8_t          pic_init_qp_minus26;
 149         int8_t          pic_init_qs_minus26;
 150         int8_t          chroma_qp_index_offset;
 151         int8_t          second_chroma_qp_index_offset;
 152
 153         uint8_t         num_slice_groups_minus1;
 154         uint8_t         slice_group_map_type;
 155         uint8_t         num_ref_idx_l0_active_minus1;
 156         uint8_t         num_ref_idx_l1_active_minus1;
 157
 158         uint16_t        slice_group_change_rate_minus1;
 159         uint16_t        reserved_16bit_1;
 160
 161         uint8_t         scaling_list_4x4[6][16];
 162         uint8_t         scaling_list_8x8[2][64];
 163
 164         uint32_t        frame_num;
 165         uint32_t        frame_num_list[16];
 166         int32_t         curr_field_order_cnt_list[2];
 167         int32_t         field_order_cnt_list[16][2];
 168
 169         uint32_t        decoded_pic_idx;
 170
 171         uint32_t        curr_pic_ref_frame_num;
 172
 173         uint8_t         ref_frame_list[16];
 174
 175         uint32_t        reserved[122];
 176
 177         struct {
 178                 uint32_t                        numViews;
 179                 uint32_t                        viewId0;
 180                 struct ruvd_mvc_element mvcElements[1];
 181         } mvc;
 182 };
 183
 184 struct ruvd_h265 {
 185         uint32_t        sps_info_flags;
 186         uint32_t        pps_info_flags;
 187
 188         uint8_t         chroma_format;
 189         uint8_t         bit_depth_luma_minus8;
 190         uint8_t         bit_depth_chroma_minus8;
 191         uint8_t         log2_max_pic_order_cnt_lsb_minus4;
 192
 193         uint8_t         sps_max_dec_pic_buffering_minus1;
 194         uint8_t         log2_min_luma_coding_block_size_minus3;
 195         uint8_t         log2_diff_max_min_luma_coding_block_size;
 196         uint8_t         log2_min_transform_block_size_minus2;
 197
 198         uint8_t         log2_diff_max_min_transform_block_size;
 199         uint8_t         max_transform_hierarchy_depth_inter;
 200         uint8_t         max_transform_hierarchy_depth_intra;
 201         uint8_t         pcm_sample_bit_depth_luma_minus1;
 202
 203         uint8_t         pcm_sample_bit_depth_chroma_minus1;
 204         uint8_t         log2_min_pcm_luma_coding_block_size_minus3;
 205         uint8_t         log2_diff_max_min_pcm_luma_coding_block_size;
 206         uint8_t         num_extra_slice_header_bits;
 207
 208         uint8_t         num_short_term_ref_pic_sets;
 209         uint8_t         num_long_term_ref_pic_sps;
 210         uint8_t         num_ref_idx_l0_default_active_minus1;
 211         uint8_t         num_ref_idx_l1_default_active_minus1;
 212
 213         int8_t          pps_cb_qp_offset;
 214         int8_t          pps_cr_qp_offset;
 215         int8_t          pps_beta_offset_div2;
 216         int8_t          pps_tc_offset_div2;
 217
 218         uint8_t         diff_cu_qp_delta_depth;
 219         uint8_t         num_tile_columns_minus1;
 220         uint8_t         num_tile_rows_minus1;
 221         uint8_t         log2_parallel_merge_level_minus2;
 222
 223         uint16_t        column_width_minus1[19];
 224         uint16_t        row_height_minus1[21];
 225
 226         int8_t          init_qp_minus26;
 227         uint8_t         num_delta_pocs_ref_rps_idx;
 228         uint8_t         curr_idx;
 229         uint8_t         reserved1;
 230         int32_t         curr_poc;
 231         uint8_t         ref_pic_list[16];
 232         int32_t         poc_list[16];
 233         uint8_t         ref_pic_set_st_curr_before[8];
 234         uint8_t         ref_pic_set_st_curr_after[8];
 235         uint8_t         ref_pic_set_lt_curr[8];
 236
 237         uint8_t         ucScalingListDCCoefSizeID2[6];
 238         uint8_t         ucScalingListDCCoefSizeID3[2];
 239
 240         uint8_t         highestTid;
 241         uint8_t         isNonRef;
 242
 243         uint8_t         p010_mode;
 244         uint8_t         msb_mode;
 245         uint8_t         luma_10to8;
 246         uint8_t         chroma_10to8;
 247         uint8_t         sclr_luma10to8;
 248         uint8_t         sclr_chroma10to8;
 249
 250         uint8_t         direct_reflist[2][15];
 251 };
 252
 253 struct ruvd_vc1 {
 254         uint32_t        profile;
 255         uint32_t        level;
 256         uint32_t        sps_info_flags;
 257         uint32_t        pps_info_flags;
 258         uint32_t        pic_structure;
 259         uint32_t        chroma_format;
 260 };
 261
 262 struct ruvd_mpeg2 {
 263         uint32_t        decoded_pic_idx;
 264         uint32_t        ref_pic_idx[2];
 265
 266         uint8_t         load_intra_quantiser_matrix;
 267         uint8_t         load_nonintra_quantiser_matrix;
 268         uint8_t         reserved_quantiser_alignement[2];
 269         uint8_t         intra_quantiser_matrix[64];
 270         uint8_t         nonintra_quantiser_matrix[64];
 271
 272         uint8_t         profile_and_level_indication;
 273         uint8_t         chroma_format;
 274
 275         uint8_t         picture_coding_type;
 276
 277         uint8_t         reserved_1;
 278
 279         uint8_t         f_code[2][2];
 280         uint8_t         intra_dc_precision;
 281         uint8_t         pic_structure;
 282         uint8_t         top_field_first;
 283         uint8_t         frame_pred_frame_dct;
 284         uint8_t         concealment_motion_vectors;
 285         uint8_t         q_scale_type;
 286         uint8_t         intra_vlc_format;
 287         uint8_t         alternate_scan;
 288 };
 289
 290 struct ruvd_mpeg4
 291 {
 292         uint32_t        decoded_pic_idx;
 293         uint32_t        ref_pic_idx[2];
 294
 295         uint32_t        variant_type;
 296         uint8_t         profile_and_level_indication;
 297
 298         uint8_t         video_object_layer_verid;
 299         uint8_t         video_object_layer_shape;
 300
 301         uint8_t         reserved_1;
 302
 303         uint16_t        video_object_layer_width;
 304         uint16_t        video_object_layer_height;
 305
 306         uint16_t        vop_time_increment_resolution;
 307
 308         uint16_t        reserved_2;
 309
 310         uint32_t        flags;
 311
 312         uint8_t         quant_type;
 313
 314         uint8_t         reserved_3[3];
 315
 316         uint8_t         intra_quant_mat[64];
 317         uint8_t         nonintra_quant_mat[64];
 318
 319         struct {
 320                 uint8_t         sprite_enable;
 321
 322                 uint8_t         reserved_4[3];
 323
 324                 uint16_t        sprite_width;
 325                 uint16_t        sprite_height;
 326                 int16_t         sprite_left_coordinate;
 327                 int16_t         sprite_top_coordinate;
 328
 329                 uint8_t         no_of_sprite_warping_points;
 330                 uint8_t         sprite_warping_accuracy;
 331                 uint8_t         sprite_brightness_change;
 332                 uint8_t         low_latency_sprite_enable;
 333         } sprite_config;
 334
 335         struct {
 336                 uint32_t        flags;
 337                 uint8_t         vol_mode;
 338                 uint8_t         reserved_5[3];
 339         } divx_311_config;
 340 };
 341
 342 /* message between driver and hardware */
 343 struct ruvd_msg {
 344
 345         uint32_t        size;
 346         uint32_t        msg_type;
 347         uint32_t        stream_handle;
 348         uint32_t        status_report_feedback_number;
 349
 350         union {
 351                 struct {
 352                         uint32_t        stream_type;
 353                         uint32_t        session_flags;
 354                         uint32_t        asic_id;
 355                         uint32_t        width_in_samples;
 356                         uint32_t        height_in_samples;
 357                         uint32_t        dpb_buffer;
 358                         uint32_t        dpb_size;
 359                         uint32_t        dpb_model;
 360                         uint32_t        version_info;
 361                 } create;
 362
 363                 struct {
 364                         uint32_t        stream_type;
 365                         uint32_t        decode_flags;
 366                         uint32_t        width_in_samples;
 367                         uint32_t        height_in_samples;
 368
 369                         uint32_t        dpb_buffer;
 370                         uint32_t        dpb_size;
 371                         uint32_t        dpb_model;
 372                         uint32_t        dpb_reserved;
 373
 374                         uint32_t        db_offset_alignment;
 375                         uint32_t        db_pitch;
 376                         uint32_t        db_tiling_mode;
 377                         uint32_t        db_array_mode;
 378                         uint32_t        db_field_mode;
 379                         uint32_t        db_surf_tile_config;
 380                         uint32_t        db_aligned_height;
 381                         uint32_t        db_reserved;
 382
 383                         uint32_t        use_addr_macro;
 384
 385                         uint32_t        bsd_buffer;
 386                         uint32_t        bsd_size;
 387
 388                         uint32_t        pic_param_buffer;
 389                         uint32_t        pic_param_size;
 390                         uint32_t        mb_cntl_buffer;
 391                         uint32_t        mb_cntl_size;
 392
 393                         uint32_t        dt_buffer;
 394                         uint32_t        dt_pitch;
 395                         uint32_t        dt_tiling_mode;
 396                         uint32_t        dt_array_mode;
 397                         uint32_t        dt_field_mode;
 398                         uint32_t        dt_luma_top_offset;
 399                         uint32_t        dt_luma_bottom_offset;
 400                         uint32_t        dt_chroma_top_offset;
 401                         uint32_t        dt_chroma_bottom_offset;
 402                         uint32_t        dt_surf_tile_config;
 403                         uint32_t        dt_uv_surf_tile_config;
 404                         // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
 405                         uint32_t        dt_wa_chroma_top_offset;
 406                         uint32_t        dt_wa_chroma_bottom_offset;
 407
 408                         uint32_t        reserved[16];
 409
 410                         union {
 411                                 struct ruvd_h264        h264;
 412                                 struct ruvd_h265        h265;
 413                                 struct ruvd_vc1         vc1;
 414                                 struct ruvd_mpeg2       mpeg2;
 415                                 struct ruvd_mpeg4       mpeg4;
 416
 417                                 uint32_t info[768];
 418                         } codec;
 419
 420                         uint8_t         extension_support;
 421                         uint8_t         reserved_8bit_1;
 422                         uint8_t         reserved_8bit_2;
 423                         uint8_t         reserved_8bit_3;
 424                         uint32_t        extension_reserved[64];
 425                 } decode;
 426         } body;
 427 };
 428
 429 /* driver dependent callback */
 430 typedef struct pb_buffer* (*ruvd_set_dtb)
 431 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
 432
 433 /* create an UVD decode */
 434 struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
 435                                                       const struct pipe_video_codec *templat,
 436                                                       ruvd_set_dtb set_dtb);
 437
 438 /* fill decoding target field from the luma and chroma surfaces */
 439 void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
 440                             struct radeon_surf *chroma, enum ruvd_surface_type type);
 441 #endif