src/gallium/drivers/radeon/radeon_uvd_enc.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "radeon_uvd_enc.h"
  29
  30 #include "pipe/p_video_codec.h"
  31 #include "radeon_video.h"
  32 #include "radeonsi/si_pipe.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_video.h"
  35 #include "vl/vl_video_buffer.h"
  36
  37 #include <stdio.h>
  38
  39 #define UVD_HEVC_LEVEL_1   30
  40 #define UVD_HEVC_LEVEL_2   60
  41 #define UVD_HEVC_LEVEL_2_1 63
  42 #define UVD_HEVC_LEVEL_3   90
  43 #define UVD_HEVC_LEVEL_3_1 93
  44 #define UVD_HEVC_LEVEL_4   120
  45 #define UVD_HEVC_LEVEL_4_1 123
  46 #define UVD_HEVC_LEVEL_5   150
  47 #define UVD_HEVC_LEVEL_5_1 153
  48 #define UVD_HEVC_LEVEL_5_2 156
  49 #define UVD_HEVC_LEVEL_6   180
  50 #define UVD_HEVC_LEVEL_6_1 183
  51 #define UVD_HEVC_LEVEL_6_2 186
  52
  53 static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
  54                                      struct pipe_h265_enc_picture_desc *pic)
  55 {
  56    enc->enc_pic.picture_type = pic->picture_type;
  57    enc->enc_pic.frame_num = pic->frame_num;
  58    enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
  59    enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
  60    enc->enc_pic.not_referenced = pic->not_referenced;
  61    enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
  62                             (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
  63    enc->enc_pic.crop_left = 0;
  64    enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
  65    enc->enc_pic.crop_top = 0;
  66    enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
  67    enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
  68    enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
  69    enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
  70    enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
  71    enc->enc_pic.log2_max_poc = 0;
  72    for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  73       i = (i >> 1);
  74    enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
  75    enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
  76    enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
  77    enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
  78       pic->seq.log2_diff_max_min_luma_coding_block_size;
  79    enc->enc_pic.log2_min_transform_block_size_minus2 =
  80       pic->seq.log2_min_transform_block_size_minus2;
  81    enc->enc_pic.log2_diff_max_min_transform_block_size =
  82       pic->seq.log2_diff_max_min_transform_block_size;
  83    enc->enc_pic.max_transform_hierarchy_depth_inter = pic->seq.max_transform_hierarchy_depth_inter;
  84    enc->enc_pic.max_transform_hierarchy_depth_intra = pic->seq.max_transform_hierarchy_depth_intra;
  85    enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
  86    enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
  87    enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
  88    enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
  89    enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
  90    enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
  91    enc->enc_pic.pcm_enabled_flag = 0; /*HW not support PCM */
  92    enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
  93 }
  94
  95 static void flush(struct radeon_uvd_encoder *enc)
  96 {
  97    enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
  98 }
  99
 100 static void radeon_uvd_enc_flush(struct pipe_video_codec *encoder)
 101 {
 102    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 103    flush(enc);
 104 }
 105
 106 static void radeon_uvd_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
 107 {
 108    // just ignored
 109 }
 110
 111 static unsigned get_cpb_num(struct radeon_uvd_encoder *enc)
 112 {
 113    unsigned w = align(enc->base.width, 16) / 16;
 114    unsigned h = align(enc->base.height, 16) / 16;
 115    unsigned dpb;
 116
 117    switch (enc->base.level) {
 118    case UVD_HEVC_LEVEL_1:
 119       dpb = 36864;
 120       break;
 121
 122    case UVD_HEVC_LEVEL_2:
 123       dpb = 122880;
 124       break;
 125
 126    case UVD_HEVC_LEVEL_2_1:
 127       dpb = 245760;
 128       break;
 129
 130    case UVD_HEVC_LEVEL_3:
 131       dpb = 552960;
 132       break;
 133
 134    case UVD_HEVC_LEVEL_3_1:
 135       dpb = 983040;
 136       break;
 137
 138    case UVD_HEVC_LEVEL_4:
 139    case UVD_HEVC_LEVEL_4_1:
 140       dpb = 2228224;
 141       break;
 142
 143    case UVD_HEVC_LEVEL_5:
 144    case UVD_HEVC_LEVEL_5_1:
 145    case UVD_HEVC_LEVEL_5_2:
 146       dpb = 8912896;
 147       break;
 148
 149    case UVD_HEVC_LEVEL_6:
 150    case UVD_HEVC_LEVEL_6_1:
 151    case UVD_HEVC_LEVEL_6_2:
 152    default:
 153       dpb = 35651584;
 154       break;
 155    }
 156
 157    return MIN2(dpb / (w * h), 16);
 158 }
 159
 160 static void radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
 161                                        struct pipe_video_buffer *source,
 162                                        struct pipe_picture_desc *picture)
 163 {
 164    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 165    struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
 166
 167    radeon_uvd_enc_get_param(enc, (struct pipe_h265_enc_picture_desc *)picture);
 168
 169    enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
 170    enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
 171
 172    enc->need_feedback = false;
 173
 174    if (!enc->stream_handle) {
 175       struct rvid_buffer fb;
 176       enc->stream_handle = si_vid_alloc_stream_handle();
 177       enc->si = CALLOC_STRUCT(rvid_buffer);
 178       si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
 179       si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
 180       enc->fb = &fb;
 181       enc->begin(enc, picture);
 182       flush(enc);
 183       si_vid_destroy_buffer(&fb);
 184    }
 185 }
 186
 187 static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
 188                                             struct pipe_video_buffer *source,
 189                                             struct pipe_resource *destination, void **fb)
 190 {
 191    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 192    enc->get_buffer(destination, &enc->bs_handle, NULL);
 193    enc->bs_size = destination->width0;
 194
 195    *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
 196
 197    if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
 198       RVID_ERR("Can't create feedback buffer.\n");
 199       return;
 200    }
 201
 202    enc->need_feedback = true;
 203    enc->encode(enc);
 204 }
 205
 206 static void radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder,
 207                                      struct pipe_video_buffer *source,
 208                                      struct pipe_picture_desc *picture)
 209 {
 210    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 211    flush(enc);
 212 }
 213
 214 static void radeon_uvd_enc_destroy(struct pipe_video_codec *encoder)
 215 {
 216    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 217
 218    if (enc->stream_handle) {
 219       struct rvid_buffer fb;
 220       enc->need_feedback = false;
 221       si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
 222       enc->fb = &fb;
 223       enc->destroy(enc);
 224       flush(enc);
 225       si_vid_destroy_buffer(&fb);
 226    }
 227
 228    si_vid_destroy_buffer(&enc->cpb);
 229    enc->ws->cs_destroy(enc->cs);
 230    FREE(enc);
 231 }
 232
 233 static void radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
 234                                         unsigned *size)
 235 {
 236    struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
 237    struct rvid_buffer *fb = feedback;
 238
 239    if (NULL != size) {
 240       radeon_uvd_enc_feedback_t *fb_data = (radeon_uvd_enc_feedback_t *)enc->ws->buffer_map(
 241          fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
 242
 243       if (!fb_data->status)
 244          *size = fb_data->bitstream_size;
 245       else
 246          *size = 0;
 247       enc->ws->buffer_unmap(fb->res->buf);
 248    }
 249
 250    si_vid_destroy_buffer(fb);
 251    FREE(fb);
 252 }
 253
 254 struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context,
 255                                                    const struct pipe_video_codec *templ,
 256                                                    struct radeon_winsys *ws,
 257                                                    radeon_uvd_enc_get_buffer get_buffer)
 258 {
 259    struct si_screen *sscreen = (struct si_screen *)context->screen;
 260    struct si_context *sctx = (struct si_context *)context;
 261    struct radeon_uvd_encoder *enc;
 262    struct pipe_video_buffer *tmp_buf, templat = {};
 263    struct radeon_surf *tmp_surf;
 264    unsigned cpb_size;
 265
 266    if (!si_radeon_uvd_enc_supported(sscreen)) {
 267       RVID_ERR("Unsupported UVD ENC fw version loaded!\n");
 268       return NULL;
 269    }
 270
 271    enc = CALLOC_STRUCT(radeon_uvd_encoder);
 272
 273    if (!enc)
 274       return NULL;
 275
 276    enc->base = *templ;
 277    enc->base.context = context;
 278    enc->base.destroy = radeon_uvd_enc_destroy;
 279    enc->base.begin_frame = radeon_uvd_enc_begin_frame;
 280    enc->base.encode_bitstream = radeon_uvd_enc_encode_bitstream;
 281    enc->base.end_frame = radeon_uvd_enc_end_frame;
 282    enc->base.flush = radeon_uvd_enc_flush;
 283    enc->base.get_feedback = radeon_uvd_enc_get_feedback;
 284    enc->get_buffer = get_buffer;
 285    enc->bits_in_shifter = 0;
 286    enc->screen = context->screen;
 287    enc->ws = ws;
 288    enc->cs = ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc, false);
 289
 290    if (!enc->cs) {
 291       RVID_ERR("Can't get command submission context.\n");
 292       goto error;
 293    }
 294
 295    struct rvid_buffer si;
 296    si_vid_create_buffer(enc->screen, &si, 128 * 1024, PIPE_USAGE_STAGING);
 297    enc->si = &si;
 298
 299    templat.buffer_format = PIPE_FORMAT_NV12;
 300    templat.width = enc->base.width;
 301    templat.height = enc->base.height;
 302    templat.interlaced = false;
 303
 304    if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
 305       RVID_ERR("Can't create video buffer.\n");
 306       goto error;
 307    }
 308
 309    enc->cpb_num = get_cpb_num(enc);
 310
 311    if (!enc->cpb_num)
 312       goto error;
 313
 314    get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
 315
 316    cpb_size = (sscreen->info.chip_class < GFX9)
 317                  ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
 318                       align(tmp_surf->u.legacy.level[0].nblk_y, 32)
 319                  : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
 320                       align(tmp_surf->u.gfx9.surf_height, 32);
 321
 322    cpb_size = cpb_size * 3 / 2;
 323    cpb_size = cpb_size * enc->cpb_num;
 324    tmp_buf->destroy(tmp_buf);
 325
 326    if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
 327       RVID_ERR("Can't create CPB buffer.\n");
 328       goto error;
 329    }
 330
 331    radeon_uvd_enc_1_1_init(enc);
 332
 333    return &enc->base;
 334
 335 error:
 336    if (enc->cs)
 337       enc->ws->cs_destroy(enc->cs);
 338
 339    si_vid_destroy_buffer(&enc->cpb);
 340
 341    FREE(enc);
 342    return NULL;
 343 }
 344
 345 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen)
 346 {
 347    return (sscreen->info.uvd_enc_supported);
 348 }