src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33 #include "util/u_memory.h"
  34
  35 #include "vl/vl_video_buffer.h"
  36 #include "radeonsi/si_pipe.h"
  37 #include "radeon_video.h"
  38 #include "radeon_uvd_enc.h"
  39
  40 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
  41 #define RADEON_ENC_BEGIN(cmd) { \
  42         uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
  43 RADEON_ENC_CS(cmd)
  44 #define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
  45 #define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
  46 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
  47 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
  48         enc->total_task_size += *begin;}
  49
  50 static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
  51
  52 static void
  53 radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
  54                           struct pb_buffer *buf, enum radeon_bo_usage usage,
  55                           enum radeon_bo_domain domain, signed offset)
  56 {
  57    enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
  58                           domain, 0);
  59    uint64_t addr;
  60    addr = enc->ws->buffer_get_virtual_address(buf);
  61    addr = addr + offset;
  62    RADEON_ENC_CS(addr >> 32);
  63    RADEON_ENC_CS(addr);
  64 }
  65
  66 static void
  67 radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
  68                                         bool set)
  69 {
  70    if (set != enc->emulation_prevention) {
  71       enc->emulation_prevention = set;
  72       enc->num_zeros = 0;
  73    }
  74 }
  75
  76 static void
  77 radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
  78                                unsigned char byte)
  79 {
  80    if (enc->byte_index == 0)
  81       enc->cs->current.buf[enc->cs->current.cdw] = 0;
  82    enc->cs->current.buf[enc->cs->current.cdw] |=
  83       ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
  84    enc->byte_index++;
  85
  86    if (enc->byte_index >= 4) {
  87       enc->byte_index = 0;
  88       enc->cs->current.cdw++;
  89    }
  90 }
  91
  92 static void
  93 radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
  94                                     unsigned char byte)
  95 {
  96    if (enc->emulation_prevention) {
  97       if ((enc->num_zeros >= 2)
  98           && ((byte == 0x00) || (byte == 0x01)
  99            || (byte == 0x02) || (byte == 0x03))) {
 100          radeon_uvd_enc_output_one_byte(enc, 0x03);
 101          enc->bits_output += 8;
 102          enc->num_zeros = 0;
 103       }
 104       enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
 105    }
 106 }
 107
 108 static void
 109 radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
 110                                unsigned int value, unsigned int num_bits)
 111 {
 112    unsigned int bits_to_pack = 0;
 113
 114    while (num_bits > 0) {
 115       unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
 116       bits_to_pack =
 117          num_bits >
 118          (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
 119
 120       if (bits_to_pack < num_bits)
 121          value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
 122
 123       enc->shifter |=
 124          value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
 125       num_bits -= bits_to_pack;
 126       enc->bits_in_shifter += bits_to_pack;
 127
 128       while (enc->bits_in_shifter >= 8) {
 129          unsigned char output_byte = (unsigned char) (enc->shifter >> 24);
 130          enc->shifter <<= 8;
 131          radeon_uvd_enc_emulation_prevention(enc, output_byte);
 132          radeon_uvd_enc_output_one_byte(enc, output_byte);
 133          enc->bits_in_shifter -= 8;
 134          enc->bits_output += 8;
 135       }
 136    }
 137 }
 138
 139 static void
 140 radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
 141 {
 142    enc->emulation_prevention = false;
 143    enc->shifter = 0;
 144    enc->bits_in_shifter = 0;
 145    enc->bits_output = 0;
 146    enc->num_zeros = 0;
 147    enc->byte_index = 0;
 148 }
 149
 150 static void
 151 radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
 152 {
 153    unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
 154
 155    if (num_padding_zeros > 0)
 156       radeon_uvd_enc_code_fixed_bits(enc, 0, num_padding_zeros);
 157 }
 158
 159 static void
 160 radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
 161 {
 162    if (enc->bits_in_shifter != 0) {
 163       unsigned char output_byte = (unsigned char) (enc->shifter >> 24);
 164       radeon_uvd_enc_emulation_prevention(enc, output_byte);
 165       radeon_uvd_enc_output_one_byte(enc, output_byte);
 166       enc->bits_output += enc->bits_in_shifter;
 167       enc->shifter = 0;
 168       enc->bits_in_shifter = 0;
 169       enc->num_zeros = 0;
 170    }
 171
 172    if (enc->byte_index > 0) {
 173       enc->cs->current.cdw++;
 174       enc->byte_index = 0;
 175    }
 176 }
 177
 178 static void
 179 radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
 180 {
 181    int x = -1;
 182    unsigned int ue_code = value + 1;
 183    value += 1;
 184
 185    while (value) {
 186       value = (value >> 1);
 187       x += 1;
 188    }
 189
 190    unsigned int ue_length = (x << 1) + 1;
 191    radeon_uvd_enc_code_fixed_bits(enc, ue_code, ue_length);
 192 }
 193
 194 static void
 195 radeon_uvd_enc_code_se(struct radeon_uvd_encoder *enc, int value)
 196 {
 197    unsigned int v = 0;
 198
 199    if (value != 0)
 200       v = (value < 0 ? ((unsigned int) (0 - value) << 1)
 201            : (((unsigned int) (value) << 1) - 1));
 202
 203    radeon_uvd_enc_code_ue(enc, v);
 204 }
 205
 206 static void
 207 radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
 208 {
 209    unsigned int interface_version =
 210       ((RENC_UVD_FW_INTERFACE_MAJOR_VERSION <<
 211         RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
 212        (RENC_UVD_FW_INTERFACE_MINOR_VERSION <<
 213         RENC_UVD_IF_MINOR_VERSION_SHIFT));
 214    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
 215    RADEON_ENC_CS(0x00000000);   // reserved
 216    RADEON_ENC_CS(interface_version);
 217    RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
 218    RADEON_ENC_END();
 219 }
 220
 221 static void
 222 radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
 223 {
 224    enc->enc_pic.task_info.task_id++;
 225
 226    if (need_feedback)
 227       enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
 228    else
 229       enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
 230
 231    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
 232    enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
 233    RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
 234    RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
 235    RADEON_ENC_END();
 236 }
 237
 238 static void
 239 radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
 240 {
 241    enc->enc_pic.session_init.aligned_picture_width =
 242       align(enc->base.width, 64);
 243    enc->enc_pic.session_init.aligned_picture_height =
 244       align(enc->base.height, 16);
 245    enc->enc_pic.session_init.padding_width =
 246       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 247    enc->enc_pic.session_init.padding_height =
 248       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 249    enc->enc_pic.session_init.pre_encode_mode = RENC_UVD_PREENCODE_MODE_NONE;
 250    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 251
 252    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
 253    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 254    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 255    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 256    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 257    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 258    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 259    RADEON_ENC_END();
 260 }
 261
 262 static void
 263 radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
 264 {
 265    enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 266    enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 267
 268    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
 269    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 270    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 271    RADEON_ENC_END();
 272 }
 273
 274 static void
 275 radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
 276 {
 277    enc->enc_pic.layer_sel.temporal_layer_index = 0;
 278
 279    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
 280    RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 281    RADEON_ENC_END();
 282 }
 283
 284 static void
 285 radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc)
 286 {
 287    enc->enc_pic.hevc_slice_ctrl.slice_control_mode =
 288       RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
 289    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
 290       align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 291    enc->enc_pic.hevc_slice_ctrl.
 292       fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
 293       enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 294
 295    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
 296    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 297    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.
 298                  fixed_ctbs_per_slice.num_ctbs_per_slice);
 299    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.
 300                  fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 301    RADEON_ENC_END();
 302 }
 303
 304 static void
 305 radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
 306                               struct pipe_picture_desc *picture)
 307 {
 308    struct pipe_h265_enc_picture_desc *pic =
 309       (struct pipe_h265_enc_picture_desc *) picture;
 310    enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
 311       pic->seq.log2_min_luma_coding_block_size_minus3;
 312    enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
 313    enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
 314       pic->seq.strong_intra_smoothing_enabled_flag;
 315    enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
 316       pic->pic.constrained_intra_pred_flag;
 317    enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
 318    enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
 319    enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
 320
 321    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
 322    RADEON_ENC_CS(enc->enc_pic.
 323                  hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 324    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 325    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 326    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 327    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 328    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 329    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 330    RADEON_ENC_END();
 331 }
 332
 333 static void
 334 radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
 335                                struct pipe_picture_desc *picture)
 336 {
 337    struct pipe_h265_enc_picture_desc *pic =
 338       (struct pipe_h265_enc_picture_desc *) picture;
 339    enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
 340    switch (pic->rc.rate_ctrl_method) {
 341    case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
 342       enc->enc_pic.rc_session_init.rate_control_method =
 343          RENC_UVD_RATE_CONTROL_METHOD_NONE;
 344       break;
 345    case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 346    case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
 347       enc->enc_pic.rc_session_init.rate_control_method =
 348          RENC_UVD_RATE_CONTROL_METHOD_CBR;
 349       break;
 350    case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 351    case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
 352       enc->enc_pic.rc_session_init.rate_control_method =
 353          RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 354       break;
 355    default:
 356       enc->enc_pic.rc_session_init.rate_control_method =
 357          RENC_UVD_RATE_CONTROL_METHOD_NONE;
 358    }
 359
 360    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
 361    RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 362    RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 363    RADEON_ENC_END();
 364 }
 365
 366 static void
 367 radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
 368                              struct pipe_picture_desc *picture)
 369 {
 370    struct pipe_h265_enc_picture_desc *pic =
 371       (struct pipe_h265_enc_picture_desc *) picture;
 372    enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
 373    enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
 374    enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
 375    enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
 376    enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
 377    enc->enc_pic.rc_layer_init.avg_target_bits_per_picture =
 378       pic->rc.target_bits_picture;
 379    enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer =
 380       pic->rc.peak_bits_picture_integer;
 381    enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional =
 382       pic->rc.peak_bits_picture_fraction;
 383
 384    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT);
 385    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 386    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 387    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 388    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 389    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 390    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 391    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 392    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 393    RADEON_ENC_END();
 394 }
 395
 396 static void
 397 radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
 398                                       struct pipe_picture_desc *picture)
 399 {
 400    struct pipe_h265_enc_picture_desc *pic =
 401       (struct pipe_h265_enc_picture_desc *) picture;
 402    enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
 403       pic->slice.slice_loop_filter_across_slices_enabled_flag;
 404    enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
 405       pic->slice.slice_deblocking_filter_disabled_flag;
 406    enc->enc_pic.hevc_deblock.beta_offset_div2 =
 407       pic->slice.slice_beta_offset_div2;
 408    enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
 409    enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
 410    enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
 411
 412    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_DEBLOCKING_FILTER);
 413    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 414    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 415    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 416    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 417    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 418    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 419    RADEON_ENC_END();
 420 }
 421
 422 static void
 423 radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
 424 {
 425    enc->enc_pic.quality_params.vbaq_mode = 0;
 426    enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 427    enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 428
 429    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_QUALITY_PARAMS);
 430    RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 431    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 432    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 433    RADEON_ENC_END();
 434 }
 435
 436 static void
 437 radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
 438 {
 439    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
 440    RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
 441    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 442    int i;
 443
 444    radeon_uvd_enc_reset(enc);
 445    radeon_uvd_enc_set_emulation_prevention(enc, false);
 446    radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
 447    radeon_uvd_enc_code_fixed_bits(enc, 0x4201, 16);
 448    radeon_uvd_enc_byte_align(enc);
 449    radeon_uvd_enc_set_emulation_prevention(enc, true);
 450    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
 451    radeon_uvd_enc_code_fixed_bits(enc,
 452                                   enc->enc_pic.
 453                                   layer_ctrl.max_num_temporal_layers - 1, 3);
 454    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 455    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 456    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 457    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 458    radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
 459    radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
 460    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
 461    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 462
 463    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
 464       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 465
 466    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 467       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 468          radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 469    }
 470
 471    radeon_uvd_enc_code_ue(enc, 0x0);
 472    radeon_uvd_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 473    radeon_uvd_enc_code_ue(enc,
 474                           enc->enc_pic.session_init.aligned_picture_width);
 475    radeon_uvd_enc_code_ue(enc,
 476                           enc->enc_pic.session_init.aligned_picture_height);
 477
 478    int conformance_window_flag =
 479       (enc->enc_pic.crop_top > 0) ||
 480       (enc->enc_pic.crop_bottom > 0) ||
 481       (enc->enc_pic.crop_left > 0) ||
 482       (enc->enc_pic.crop_right > 0) ? 0x1 : 0x0;
 483    radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1);
 484    if (conformance_window_flag == 1) {
 485       radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left);
 486       radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_right);
 487       radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_top);
 488       radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 489    }
 490
 491    radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 492    radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 493    radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 494    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 495    radeon_uvd_enc_code_ue(enc, 1);
 496    radeon_uvd_enc_code_ue(enc, 0x0);
 497    radeon_uvd_enc_code_ue(enc, 0x0);
 498    radeon_uvd_enc_code_ue(enc,
 499                           enc->enc_pic.hevc_spec_misc.
 500                           log2_min_luma_coding_block_size_minus3);
 501    /* Only support CTBSize 64 */
 502    radeon_uvd_enc_code_ue(enc,
 503                           6 -
 504                           (enc->enc_pic.hevc_spec_misc.
 505                            log2_min_luma_coding_block_size_minus3 + 3));
 506    radeon_uvd_enc_code_ue(enc,
 507                           enc->enc_pic.log2_min_transform_block_size_minus2);
 508    radeon_uvd_enc_code_ue(enc,
 509                           enc->enc_pic.
 510                           log2_diff_max_min_transform_block_size);
 511    radeon_uvd_enc_code_ue(enc,
 512                           enc->enc_pic.max_transform_hierarchy_depth_inter);
 513    radeon_uvd_enc_code_ue(enc,
 514                           enc->enc_pic.max_transform_hierarchy_depth_intra);
 515
 516    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 517    radeon_uvd_enc_code_fixed_bits(enc,
 518                                   !enc->enc_pic.hevc_spec_misc.amp_disabled,
 519                                   1);
 520    radeon_uvd_enc_code_fixed_bits(enc,
 521                                   enc->enc_pic.
 522                                   sample_adaptive_offset_enabled_flag, 1);
 523    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 524
 525    radeon_uvd_enc_code_ue(enc, 1);
 526    radeon_uvd_enc_code_ue(enc, 1);
 527    radeon_uvd_enc_code_ue(enc, 0);
 528    radeon_uvd_enc_code_ue(enc, 0);
 529    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 530
 531    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 532
 533    radeon_uvd_enc_code_fixed_bits(enc, 0, 1);
 534    radeon_uvd_enc_code_fixed_bits(enc,
 535                                   enc->enc_pic.hevc_spec_misc.
 536                                   strong_intra_smoothing_enabled, 1);
 537
 538    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 539
 540    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 541
 542    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 543
 544    radeon_uvd_enc_byte_align(enc);
 545    radeon_uvd_enc_flush_headers(enc);
 546    *size_in_bytes = (enc->bits_output + 7) / 8;
 547    RADEON_ENC_END();
 548 }
 549
 550 static void
 551 radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
 552 {
 553    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
 554    RADEON_ENC_CS(RENC_UVD_NALU_TYPE_PPS);
 555    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 556    radeon_uvd_enc_reset(enc);
 557    radeon_uvd_enc_set_emulation_prevention(enc, false);
 558    radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
 559    radeon_uvd_enc_code_fixed_bits(enc, 0x4401, 16);
 560    radeon_uvd_enc_byte_align(enc);
 561    radeon_uvd_enc_set_emulation_prevention(enc, true);
 562    radeon_uvd_enc_code_ue(enc, 0x0);
 563    radeon_uvd_enc_code_ue(enc, 0x0);
 564    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 565    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* output_flag_resent_flag */
 566    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 3); /* num_extra_slice_header_bits */
 567    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 568    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 569    radeon_uvd_enc_code_ue(enc, 0x0);
 570    radeon_uvd_enc_code_ue(enc, 0x0);
 571    radeon_uvd_enc_code_se(enc, 0x0);
 572    radeon_uvd_enc_code_fixed_bits(enc,
 573                                   enc->enc_pic.hevc_spec_misc.
 574                                   constrained_intra_pred_flag, 1);
 575    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 576    if (enc->enc_pic.rc_session_init.rate_control_method ==
 577       RENC_UVD_RATE_CONTROL_METHOD_NONE)
 578       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 579    else {
 580       radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 581       radeon_uvd_enc_code_ue(enc, 0x0);
 582    }
 583    radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 584    radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 585    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 586    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 587    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 588    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 589    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 590    radeon_uvd_enc_code_fixed_bits(enc,
 591                                   enc->enc_pic.hevc_deblock.
 592                                   loop_filter_across_slices_enabled, 1);
 593    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 594    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 595    radeon_uvd_enc_code_fixed_bits(enc,
 596                                   enc->enc_pic.hevc_deblock.
 597                                   deblocking_filter_disabled, 1);
 598
 599    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 600       radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 601       radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 602    }
 603
 604    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 605    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 606    radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 607    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 608
 609    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 610
 611    radeon_uvd_enc_byte_align(enc);
 612    radeon_uvd_enc_flush_headers(enc);
 613    *size_in_bytes = (enc->bits_output + 7) / 8;
 614    RADEON_ENC_END();
 615 }
 616
 617 static void
 618 radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
 619 {
 620    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
 621    RADEON_ENC_CS(RENC_UVD_NALU_TYPE_VPS);
 622    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 623    int i;
 624
 625    radeon_uvd_enc_reset(enc);
 626    radeon_uvd_enc_set_emulation_prevention(enc, false);
 627    radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
 628    radeon_uvd_enc_code_fixed_bits(enc, 0x4001, 16);
 629    radeon_uvd_enc_byte_align(enc);
 630    radeon_uvd_enc_set_emulation_prevention(enc, true);
 631
 632    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
 633    radeon_uvd_enc_code_fixed_bits(enc, 0x3, 2);
 634    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
 635    radeon_uvd_enc_code_fixed_bits(enc,
 636                                   enc->enc_pic.layer_ctrl.
 637                                   max_num_temporal_layers - 1, 3);
 638    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 639    radeon_uvd_enc_code_fixed_bits(enc, 0xffff, 16);
 640    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 641    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 642    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 643    radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
 644    radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
 645    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
 646    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 647
 648    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
 649       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 650
 651    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 652       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 653          radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
 654    }
 655
 656    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 657    radeon_uvd_enc_code_ue(enc, 0x1);
 658    radeon_uvd_enc_code_ue(enc, 0x0);
 659    radeon_uvd_enc_code_ue(enc, 0x0);
 660
 661    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
 662    radeon_uvd_enc_code_ue(enc, 0x0);
 663    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 664    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 665
 666    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 667
 668    radeon_uvd_enc_byte_align(enc);
 669    radeon_uvd_enc_flush_headers(enc);
 670    *size_in_bytes = (enc->bits_output + 7) / 8;
 671    RADEON_ENC_END();
 672 }
 673
 674 static void
 675 radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
 676 {
 677    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
 678    RADEON_ENC_CS(RENC_UVD_NALU_TYPE_AUD);
 679    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 680    radeon_uvd_enc_reset(enc);
 681    radeon_uvd_enc_set_emulation_prevention(enc, false);
 682    radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
 683    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 684    radeon_uvd_enc_code_fixed_bits(enc, 35, 6);
 685    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
 686    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
 687    radeon_uvd_enc_byte_align(enc);
 688    radeon_uvd_enc_set_emulation_prevention(enc, true);
 689    switch (enc->enc_pic.picture_type) {
 690    case PIPE_H265_ENC_PICTURE_TYPE_I:
 691    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 692       radeon_uvd_enc_code_fixed_bits(enc, 0x00, 3);
 693       break;
 694    case PIPE_H265_ENC_PICTURE_TYPE_P:
 695       radeon_uvd_enc_code_fixed_bits(enc, 0x01, 3);
 696       break;
 697    case PIPE_H265_ENC_PICTURE_TYPE_B:
 698       radeon_uvd_enc_code_fixed_bits(enc, 0x02, 3);
 699       break;
 700    default:
 701       assert(0 && "Unsupported picture type!");
 702    }
 703
 704    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 705
 706    radeon_uvd_enc_byte_align(enc);
 707    radeon_uvd_enc_flush_headers(enc);
 708    *size_in_bytes = (enc->bits_output + 7) / 8;
 709    RADEON_ENC_END();
 710 }
 711
 712 static void
 713 radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
 714 {
 715    uint32_t instruction[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = { 0 };
 716    uint32_t num_bits[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = { 0 };
 717    unsigned int inst_index = 0;
 718    unsigned int bit_index = 0;
 719    unsigned int bits_copied = 0;
 720    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_HEADER);
 721    radeon_uvd_enc_reset(enc);
 722    radeon_uvd_enc_set_emulation_prevention(enc, false);
 723
 724    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 725    radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
 726    radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
 727    radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
 728
 729    radeon_uvd_enc_flush_headers(enc);
 730    bit_index++;
 731    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
 732    num_bits[inst_index] = enc->bits_output - bits_copied;
 733    bits_copied = enc->bits_output;
 734    inst_index++;
 735
 736    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE;
 737    inst_index++;
 738
 739    if ((enc->enc_pic.nal_unit_type >= 16)
 740        && (enc->enc_pic.nal_unit_type <= 23))
 741       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 742
 743    radeon_uvd_enc_code_ue(enc, 0x0);
 744
 745    radeon_uvd_enc_flush_headers(enc);
 746    bit_index++;
 747    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
 748    num_bits[inst_index] = enc->bits_output - bits_copied;
 749    bits_copied = enc->bits_output;
 750    inst_index++;
 751
 752    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT;
 753    inst_index++;
 754
 755    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
 756    inst_index++;
 757
 758    switch (enc->enc_pic.picture_type) {
 759    case PIPE_H265_ENC_PICTURE_TYPE_I:
 760    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 761       radeon_uvd_enc_code_ue(enc, 0x2);
 762       break;
 763    case PIPE_H265_ENC_PICTURE_TYPE_P:
 764    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 765       radeon_uvd_enc_code_ue(enc, 0x1);
 766       break;
 767    case PIPE_H265_ENC_PICTURE_TYPE_B:
 768       radeon_uvd_enc_code_ue(enc, 0x0);
 769       break;
 770    default:
 771       radeon_uvd_enc_code_ue(enc, 0x1);
 772    }
 773
 774    if ((enc->enc_pic.nal_unit_type != 19)
 775        && (enc->enc_pic.nal_unit_type != 20)) {
 776       radeon_uvd_enc_code_fixed_bits(enc,
 777                                      enc->enc_pic.pic_order_cnt,
 778                                      enc->enc_pic.log2_max_poc);
 779       if (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P)
 780          radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
 781       else {
 782          radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 783          radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 784          radeon_uvd_enc_code_ue(enc, 0x0);
 785          radeon_uvd_enc_code_ue(enc, 0x0);
 786       }
 787    }
 788
 789    if (enc->enc_pic.sample_adaptive_offset_enabled_flag)
 790       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);      /* slice_sao_luma_flag */
 791
 792    if ((enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_P) ||
 793        (enc->enc_pic.picture_type == PIPE_H265_ENC_PICTURE_TYPE_B)) {
 794       radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
 795       radeon_uvd_enc_code_fixed_bits(enc,
 796                                      enc->enc_pic.hevc_spec_misc.
 797                                      cabac_init_flag, 1);
 798       radeon_uvd_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
 799    }
 800
 801    radeon_uvd_enc_flush_headers(enc);
 802    bit_index++;
 803    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
 804    num_bits[inst_index] = enc->bits_output - bits_copied;
 805    bits_copied = enc->bits_output;
 806    inst_index++;
 807
 808    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 809    inst_index++;
 810
 811    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
 812        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
 813       radeon_uvd_enc_code_fixed_bits(enc,
 814                                      enc->enc_pic.hevc_deblock.
 815                                      loop_filter_across_slices_enabled, 1);
 816
 817       radeon_uvd_enc_flush_headers(enc);
 818       bit_index++;
 819       instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
 820       num_bits[inst_index] = enc->bits_output - bits_copied;
 821       bits_copied = enc->bits_output;
 822       inst_index++;
 823    }
 824
 825    instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_END;
 826
 827    for (int i = bit_index;
 828         i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 829       RADEON_ENC_CS(0x00000000);
 830
 831    for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS;
 832         j++) {
 833       RADEON_ENC_CS(instruction[j]);
 834       RADEON_ENC_CS(num_bits[j]);
 835    }
 836
 837    RADEON_ENC_END();
 838 }
 839
 840 static void
 841 radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
 842 {
 843    struct si_screen *sscreen = (struct si_screen *) enc->screen;
 844
 845    enc->enc_pic.ctx_buf.swizzle_mode = 0;
 846    if (sscreen->info.chip_class < GFX9) {
 847       enc->enc_pic.ctx_buf.rec_luma_pitch =
 848          (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
 849       enc->enc_pic.ctx_buf.rec_chroma_pitch =
 850          (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
 851    }
 852    else {
 853       enc->enc_pic.ctx_buf.rec_luma_pitch =
 854          enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
 855       enc->enc_pic.ctx_buf.rec_chroma_pitch =
 856          enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
 857    }
 858    enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 859
 860    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER);
 861    RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 862    RADEON_ENC_CS(0x00000000);   // reserved
 863    RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 864    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 865    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 866    RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 867    /* reconstructed_picture_1_luma_offset */
 868    RADEON_ENC_CS(0x00000000);
 869    /* reconstructed_picture_1_chroma_offset */
 870    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch *
 871                  align(enc->base.height, 16));
 872    /* reconstructed_picture_2_luma_offset */
 873    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch *
 874                  align(enc->base.height, 16) * 3 / 2);
 875    /* reconstructed_picture_2_chroma_offset */
 876    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch *
 877                  align(enc->base.height, 16) * 5 / 2);
 878
 879    for (int i = 0; i < 136; i++)
 880       RADEON_ENC_CS(0x00000000);
 881
 882    RADEON_ENC_END();
 883 }
 884
 885 static void
 886 radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
 887 {
 888    enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
 889    enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
 890    enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
 891
 892    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
 893    RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
 894    RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
 895    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
 896    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
 897    RADEON_ENC_END();
 898 }
 899
 900 static void
 901 radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
 902 {
 903    enc->enc_pic.fb_buf.mode = RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR;
 904    enc->enc_pic.fb_buf.feedback_buffer_size = 16;
 905    enc->enc_pic.fb_buf.feedback_data_size = 40;
 906
 907    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_FEEDBACK_BUFFER);
 908    RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
 909    RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
 910    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
 911    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
 912    RADEON_ENC_END();
 913 }
 914
 915 static void
 916 radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
 917 {
 918    enc->enc_pic.intra_ref.intra_refresh_mode =
 919       RENC_UVD_INTRA_REFRESH_MODE_NONE;
 920    enc->enc_pic.intra_ref.offset = 0;
 921    enc->enc_pic.intra_ref.region_size = 0;
 922
 923    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INTRA_REFRESH);
 924    RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
 925    RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
 926    RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
 927    RADEON_ENC_END();
 928 }
 929
 930 static void
 931 radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
 932                           struct pipe_picture_desc *picture)
 933 {
 934    struct pipe_h265_enc_picture_desc *pic =
 935       (struct pipe_h265_enc_picture_desc *) picture;
 936    enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
 937    enc->enc_pic.rc_per_pic.min_qp_app = 0;
 938    enc->enc_pic.rc_per_pic.max_qp_app = 51;
 939    enc->enc_pic.rc_per_pic.max_au_size = 0;
 940    enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
 941    enc->enc_pic.rc_per_pic.skip_frame_enable = false;
 942    enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
 943
 944    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE);
 945    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
 946    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
 947    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
 948    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
 949    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
 950    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
 951    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
 952    RADEON_ENC_END();
 953 }
 954
 955 static void
 956 radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
 957 {
 958    struct si_screen *sscreen = (struct si_screen *) enc->screen;
 959    switch (enc->enc_pic.picture_type) {
 960    case PIPE_H265_ENC_PICTURE_TYPE_I:
 961    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 962       enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
 963       break;
 964    case PIPE_H265_ENC_PICTURE_TYPE_P:
 965       enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P;
 966       break;
 967    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 968       enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P_SKIP;
 969       break;
 970    case PIPE_H265_ENC_PICTURE_TYPE_B:
 971       enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_B;
 972       break;
 973    default:
 974       enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
 975    }
 976
 977    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
 978    if (sscreen->info.chip_class < GFX9) {
 979       enc->enc_pic.enc_params.input_pic_luma_pitch =
 980          (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
 981       enc->enc_pic.enc_params.input_pic_chroma_pitch =
 982          (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
 983    }
 984    else {
 985       enc->enc_pic.enc_params.input_pic_luma_pitch =
 986          enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
 987       enc->enc_pic.enc_params.input_pic_chroma_pitch =
 988          enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
 989    }
 990    enc->enc_pic.enc_params.input_pic_swizzle_mode =
 991       RENC_UVD_SWIZZLE_MODE_LINEAR;
 992
 993    if (enc->enc_pic.enc_params.pic_type == RENC_UVD_PICTURE_TYPE_I)
 994       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
 995    else
 996       enc->enc_pic.enc_params.reference_picture_index =
 997          (enc->enc_pic.frame_num - 1) % 2;
 998
 999    enc->enc_pic.enc_params.reconstructed_picture_index =
1000       enc->enc_pic.frame_num % 2;
1001
1002    RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
1003    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1004    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1005
1006    if (sscreen->info.chip_class < GFX9) {
1007       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
1008                       enc->luma->u.legacy.level[0].offset);
1009       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
1010                       enc->chroma->u.legacy.level[0].offset);
1011    }
1012    else {
1013       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
1014                       enc->luma->u.gfx9.surf_offset);
1015       RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM,
1016                       enc->chroma->u.gfx9.surf_offset);
1017    }
1018    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1019    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1020    RADEON_ENC_CS(0x00000000);   // reserved
1021    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1022    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1023    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1024    RADEON_ENC_END();
1025 }
1026
1027 static void
1028 radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
1029 {
1030    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INITIALIZE);
1031    RADEON_ENC_END();
1032 }
1033
1034 static void
1035 radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
1036 {
1037    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_CLOSE_SESSION);
1038    RADEON_ENC_END();
1039 }
1040
1041 static void
1042 radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
1043 {
1044    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_ENCODE);
1045    RADEON_ENC_END();
1046 }
1047
1048 static void
1049 radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
1050 {
1051    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC);
1052    RADEON_ENC_END();
1053 }
1054
1055 static void
1056 radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
1057 {
1058    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1059    RADEON_ENC_END();
1060 }
1061
1062 static void
1063 radeon_uvd_enc_op_speed(struct radeon_uvd_encoder *enc)
1064 {
1065    RADEON_ENC_BEGIN(RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE);
1066    RADEON_ENC_END();
1067 }
1068
1069 static void
1070 begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
1071 {
1072    radeon_uvd_enc_session_info(enc);
1073    enc->total_task_size = 0;
1074    radeon_uvd_enc_task_info(enc, enc->need_feedback);
1075    radeon_uvd_enc_op_init(enc);
1076
1077    radeon_uvd_enc_session_init_hevc(enc);
1078    radeon_uvd_enc_slice_control_hevc(enc);
1079    radeon_uvd_enc_spec_misc_hevc(enc, pic);
1080    radeon_uvd_enc_deblocking_filter_hevc(enc, pic);
1081
1082    radeon_uvd_enc_layer_control(enc);
1083    radeon_uvd_enc_rc_session_init(enc, pic);
1084    radeon_uvd_enc_quality_params(enc);
1085    radeon_uvd_enc_layer_select(enc);
1086    radeon_uvd_enc_rc_layer_init(enc, pic);
1087    radeon_uvd_enc_layer_select(enc);
1088    radeon_uvd_enc_rc_per_pic(enc, pic);
1089    radeon_uvd_enc_op_init_rc(enc);
1090    radeon_uvd_enc_op_init_rc_vbv(enc);
1091    *enc->p_task_size = (enc->total_task_size);
1092 }
1093
1094 static void
1095 encode(struct radeon_uvd_encoder *enc)
1096 {
1097    radeon_uvd_enc_session_info(enc);
1098    enc->total_task_size = 0;
1099    radeon_uvd_enc_task_info(enc, enc->need_feedback);
1100
1101    radeon_uvd_enc_nalu_aud_hevc(enc);
1102
1103    if (enc->enc_pic.is_iframe) {
1104       radeon_uvd_enc_nalu_vps_hevc(enc);
1105       radeon_uvd_enc_nalu_pps_hevc(enc);
1106       radeon_uvd_enc_nalu_sps_hevc(enc);
1107    }
1108    radeon_uvd_enc_slice_header_hevc(enc);
1109    radeon_uvd_enc_encode_params_hevc(enc);
1110
1111    radeon_uvd_enc_ctx(enc);
1112    radeon_uvd_enc_bitstream(enc);
1113    radeon_uvd_enc_feedback(enc);
1114    radeon_uvd_enc_intra_refresh(enc);
1115
1116    radeon_uvd_enc_op_speed(enc);
1117    radeon_uvd_enc_op_enc(enc);
1118    *enc->p_task_size = (enc->total_task_size);
1119 }
1120
1121 static void
1122 destroy(struct radeon_uvd_encoder *enc)
1123 {
1124    radeon_uvd_enc_session_info(enc);
1125    enc->total_task_size = 0;
1126    radeon_uvd_enc_task_info(enc, enc->need_feedback);
1127    radeon_uvd_enc_op_close(enc);
1128    *enc->p_task_size = (enc->total_task_size);
1129 }
1130
1131 void
1132 radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
1133 {
1134    enc->begin = begin;
1135    enc->encode = encode;
1136    enc->destroy = destroy;
1137 }