src/gallium/drivers/radeon/radeon_vce.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <stdio.h>
  35
  36 #include "pipe/p_video_codec.h"
  37
  38 #include "util/u_video.h"
  39 #include "util/u_memory.h"
  40
  41 #include "vl/vl_video_buffer.h"
  42
  43 #include "r600_pipe_common.h"
  44 #include "radeon_video.h"
  45 #include "radeon_vce.h"
  46
  47 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
  48 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
  49 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
  50 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
  51 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
  52 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
  53
  54 /**
  55  * flush commands to the hardware
  56  */
  57 static void flush(struct rvce_encoder *enc)
  58 {
  59         enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL, 0);
  60         enc->task_info_idx = 0;
  61         enc->bs_idx = 0;
  62 }
  63
  64 #if 0
  65 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
  66 {
  67         uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
  68         unsigned i = 0;
  69         fprintf(stderr, "\n");
  70         fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
  71         fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
  72         fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
  73         fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
  74         fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
  75         fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
  76         fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
  77         fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
  78         fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
  79         fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
  80         fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
  81         fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
  82         fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
  83         fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
  84         fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
  85         fprintf(stderr, "\n");
  86         enc->ws->buffer_unmap(fb->res->buf);
  87 }
  88 #endif
  89
  90 /**
  91  * reset the CPB handling
  92  */
  93 static void reset_cpb(struct rvce_encoder *enc)
  94 {
  95         unsigned i;
  96
  97         LIST_INITHEAD(&enc->cpb_slots);
  98         for (i = 0; i < enc->cpb_num; ++i) {
  99                 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
 100                 slot->index = i;
 101                 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
 102                 slot->frame_num = 0;
 103                 slot->pic_order_cnt = 0;
 104                 LIST_ADDTAIL(&slot->list, &enc->cpb_slots);
 105         }
 106 }
 107
 108 /**
 109  * sort l0 and l1 to the top of the list
 110  */
 111 static void sort_cpb(struct rvce_encoder *enc)
 112 {
 113         struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
 114
 115         LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
 116                 if (i->frame_num == enc->pic.ref_idx_l0)
 117                         l0 = i;
 118
 119                 if (i->frame_num == enc->pic.ref_idx_l1)
 120                         l1 = i;
 121
 122                 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
 123                         break;
 124
 125                 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
 126                     l0 && l1)
 127                         break;
 128         }
 129
 130         if (l1) {
 131                 LIST_DEL(&l1->list);
 132                 LIST_ADD(&l1->list, &enc->cpb_slots);
 133         }
 134
 135         if (l0) {
 136                 LIST_DEL(&l0->list);
 137                 LIST_ADD(&l0->list, &enc->cpb_slots);
 138         }
 139 }
 140
 141 /**
 142  * get number of cpbs based on dpb
 143  */
 144 static unsigned get_cpb_num(struct rvce_encoder *enc)
 145 {
 146         unsigned w = align(enc->base.width, 16) / 16;
 147         unsigned h = align(enc->base.height, 16) / 16;
 148         unsigned dpb;
 149
 150         switch (enc->base.level) {
 151         case 10:
 152                 dpb = 396;
 153                 break;
 154         case 11:
 155                 dpb = 900;
 156                 break;
 157         case 12:
 158         case 13:
 159         case 20:
 160                 dpb = 2376;
 161                 break;
 162         case 21:
 163                 dpb = 4752;
 164                 break;
 165         case 22:
 166         case 30:
 167                 dpb = 8100;
 168                 break;
 169         case 31:
 170                 dpb = 18000;
 171                 break;
 172         case 32:
 173                 dpb = 20480;
 174                 break;
 175         case 40:
 176         case 41:
 177                 dpb = 32768;
 178                 break;
 179         default:
 180         case 42:
 181                 dpb = 34816;
 182                 break;
 183         case 50:
 184                 dpb = 110400;
 185                 break;
 186         case 51:
 187                 dpb = 184320;
 188                 break;
 189         }
 190
 191         return MIN2(dpb / (w * h), 16);
 192 }
 193
 194 /**
 195  * Get the slot for the currently encoded frame
 196  */
 197 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
 198 {
 199         return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
 200 }
 201
 202 /**
 203  * Get the slot for L0
 204  */
 205 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
 206 {
 207         return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
 208 }
 209
 210 /**
 211  * Get the slot for L1
 212  */
 213 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
 214 {
 215         return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
 216 }
 217
 218 /**
 219  * Calculate the offsets into the CPB
 220  */
 221 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
 222                        signed *luma_offset, signed *chroma_offset)
 223 {
 224         unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
 225         unsigned vpitch = align(enc->luma->npix_y, 16);
 226         unsigned fsize = pitch * (vpitch + vpitch / 2);
 227
 228         *luma_offset = slot->index * fsize;
 229         *chroma_offset = *luma_offset + pitch * vpitch;
 230 }
 231
 232 /**
 233  * destroy this video encoder
 234  */
 235 static void rvce_destroy(struct pipe_video_codec *encoder)
 236 {
 237         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 238         if (enc->stream_handle) {
 239                 struct rvid_buffer fb;
 240                 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
 241                 enc->fb = &fb;
 242                 enc->session(enc);
 243                 enc->feedback(enc);
 244                 enc->destroy(enc);
 245                 flush(enc);
 246                 rvid_destroy_buffer(&fb);
 247         }
 248         rvid_destroy_buffer(&enc->cpb);
 249         enc->ws->cs_destroy(enc->cs);
 250         FREE(enc->cpb_array);
 251         FREE(enc);
 252 }
 253
 254 static void rvce_begin_frame(struct pipe_video_codec *encoder,
 255                              struct pipe_video_buffer *source,
 256                              struct pipe_picture_desc *picture)
 257 {
 258         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 259         struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
 260         struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 261
 262         bool need_rate_control =
 263                 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
 264                 enc->pic.quant_i_frames != pic->quant_i_frames ||
 265                 enc->pic.quant_p_frames != pic->quant_p_frames ||
 266                 enc->pic.quant_b_frames != pic->quant_b_frames;
 267
 268         enc->pic = *pic;
 269
 270         enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
 271         enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
 272
 273         if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
 274                 reset_cpb(enc);
 275         else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
 276                  pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
 277                 sort_cpb(enc);
 278
 279         if (!enc->stream_handle) {
 280                 struct rvid_buffer fb;
 281                 enc->stream_handle = rvid_alloc_stream_handle();
 282                 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
 283                 enc->fb = &fb;
 284                 enc->session(enc);
 285                 enc->create(enc);
 286                 enc->config(enc);
 287                 enc->feedback(enc);
 288                 flush(enc);
 289                 //dump_feedback(enc, &fb);
 290                 rvid_destroy_buffer(&fb);
 291                 need_rate_control = false;
 292         }
 293
 294         if (need_rate_control) {
 295                 enc->session(enc);
 296                 enc->config(enc);
 297                 flush(enc);
 298         }
 299 }
 300
 301 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
 302                                   struct pipe_video_buffer *source,
 303                                   struct pipe_resource *destination,
 304                                   void **fb)
 305 {
 306         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 307         enc->get_buffer(destination, &enc->bs_handle, NULL);
 308         enc->bs_size = destination->width0;
 309
 310         *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
 311         if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
 312                 RVID_ERR("Can't create feedback buffer.\n");
 313                 return;
 314         }
 315         if (!enc->cs->cdw)
 316                 enc->session(enc);
 317         enc->encode(enc);
 318         enc->feedback(enc);
 319 }
 320
 321 static void rvce_end_frame(struct pipe_video_codec *encoder,
 322                            struct pipe_video_buffer *source,
 323                            struct pipe_picture_desc *picture)
 324 {
 325         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 326         struct rvce_cpb_slot *slot = LIST_ENTRY(
 327                 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
 328
 329         if (!enc->dual_inst || enc->bs_idx > 1)
 330                 flush(enc);
 331
 332         /* update the CPB backtrack with the just encoded frame */
 333         slot->picture_type = enc->pic.picture_type;
 334         slot->frame_num = enc->pic.frame_num;
 335         slot->pic_order_cnt = enc->pic.pic_order_cnt;
 336         if (!enc->pic.not_referenced) {
 337                 LIST_DEL(&slot->list);
 338                 LIST_ADD(&slot->list, &enc->cpb_slots);
 339         }
 340 }
 341
 342 static void rvce_get_feedback(struct pipe_video_codec *encoder,
 343                               void *feedback, unsigned *size)
 344 {
 345         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 346         struct rvid_buffer *fb = feedback;
 347
 348         if (size) {
 349                 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
 350
 351                 if (ptr[1]) {
 352                         *size = ptr[4] - ptr[9];
 353                 } else {
 354                         *size = 0;
 355                 }
 356
 357                 enc->ws->buffer_unmap(fb->res->buf);
 358         }
 359         //dump_feedback(enc, fb);
 360         rvid_destroy_buffer(fb);
 361         FREE(fb);
 362 }
 363
 364 /**
 365  * flush any outstanding command buffers to the hardware
 366  */
 367 static void rvce_flush(struct pipe_video_codec *encoder)
 368 {
 369         struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
 370
 371         flush(enc);
 372 }
 373
 374 static void rvce_cs_flush(void *ctx, unsigned flags,
 375                           struct pipe_fence_handle **fence)
 376 {
 377         // just ignored
 378 }
 379
 380 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
 381                                              const struct pipe_video_codec *templ,
 382                                              struct radeon_winsys* ws,
 383                                              rvce_get_buffer get_buffer)
 384 {
 385         struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
 386         struct r600_common_context *rctx = (struct r600_common_context*)context;
 387         struct rvce_encoder *enc;
 388         struct pipe_video_buffer *tmp_buf, templat = {};
 389         struct radeon_surf *tmp_surf;
 390         unsigned cpb_size;
 391
 392         if (!rscreen->info.vce_fw_version) {
 393                 RVID_ERR("Kernel doesn't supports VCE!\n");
 394                 return NULL;
 395
 396         } else if (!rvce_is_fw_version_supported(rscreen)) {
 397                 RVID_ERR("Unsupported VCE fw version loaded!\n");
 398                 return NULL;
 399         }
 400
 401         enc = CALLOC_STRUCT(rvce_encoder);
 402         if (!enc)
 403                 return NULL;
 404
 405         if (rscreen->info.drm_major == 3)
 406                 enc->use_vm = true;
 407         if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
 408             rscreen->info.drm_major == 3)
 409                 enc->use_vui = true;
 410         if (rscreen->info.family >= CHIP_TONGA &&
 411              rscreen->info.family != CHIP_STONEY)
 412                 enc->dual_pipe = true;
 413         /* TODO enable B frame with dual instance */
 414         if ((rscreen->info.family >= CHIP_TONGA) &&
 415                 (templ->max_references == 1) &&
 416                 (rscreen->info.vce_harvest_config == 0))
 417                 enc->dual_inst = true;
 418
 419         enc->base = *templ;
 420         enc->base.context = context;
 421
 422         enc->base.destroy = rvce_destroy;
 423         enc->base.begin_frame = rvce_begin_frame;
 424         enc->base.encode_bitstream = rvce_encode_bitstream;
 425         enc->base.end_frame = rvce_end_frame;
 426         enc->base.flush = rvce_flush;
 427         enc->base.get_feedback = rvce_get_feedback;
 428         enc->get_buffer = get_buffer;
 429
 430         enc->screen = context->screen;
 431         enc->ws = ws;
 432         enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc, NULL);
 433         if (!enc->cs) {
 434                 RVID_ERR("Can't get command submission context.\n");
 435                 goto error;
 436         }
 437
 438         templat.buffer_format = PIPE_FORMAT_NV12;
 439         templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
 440         templat.width = enc->base.width;
 441         templat.height = enc->base.height;
 442         templat.interlaced = false;
 443         if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
 444                 RVID_ERR("Can't create video buffer.\n");
 445                 goto error;
 446         }
 447
 448         enc->cpb_num = get_cpb_num(enc);
 449         if (!enc->cpb_num)
 450                 goto error;
 451
 452         get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
 453         cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
 454         cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
 455         cpb_size = cpb_size * 3 / 2;
 456         cpb_size = cpb_size * enc->cpb_num;
 457         if (enc->dual_pipe)
 458                 cpb_size +=  RVCE_MAX_AUX_BUFFER_NUM *
 459                         RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
 460         tmp_buf->destroy(tmp_buf);
 461         if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
 462                 RVID_ERR("Can't create CPB buffer.\n");
 463                 goto error;
 464         }
 465
 466         enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
 467         if (!enc->cpb_array)
 468                 goto error;
 469
 470         reset_cpb(enc);
 471
 472         switch (rscreen->info.vce_fw_version) {
 473         case FW_40_2_2:
 474                 radeon_vce_40_2_2_init(enc);
 475                 break;
 476
 477         case FW_50_0_1:
 478         case FW_50_1_2:
 479         case FW_50_10_2:
 480         case FW_50_17_3:
 481                 radeon_vce_50_init(enc);
 482                 break;
 483
 484         case FW_52_0_3:
 485                 radeon_vce_52_init(enc);
 486                 break;
 487
 488         default:
 489                 goto error;
 490         }
 491
 492         return &enc->base;
 493
 494 error:
 495         if (enc->cs)
 496                 enc->ws->cs_destroy(enc->cs);
 497
 498         rvid_destroy_buffer(&enc->cpb);
 499
 500         FREE(enc->cpb_array);
 501         FREE(enc);
 502         return NULL;
 503 }
 504
 505 /**
 506  * check if kernel has the right fw version loaded
 507  */
 508 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
 509 {
 510         switch (rscreen->info.vce_fw_version) {
 511         case FW_40_2_2:
 512         case FW_50_0_1:
 513         case FW_50_1_2:
 514         case FW_50_10_2:
 515         case FW_50_17_3:
 516         case FW_52_0_3:
 517                 return true;
 518         default:
 519                 return false;
 520         }
 521 }
 522
 523 /**
 524  * Add the buffer as relocation to the current command submission
 525  */
 526 void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
 527                      enum radeon_bo_usage usage, enum radeon_bo_domain domain,
 528                      signed offset)
 529 {
 530         int reloc_idx;
 531
 532         reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage, domain, RADEON_PRIO_VCE);
 533         if (enc->use_vm) {
 534                 uint64_t addr;
 535                 addr = enc->ws->buffer_get_virtual_address(buf);
 536                 addr = addr + offset;
 537                 RVCE_CS(addr >> 32);
 538                 RVCE_CS(addr);
 539         } else {
 540                 RVCE_CS(reloc_idx * 4);
 541                 RVCE_CS(offset);
 542         }
 543 }