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etnaviv: update Android build files
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <assert.h>
29 #include <stdio.h>
30
31 #include "pipe/p_video_codec.h"
32
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35
36 #include "vl/vl_mpeg12_decoder.h"
37
38 #include "radeonsi/si_pipe.h"
39 #include "radeon_video.h"
40 #include "radeon_vcn_dec.h"
41 #include "vl/vl_probs_table.h"
42
43 #define FB_BUFFER_OFFSET 0x1000
44 #define FB_BUFFER_SIZE 2048
45 #define IT_SCALING_TABLE_SIZE 992
46 #define VP9_PROBS_TABLE_SIZE (RDECODE_VP9_PROBS_DATA_SIZE + 256)
47 #define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)
48
49 #define RDECODE_VCN1_GPCOM_VCPU_CMD 0x2070c
50 #define RDECODE_VCN1_GPCOM_VCPU_DATA0 0x20710
51 #define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714
52 #define RDECODE_VCN1_ENGINE_CNTL 0x20718
53
54 #define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2)
55 #define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2)
56 #define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
57 #define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2)
58
59 #define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c
60 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
61 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
62 #define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4
63
64 #define NUM_MPEG2_REFS 6
65 #define NUM_H264_REFS 17
66 #define NUM_VC1_REFS 5
67 #define NUM_VP9_REFS 8
68
69 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
70 struct pipe_h264_picture_desc *pic)
71 {
72 rvcn_dec_message_avc_t result;
73
74 memset(&result, 0, sizeof(result));
75 switch (pic->base.profile) {
76 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
77 case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
78 result.profile = RDECODE_H264_PROFILE_BASELINE;
79 break;
80
81 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
82 result.profile = RDECODE_H264_PROFILE_MAIN;
83 break;
84
85 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
86 result.profile = RDECODE_H264_PROFILE_HIGH;
87 break;
88
89 default:
90 assert(0);
91 break;
92 }
93
94 result.level = dec->base.level;
95
96 result.sps_info_flags = 0;
97 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
98 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
99 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
100 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
101 result.sps_info_flags |= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT;
102
103 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
104 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
105 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
106 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
107 result.log2_max_pic_order_cnt_lsb_minus4 =
108 pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
109
110 switch (dec->base.chroma_format) {
111 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
112 break;
113 case PIPE_VIDEO_CHROMA_FORMAT_400:
114 result.chroma_format = 0;
115 break;
116 case PIPE_VIDEO_CHROMA_FORMAT_420:
117 result.chroma_format = 1;
118 break;
119 case PIPE_VIDEO_CHROMA_FORMAT_422:
120 result.chroma_format = 2;
121 break;
122 case PIPE_VIDEO_CHROMA_FORMAT_444:
123 result.chroma_format = 3;
124 break;
125 }
126
127 result.pps_info_flags = 0;
128 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
129 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
130 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
131 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
132 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
133 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
134 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
135 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
136
137 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
138 result.slice_group_map_type = pic->pps->slice_group_map_type;
139 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
140 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
141 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
142 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
143
144 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
145 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
146
147 memcpy(dec->it, result.scaling_list_4x4, 6*16);
148 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
149
150 result.num_ref_frames = pic->num_ref_frames;
151
152 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
153 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
154
155 result.frame_num = pic->frame_num;
156 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
157 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
158 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
159 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
160
161 result.decoded_pic_idx = pic->frame_num;
162
163 return result;
164 }
165
166 static void radeon_dec_destroy_associated_data(void *data)
167 {
168 /* NOOP, since we only use an intptr */
169 }
170
171 static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
172 struct pipe_video_buffer *target,
173 struct pipe_h265_picture_desc *pic)
174 {
175 rvcn_dec_message_hevc_t result;
176 unsigned i, j;
177
178 memset(&result, 0, sizeof(result));
179 result.sps_info_flags = 0;
180 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
181 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
182 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
183 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
184 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
185 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
186 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
187 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
188 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
189 if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
190 result.sps_info_flags |= 1 << 9;
191 if (pic->UseRefPicList == true)
192 result.sps_info_flags |= 1 << 10;
193
194 result.chroma_format = pic->pps->sps->chroma_format_idc;
195 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
196 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
197 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
198 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
199 result.log2_min_luma_coding_block_size_minus3 =
200 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
201 result.log2_diff_max_min_luma_coding_block_size =
202 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
203 result.log2_min_transform_block_size_minus2 =
204 pic->pps->sps->log2_min_transform_block_size_minus2;
205 result.log2_diff_max_min_transform_block_size =
206 pic->pps->sps->log2_diff_max_min_transform_block_size;
207 result.max_transform_hierarchy_depth_inter =
208 pic->pps->sps->max_transform_hierarchy_depth_inter;
209 result.max_transform_hierarchy_depth_intra =
210 pic->pps->sps->max_transform_hierarchy_depth_intra;
211 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
212 result.pcm_sample_bit_depth_chroma_minus1 =
213 pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
214 result.log2_min_pcm_luma_coding_block_size_minus3 =
215 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
216 result.log2_diff_max_min_pcm_luma_coding_block_size =
217 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
218 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
219
220 result.pps_info_flags = 0;
221 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
222 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
223 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
224 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
225 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
226 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
227 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
228 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
229 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
230 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
231 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
232 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
233 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
234 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
235 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
236 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
237 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
238 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
239 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
240 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
241
242 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
243 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
244 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
245 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
246 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
247 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
248 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
249 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
250 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
251 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
252 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
253 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
254 result.init_qp_minus26 = pic->pps->init_qp_minus26;
255
256 for (i = 0; i < 19; ++i)
257 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
258
259 for (i = 0; i < 21; ++i)
260 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
261
262 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
263 result.curr_poc = pic->CurrPicOrderCntVal;
264
265 for (i = 0 ; i < 16 ; i++) {
266 for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
267 if (dec->render_pic_list[i] == pic->ref[j])
268 break;
269 if (j == 15)
270 dec->render_pic_list[i] = NULL;
271 else if (pic->ref[j+1] == NULL)
272 dec->render_pic_list[i] = NULL;
273 }
274 }
275 for (i = 0 ; i < 16 ; i++) {
276 if (dec->render_pic_list[i] == NULL) {
277 dec->render_pic_list[i] = target;
278 result.curr_idx = i;
279 break;
280 }
281 }
282
283 vl_video_buffer_set_associated_data(target, &dec->base,
284 (void *)(uintptr_t)result.curr_idx,
285 &radeon_dec_destroy_associated_data);
286
287 for (i = 0; i < 16; ++i) {
288 struct pipe_video_buffer *ref = pic->ref[i];
289 uintptr_t ref_pic = 0;
290
291 result.poc_list[i] = pic->PicOrderCntVal[i];
292
293 if (ref)
294 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
295 else
296 ref_pic = 0x7F;
297 result.ref_pic_list[i] = ref_pic;
298 }
299
300 for (i = 0; i < 8; ++i) {
301 result.ref_pic_set_st_curr_before[i] = 0xFF;
302 result.ref_pic_set_st_curr_after[i] = 0xFF;
303 result.ref_pic_set_lt_curr[i] = 0xFF;
304 }
305
306 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
307 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
308
309 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
310 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
311
312 for (i = 0; i < pic->NumPocLtCurr; ++i)
313 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
314
315 for (i = 0; i < 6; ++i)
316 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
317
318 for (i = 0; i < 2; ++i)
319 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
320
321 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
322 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
323 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
324 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
325
326 for (i = 0 ; i < 2 ; i++) {
327 for (j = 0 ; j < 15 ; j++)
328 result.direct_reflist[i][j] = pic->RefPicList[i][j];
329 }
330
331 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
332 if (target->buffer_format == PIPE_FORMAT_P010 ||
333 target->buffer_format == PIPE_FORMAT_P016) {
334 result.p010_mode = 1;
335 result.msb_mode = 1;
336 } else {
337 result.p010_mode = 0;
338 result.luma_10to8 = 5;
339 result.chroma_10to8 = 5;
340 result.hevc_reserved[0] = 4; /* sclr_luma10to8 */
341 result.hevc_reserved[1] = 4; /* sclr_chroma10to8 */
342 }
343 }
344
345 return result;
346 }
347
348 static void fill_probs_table(void *ptr)
349 {
350 rvcn_dec_vp9_probs_t *probs = (rvcn_dec_vp9_probs_t *)ptr;
351
352 memcpy(&probs->coef_probs[0], default_coef_probs_4x4, sizeof(default_coef_probs_4x4));
353 memcpy(&probs->coef_probs[1], default_coef_probs_8x8, sizeof(default_coef_probs_8x8));
354 memcpy(&probs->coef_probs[2], default_coef_probs_16x16, sizeof(default_coef_probs_16x16));
355 memcpy(&probs->coef_probs[3], default_coef_probs_32x32, sizeof(default_coef_probs_32x32));
356 memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
357 memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
358 memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
359 memcpy(probs->switchable_interp_prob, default_switchable_interp_prob, sizeof(default_switchable_interp_prob));
360 memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
361 memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
362 memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
363 memcpy(probs->intra_inter_prob, default_intra_inter_p, sizeof(default_intra_inter_p));
364 memcpy(probs->comp_inter_prob, default_comp_inter_p, sizeof(default_comp_inter_p));
365 memcpy(probs->comp_ref_prob, default_comp_ref_p, sizeof(default_comp_ref_p));
366 memcpy(probs->tx_probs_32x32, default_tx_probs_32x32, sizeof(default_tx_probs_32x32));
367 memcpy(probs->tx_probs_16x16, default_tx_probs_16x16, sizeof(default_tx_probs_16x16));
368 memcpy(probs->tx_probs_8x8, default_tx_probs_8x8, sizeof(default_tx_probs_8x8));
369 memcpy(probs->mv_joints, default_nmv_joints, sizeof(default_nmv_joints));
370 memcpy(&probs->mv_comps[0], default_nmv_components, sizeof(default_nmv_components));
371 memset(&probs->nmvc_mask, 0, sizeof(rvcn_dec_vp9_nmv_ctx_mask_t));
372 }
373
374 static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
375 struct pipe_video_buffer *target,
376 struct pipe_vp9_picture_desc *pic)
377 {
378 rvcn_dec_message_vp9_t result;
379 unsigned i;
380
381 memset(&result, 0, sizeof(result));
382
383 /* segment table */
384 rvcn_dec_vp9_probs_segment_t *prbs = (rvcn_dec_vp9_probs_segment_t *)(dec->probs);
385
386 if (pic->picture_parameter.pic_fields.segmentation_enabled) {
387 for (i = 0; i < 8; ++i) {
388 prbs->seg.feature_data[i] =
389 (pic->slice_parameter.seg_param[i].alt_quant & 0xffff) |
390 ((pic->slice_parameter.seg_param[i].alt_lf & 0xff) << 16) |
391 ((pic->slice_parameter.seg_param[i].segment_flags.segment_reference & 0xf) << 24);
392 prbs->seg.feature_mask[i] =
393 (pic->slice_parameter.seg_param[i].alt_quant_enabled << 0) |
394 (pic->slice_parameter.seg_param[i].alt_lf_enabled << 1) |
395 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_enabled << 2) |
396 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_skipped << 3);
397 }
398
399 for (i = 0; i < 7; ++i)
400 prbs->seg.tree_probs[i] = pic->picture_parameter.mb_segment_tree_probs[i];
401
402 for (i = 0; i < 3; ++i)
403 prbs->seg.pred_probs[i] = pic->picture_parameter.segment_pred_probs[i];
404
405 prbs->seg.abs_delta = 0;
406 } else
407 memset(&prbs->seg, 0, 256);
408
409 result.frame_header_flags =
410 (pic->picture_parameter.pic_fields.frame_type <<
411 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
412 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
413
414 result.frame_header_flags |=
415 (pic->picture_parameter.pic_fields.error_resilient_mode <<
416 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
417 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
418
419 result.frame_header_flags |=
420 (pic->picture_parameter.pic_fields.intra_only <<
421 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
422 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
423
424 result.frame_header_flags |=
425 (pic->picture_parameter.pic_fields.allow_high_precision_mv <<
426 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
427 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
428
429 result.frame_header_flags |=
430 (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode <<
431 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
432 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
433
434 result.frame_header_flags |=
435 (pic->picture_parameter.pic_fields.refresh_frame_context <<
436 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
437 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
438
439 result.frame_header_flags |=
440 (pic->picture_parameter.pic_fields.segmentation_enabled <<
441 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
442 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
443
444 result.frame_header_flags |=
445 (pic->picture_parameter.pic_fields.segmentation_update_map <<
446 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
447 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
448
449 result.frame_header_flags |=
450 (pic->picture_parameter.pic_fields.segmentation_temporal_update <<
451 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
452 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
453
454 result.frame_header_flags |=
455 (pic->picture_parameter.mode_ref_delta_enabled <<
456 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
457 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
458
459 result.frame_header_flags |=
460 (pic->picture_parameter.mode_ref_delta_update <<
461 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
462 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
463
464 result.frame_header_flags |= ((dec->show_frame &&
465 !pic->picture_parameter.pic_fields.error_resilient_mode)
466 << RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
467 RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
468 dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
469
470 result.interp_filter = pic->picture_parameter.pic_fields.mcomp_filter_type;
471
472 result.frame_context_idx = pic->picture_parameter.pic_fields.frame_context_idx;
473 result.reset_frame_context = pic->picture_parameter.pic_fields.reset_frame_context;
474
475 result.filter_level = pic->picture_parameter.filter_level;
476 result.sharpness_level = pic->picture_parameter.sharpness_level;
477
478 for (i = 0; i < 8; ++i)
479 memcpy(result.lf_adj_level[i], pic->slice_parameter.seg_param[i].filter_level, 4 * 2);
480
481 if (pic->picture_parameter.pic_fields.lossless_flag) {
482 result.base_qindex = 0;
483 result.y_dc_delta_q = 0;
484 result.uv_ac_delta_q = 0;
485 result.uv_dc_delta_q = 0;
486 } else {
487 result.base_qindex = pic->picture_parameter.base_qindex;
488 result.y_dc_delta_q = pic->picture_parameter.y_dc_delta_q;
489 result.uv_ac_delta_q = pic->picture_parameter.uv_ac_delta_q;
490 result.uv_dc_delta_q = pic->picture_parameter.uv_dc_delta_q;
491 }
492
493 result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
494 result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
495 result.chroma_format = 1;
496 result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8
497 = (pic->picture_parameter.bit_depth - 8);
498
499 result.vp9_frame_size = align(dec->bs_size, 128);
500 result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
501 result.compressed_header_size = pic->picture_parameter.first_partition_size;
502
503 assert(dec->base.max_references + 1 <= 16);
504
505 for (i = 0 ; i < 16 ; ++i) {
506 if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
507 result.curr_pic_idx =
508 (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
509 break;
510 } else if (!dec->render_pic_list[i]) {
511 dec->render_pic_list[i] = target;
512 result.curr_pic_idx = dec->ref_idx;
513 vl_video_buffer_set_associated_data(target, &dec->base,
514 (void *)(uintptr_t)dec->ref_idx++,
515 &radeon_dec_destroy_associated_data);
516 break;
517 }
518 }
519
520 for (i = 0 ; i < 8; i++) {
521 result.ref_frame_map[i] = (pic->ref[i]) ?
522 (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) :
523 0x7f;
524 }
525
526 result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
527 result.ref_frame_sign_bias[0] = pic->picture_parameter.pic_fields.last_ref_frame_sign_bias;
528 result.frame_refs[1] = result.ref_frame_map[pic->picture_parameter.pic_fields.golden_ref_frame];
529 result.ref_frame_sign_bias[1] = pic->picture_parameter.pic_fields.golden_ref_frame_sign_bias;
530 result.frame_refs[2] = result.ref_frame_map[pic->picture_parameter.pic_fields.alt_ref_frame];
531 result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
532
533 if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
534 if (target->buffer_format == PIPE_FORMAT_P010 ||
535 target->buffer_format == PIPE_FORMAT_P016) {
536 result.p010_mode = 1;
537 result.msb_mode = 1;
538 } else {
539 result.p010_mode = 0;
540 result.luma_10to8 = 1;
541 result.chroma_10to8 = 1;
542 }
543 }
544
545 return result;
546 }
547
548 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
549 {
550 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
551 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
552
553 unsigned max_references = dec->base.max_references + 1;
554
555 if (dec->base.width * dec->base.height >= 4096*2000)
556 max_references = MAX2(max_references, 8);
557 else
558 max_references = MAX2(max_references, 17);
559
560 width = align (width, 16);
561 height = align (height, 16);
562 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
563 }
564
565 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
566 {
567 unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
568 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
569 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
570
571 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
572 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
573 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 ||
574 pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
575
576 unsigned max_references = dec->base.max_references + 1;
577
578 if (dec->base.width * dec->base.height >= 4096*2000)
579 max_references = MAX2(max_references, 8);
580 else
581 max_references = MAX2(max_references, 17);
582
583 log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
584 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
585
586 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
587 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
588
589 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
590 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
591 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
592
593 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
594 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
595
596 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
597 }
598
599 static rvcn_dec_message_vc1_t get_vc1_msg(struct pipe_vc1_picture_desc *pic)
600 {
601 rvcn_dec_message_vc1_t result;
602
603 memset(&result, 0, sizeof(result));
604 switch(pic->base.profile) {
605 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
606 result.profile = RDECODE_VC1_PROFILE_SIMPLE;
607 result.level = 1;
608 break;
609
610 case PIPE_VIDEO_PROFILE_VC1_MAIN:
611 result.profile = RDECODE_VC1_PROFILE_MAIN;
612 result.level = 2;
613 break;
614
615 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
616 result.profile = RDECODE_VC1_PROFILE_ADVANCED;
617 result.level = 4;
618 break;
619
620 default:
621 assert(0);
622 }
623
624 result.sps_info_flags |= pic->postprocflag << 7;
625 result.sps_info_flags |= pic->pulldown << 6;
626 result.sps_info_flags |= pic->interlace << 5;
627 result.sps_info_flags |= pic->tfcntrflag << 4;
628 result.sps_info_flags |= pic->finterpflag << 3;
629 result.sps_info_flags |= pic->psf << 1;
630
631 result.pps_info_flags |= pic->range_mapy_flag << 31;
632 result.pps_info_flags |= pic->range_mapy << 28;
633 result.pps_info_flags |= pic->range_mapuv_flag << 27;
634 result.pps_info_flags |= pic->range_mapuv << 24;
635 result.pps_info_flags |= pic->multires << 21;
636 result.pps_info_flags |= pic->maxbframes << 16;
637 result.pps_info_flags |= pic->overlap << 11;
638 result.pps_info_flags |= pic->quantizer << 9;
639 result.pps_info_flags |= pic->panscan_flag << 7;
640 result.pps_info_flags |= pic->refdist_flag << 6;
641 result.pps_info_flags |= pic->vstransform << 0;
642
643 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
644 result.pps_info_flags |= pic->syncmarker << 20;
645 result.pps_info_flags |= pic->rangered << 19;
646 result.pps_info_flags |= pic->loopfilter << 5;
647 result.pps_info_flags |= pic->fastuvmc << 4;
648 result.pps_info_flags |= pic->extended_mv << 3;
649 result.pps_info_flags |= pic->extended_dmv << 8;
650 result.pps_info_flags |= pic->dquant << 1;
651 }
652
653 result.chroma_format = 1;
654
655 return result;
656 }
657
658 static uint32_t get_ref_pic_idx(struct radeon_decoder *dec, struct pipe_video_buffer *ref)
659 {
660 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
661 uint32_t max = MAX2(dec->frame_number, 1) - 1;
662 uintptr_t frame;
663
664 /* seems to be the most sane fallback */
665 if (!ref)
666 return max;
667
668 /* get the frame number from the associated data */
669 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
670
671 /* limit the frame number to a valid range */
672 return MAX2(MIN2(frame, max), min);
673 }
674
675 static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct radeon_decoder *dec,
676 struct pipe_mpeg12_picture_desc *pic)
677 {
678 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
679 rvcn_dec_message_mpeg2_vld_t result;
680 unsigned i;
681
682 memset(&result, 0, sizeof(result));
683 result.decoded_pic_idx = dec->frame_number;
684
685 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
686 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
687
688 if(pic->intra_matrix) {
689 result.load_intra_quantiser_matrix = 1;
690 for (i = 0; i < 64; ++i) {
691 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
692 }
693 }
694 if(pic->non_intra_matrix) {
695 result.load_nonintra_quantiser_matrix = 1;
696 for (i = 0; i < 64; ++i) {
697 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
698 }
699 }
700
701 result.profile_and_level_indication = 0;
702 result.chroma_format = 0x1;
703
704 result.picture_coding_type = pic->picture_coding_type;
705 result.f_code[0][0] = pic->f_code[0][0] + 1;
706 result.f_code[0][1] = pic->f_code[0][1] + 1;
707 result.f_code[1][0] = pic->f_code[1][0] + 1;
708 result.f_code[1][1] = pic->f_code[1][1] + 1;
709 result.intra_dc_precision = pic->intra_dc_precision;
710 result.pic_structure = pic->picture_structure;
711 result.top_field_first = pic->top_field_first;
712 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
713 result.concealment_motion_vectors = pic->concealment_motion_vectors;
714 result.q_scale_type = pic->q_scale_type;
715 result.intra_vlc_format = pic->intra_vlc_format;
716 result.alternate_scan = pic->alternate_scan;
717
718 return result;
719 }
720
721 static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec,
722 struct pipe_mpeg4_picture_desc *pic)
723 {
724 rvcn_dec_message_mpeg4_asp_vld_t result;
725 unsigned i;
726
727 memset(&result, 0, sizeof(result));
728 result.decoded_pic_idx = dec->frame_number;
729
730 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
731 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
732
733 result.variant_type = 0;
734 result.profile_and_level_indication = 0xF0;
735
736 result.video_object_layer_verid = 0x5;
737 result.video_object_layer_shape = 0x0;
738
739 result.video_object_layer_width = dec->base.width;
740 result.video_object_layer_height = dec->base.height;
741
742 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
743
744 result.short_video_header = pic->short_video_header;
745 result.interlaced = pic->interlaced;
746 result.load_intra_quant_mat = 1;
747 result.load_nonintra_quant_mat = 1;
748 result.quarter_sample = pic->quarter_sample;
749 result.complexity_estimation_disable = 1;
750 result.resync_marker_disable = pic->resync_marker_disable;
751 result.newpred_enable = 0;
752 result.reduced_resolution_vop_enable = 0;
753
754 result.quant_type = pic->quant_type;
755
756 for (i = 0; i < 64; ++i) {
757 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
758 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
759 }
760
761 return result;
762 }
763
764 static void rvcn_dec_message_create(struct radeon_decoder *dec)
765 {
766 rvcn_dec_message_header_t *header = dec->msg;
767 rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
768 unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
769
770 memset(dec->msg, 0, sizes);
771 header->header_size = sizeof(rvcn_dec_message_header_t);
772 header->total_size = sizes;
773 header->num_buffers = 1;
774 header->msg_type = RDECODE_MSG_CREATE;
775 header->stream_handle = dec->stream_handle;
776 header->status_report_feedback_number = 0;
777
778 header->index[0].message_id = RDECODE_MESSAGE_CREATE;
779 header->index[0].offset = sizeof(rvcn_dec_message_header_t);
780 header->index[0].size = sizeof(rvcn_dec_message_create_t);
781 header->index[0].filled = 0;
782
783 create->stream_type = dec->stream_type;
784 create->session_flags = 0;
785 create->width_in_samples = dec->base.width;
786 create->height_in_samples = dec->base.height;
787 }
788
789 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
790 struct pipe_video_buffer *target,
791 struct pipe_picture_desc *picture)
792 {
793 struct si_texture *luma = (struct si_texture *)
794 ((struct vl_video_buffer *)target)->resources[0];
795 struct si_texture *chroma = (struct si_texture *)
796 ((struct vl_video_buffer *)target)->resources[1];
797 rvcn_dec_message_header_t *header;
798 rvcn_dec_message_index_t *index;
799 rvcn_dec_message_decode_t *decode;
800 unsigned sizes = 0, offset_decode, offset_codec;
801 void *codec;
802
803 header = dec->msg;
804 sizes += sizeof(rvcn_dec_message_header_t);
805 index = (void*)header + sizeof(rvcn_dec_message_header_t);
806 sizes += sizeof(rvcn_dec_message_index_t);
807 offset_decode = sizes;
808 decode = (void*)index + sizeof(rvcn_dec_message_index_t);
809 sizes += sizeof(rvcn_dec_message_decode_t);
810 offset_codec = sizes;
811 codec = (void*)decode + sizeof(rvcn_dec_message_decode_t);
812
813 memset(dec->msg, 0, sizes);
814 header->header_size = sizeof(rvcn_dec_message_header_t);
815 header->total_size = sizes;
816 header->num_buffers = 2;
817 header->msg_type = RDECODE_MSG_DECODE;
818 header->stream_handle = dec->stream_handle;
819 header->status_report_feedback_number = dec->frame_number;
820
821 header->index[0].message_id = RDECODE_MESSAGE_DECODE;
822 header->index[0].offset = offset_decode;
823 header->index[0].size = sizeof(rvcn_dec_message_decode_t);
824 header->index[0].filled = 0;
825
826 index->offset = offset_codec;
827 index->size = sizeof(rvcn_dec_message_avc_t);
828 index->filled = 0;
829
830 decode->stream_type = dec->stream_type;
831 decode->decode_flags = 0x1;
832 decode->width_in_samples = dec->base.width;
833 decode->height_in_samples = dec->base.height;
834
835 decode->bsd_size = align(dec->bs_size, 128);
836 decode->dpb_size = dec->dpb.res->buf->size;
837 decode->dt_size =
838 si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
839 si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
840
841 decode->sct_size = 0;
842 decode->sc_coeff_size = 0;
843
844 decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
845 decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR &&
846 dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
847 align(dec->base.width, 64) :
848 align(dec->base.width, 32) ;
849 decode->db_surf_tile_config = 0;
850
851 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
852 decode->dt_uv_pitch = decode->dt_pitch / 2;
853
854 decode->dt_tiling_mode = 0;
855 decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
856 decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
857 decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
858 decode->dt_surf_tile_config = 0;
859 decode->dt_uv_surf_tile_config = 0;
860
861 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
862 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
863 if (decode->dt_field_mode) {
864 decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset +
865 luma->surface.u.gfx9.surf_slice_size;
866 decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset +
867 chroma->surface.u.gfx9.surf_slice_size;
868 } else {
869 decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
870 decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
871 }
872
873 switch (u_reduce_video_profile(picture->profile)) {
874 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
875 rvcn_dec_message_avc_t avc =
876 get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
877 memcpy(codec, (void*)&avc, sizeof(rvcn_dec_message_avc_t));
878 index->message_id = RDECODE_MESSAGE_AVC;
879 break;
880 }
881 case PIPE_VIDEO_FORMAT_HEVC: {
882 rvcn_dec_message_hevc_t hevc =
883 get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
884
885 memcpy(codec, (void*)&hevc, sizeof(rvcn_dec_message_hevc_t));
886 index->message_id = RDECODE_MESSAGE_HEVC;
887 if (dec->ctx.res == NULL) {
888 unsigned ctx_size;
889 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
890 ctx_size = calc_ctx_size_h265_main10(dec,
891 (struct pipe_h265_picture_desc*)picture);
892 else
893 ctx_size = calc_ctx_size_h265_main(dec);
894 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
895 RVID_ERR("Can't allocated context buffer.\n");
896 si_vid_clear_buffer(dec->base.context, &dec->ctx);
897 }
898 break;
899 }
900 case PIPE_VIDEO_FORMAT_VC1: {
901 rvcn_dec_message_vc1_t vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
902
903 memcpy(codec, (void*)&vc1, sizeof(rvcn_dec_message_vc1_t));
904 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
905 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
906 decode->width_in_samples = align(decode->width_in_samples, 16) / 16;
907 decode->height_in_samples = align(decode->height_in_samples, 16) / 16;
908 }
909 index->message_id = RDECODE_MESSAGE_VC1;
910 break;
911
912 }
913 case PIPE_VIDEO_FORMAT_MPEG12: {
914 rvcn_dec_message_mpeg2_vld_t mpeg2 =
915 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
916
917 memcpy(codec, (void*)&mpeg2, sizeof(rvcn_dec_message_mpeg2_vld_t));
918 index->message_id = RDECODE_MESSAGE_MPEG2_VLD;
919 break;
920 }
921 case PIPE_VIDEO_FORMAT_MPEG4: {
922 rvcn_dec_message_mpeg4_asp_vld_t mpeg4 =
923 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
924
925 memcpy(codec, (void*)&mpeg4, sizeof(rvcn_dec_message_mpeg4_asp_vld_t));
926 index->message_id = RDECODE_MESSAGE_MPEG4_ASP_VLD;
927 break;
928 }
929 case PIPE_VIDEO_FORMAT_VP9: {
930 rvcn_dec_message_vp9_t vp9 =
931 get_vp9_msg(dec, target, (struct pipe_vp9_picture_desc*)picture);
932
933 memcpy(codec, (void*)&vp9, sizeof(rvcn_dec_message_vp9_t));
934 index->message_id = RDECODE_MESSAGE_VP9;
935
936 if (dec->ctx.res == NULL) {
937 unsigned ctx_size;
938 uint8_t *ptr;
939
940 /* default probability + probability data */
941 ctx_size = 2304 * 5;
942
943 if (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) {
944 /* SRE collocated context data */
945 ctx_size += 32 * 2 * 128 * 68;
946 /* SMP collocated context data */
947 ctx_size += 9 * 64 * 2 * 128 * 68;
948 /* SDB left tile pixel */
949 ctx_size += 8 * 2 * 2 * 8192;
950 } else {
951 ctx_size += 32 * 2 * 64 * 64;
952 ctx_size += 9 * 64 * 2 * 64 * 64;
953 ctx_size += 8 * 2 * 4096;
954 }
955
956 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
957 ctx_size += 8 * 2 * 4096;
958
959 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
960 RVID_ERR("Can't allocated context buffer.\n");
961 si_vid_clear_buffer(dec->base.context, &dec->ctx);
962
963 /* ctx needs probs table */
964 ptr = dec->ws->buffer_map(
965 dec->ctx.res->buf, dec->cs,
966 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
967 fill_probs_table(ptr);
968 dec->ws->buffer_unmap(dec->ctx.res->buf);
969 }
970 break;
971 }
972 default:
973 assert(0);
974 return NULL;
975 }
976
977 if (dec->ctx.res)
978 decode->hw_ctxt_size = dec->ctx.res->buf->size;
979
980 return luma->buffer.buf;
981 }
982
983 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
984 {
985 rvcn_dec_message_header_t *header = dec->msg;
986
987 memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
988 header->header_size = sizeof(rvcn_dec_message_header_t);
989 header->total_size = sizeof(rvcn_dec_message_header_t) -
990 sizeof(rvcn_dec_message_index_t);
991 header->num_buffers = 0;
992 header->msg_type = RDECODE_MSG_DESTROY;
993 header->stream_handle = dec->stream_handle;
994 header->status_report_feedback_number = 0;
995 }
996
997 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
998 {
999 rvcn_dec_feedback_header_t *header = (void*)dec->fb;
1000
1001 header->header_size = sizeof(rvcn_dec_feedback_header_t);
1002 header->total_size = sizeof(rvcn_dec_feedback_header_t);
1003 header->num_buffers = 0;
1004 }
1005
1006 /* flush IB to the hardware */
1007 static int flush(struct radeon_decoder *dec, unsigned flags)
1008 {
1009 return dec->ws->cs_flush(dec->cs, flags, NULL);
1010 }
1011
1012 /* add a new set register command to the IB */
1013 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
1014 {
1015 radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
1016 radeon_emit(dec->cs, val);
1017 }
1018
1019 /* send a command to the VCPU through the GPCOM registers */
1020 static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
1021 struct pb_buffer* buf, uint32_t off,
1022 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
1023 {
1024 uint64_t addr;
1025
1026 dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
1027 domain, 0);
1028 addr = dec->ws->buffer_get_virtual_address(buf);
1029 addr = addr + off;
1030
1031 set_reg(dec, dec->reg.data0, addr);
1032 set_reg(dec, dec->reg.data1, addr >> 32);
1033 set_reg(dec, dec->reg.cmd, cmd << 1);
1034 }
1035
1036 /* do the codec needs an IT buffer ?*/
1037 static bool have_it(struct radeon_decoder *dec)
1038 {
1039 return dec->stream_type == RDECODE_CODEC_H264_PERF ||
1040 dec->stream_type == RDECODE_CODEC_H265;
1041 }
1042
1043 /* do the codec needs an probs buffer? */
1044 static bool have_probs(struct radeon_decoder *dec)
1045 {
1046 return dec->stream_type == RDECODE_CODEC_VP9;
1047 }
1048
1049 /* map the next available message/feedback/itscaling buffer */
1050 static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
1051 {
1052 struct rvid_buffer* buf;
1053 uint8_t *ptr;
1054
1055 /* grab the current message/feedback buffer */
1056 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1057
1058 /* and map it for CPU access */
1059 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1060 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1061
1062 /* calc buffer offsets */
1063 dec->msg = ptr;
1064
1065 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1066 if (have_it(dec))
1067 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1068 else if (have_probs(dec))
1069 dec->probs = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1070 }
1071
1072 /* unmap and send a message command to the VCPU */
1073 static void send_msg_buf(struct radeon_decoder *dec)
1074 {
1075 struct rvid_buffer* buf;
1076
1077 /* ignore the request if message/feedback buffer isn't mapped */
1078 if (!dec->msg || !dec->fb)
1079 return;
1080
1081 /* grab the current message buffer */
1082 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1083
1084 /* unmap the buffer */
1085 dec->ws->buffer_unmap(buf->res->buf);
1086 dec->msg = NULL;
1087 dec->fb = NULL;
1088 dec->it = NULL;
1089 dec->probs = NULL;
1090
1091 if (dec->sessionctx.res)
1092 send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
1093 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
1094 RADEON_DOMAIN_VRAM);
1095
1096 /* and send it to the hardware */
1097 send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
1098 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1099 }
1100
1101 /* cycle to the next set of buffers */
1102 static void next_buffer(struct radeon_decoder *dec)
1103 {
1104 ++dec->cur_buffer;
1105 dec->cur_buffer %= NUM_BUFFERS;
1106 }
1107
1108 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
1109 {
1110 unsigned width_in_mb, height_in_mb, ctx_size;
1111 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1112 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1113
1114 unsigned max_references = dec->base.max_references + 1;
1115
1116 // picture width & height in 16 pixel units
1117 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1118 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1119
1120 unsigned fs_in_mb = width_in_mb * height_in_mb;
1121 unsigned num_dpb_buffer;
1122 switch(dec->base.level) {
1123 case 30:
1124 num_dpb_buffer = 8100 / fs_in_mb;
1125 break;
1126 case 31:
1127 num_dpb_buffer = 18000 / fs_in_mb;
1128 break;
1129 case 32:
1130 num_dpb_buffer = 20480 / fs_in_mb;
1131 break;
1132 case 41:
1133 num_dpb_buffer = 32768 / fs_in_mb;
1134 break;
1135 case 42:
1136 num_dpb_buffer = 34816 / fs_in_mb;
1137 break;
1138 case 50:
1139 num_dpb_buffer = 110400 / fs_in_mb;
1140 break;
1141 case 51:
1142 num_dpb_buffer = 184320 / fs_in_mb;
1143 break;
1144 default:
1145 num_dpb_buffer = 184320 / fs_in_mb;
1146 break;
1147 }
1148 num_dpb_buffer++;
1149 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1150 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
1151
1152 return ctx_size;
1153 }
1154
1155 /* calculate size of reference picture buffer */
1156 static unsigned calc_dpb_size(struct radeon_decoder *dec)
1157 {
1158 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
1159
1160 // always align them to MB size for dpb calculation
1161 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1162 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1163
1164 // always one more for currently decoded picture
1165 unsigned max_references = dec->base.max_references + 1;
1166
1167 // aligned size of a single frame
1168 image_size = align(width, 32) * height;
1169 image_size += image_size / 2;
1170 image_size = align(image_size, 1024);
1171
1172 // picture width & height in 16 pixel units
1173 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1174 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1175
1176 switch (u_reduce_video_profile(dec->base.profile)) {
1177 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1178 unsigned fs_in_mb = width_in_mb * height_in_mb;
1179 unsigned num_dpb_buffer;
1180
1181 switch(dec->base.level) {
1182 case 30:
1183 num_dpb_buffer = 8100 / fs_in_mb;
1184 break;
1185 case 31:
1186 num_dpb_buffer = 18000 / fs_in_mb;
1187 break;
1188 case 32:
1189 num_dpb_buffer = 20480 / fs_in_mb;
1190 break;
1191 case 41:
1192 num_dpb_buffer = 32768 / fs_in_mb;
1193 break;
1194 case 42:
1195 num_dpb_buffer = 34816 / fs_in_mb;
1196 break;
1197 case 50:
1198 num_dpb_buffer = 110400 / fs_in_mb;
1199 break;
1200 case 51:
1201 num_dpb_buffer = 184320 / fs_in_mb;
1202 break;
1203 default:
1204 num_dpb_buffer = 184320 / fs_in_mb;
1205 break;
1206 }
1207 num_dpb_buffer++;
1208 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1209 dpb_size = image_size * max_references;
1210 break;
1211 }
1212
1213 case PIPE_VIDEO_FORMAT_HEVC:
1214 if (dec->base.width * dec->base.height >= 4096*2000)
1215 max_references = MAX2(max_references, 8);
1216 else
1217 max_references = MAX2(max_references, 17);
1218
1219 width = align (width, 16);
1220 height = align (height, 16);
1221 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1222 dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
1223 else
1224 dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
1225 break;
1226
1227 case PIPE_VIDEO_FORMAT_VC1:
1228 // the firmware seems to allways assume a minimum of ref frames
1229 max_references = MAX2(NUM_VC1_REFS, max_references);
1230
1231 // reference picture buffer
1232 dpb_size = image_size * max_references;
1233
1234 // CONTEXT_BUFFER
1235 dpb_size += width_in_mb * height_in_mb * 128;
1236
1237 // IT surface buffer
1238 dpb_size += width_in_mb * 64;
1239
1240 // DB surface buffer
1241 dpb_size += width_in_mb * 128;
1242
1243 // BP
1244 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
1245 break;
1246
1247 case PIPE_VIDEO_FORMAT_MPEG12:
1248 // reference picture buffer, must be big enough for all frames
1249 dpb_size = image_size * NUM_MPEG2_REFS;
1250 break;
1251
1252 case PIPE_VIDEO_FORMAT_MPEG4:
1253 // reference picture buffer
1254 dpb_size = image_size * max_references;
1255
1256 // CM
1257 dpb_size += width_in_mb * height_in_mb * 64;
1258
1259 // IT surface buffer
1260 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
1261
1262 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
1263 break;
1264
1265 case PIPE_VIDEO_FORMAT_VP9:
1266 max_references = MAX2(max_references, 9);
1267
1268 dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) ?
1269 (8192 * 4320 * 3 / 2) * max_references :
1270 (4096 * 3000 * 3 / 2) * max_references;
1271
1272 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1273 dpb_size *= (3 / 2);
1274 break;
1275
1276 case PIPE_VIDEO_FORMAT_JPEG:
1277 dpb_size = 0;
1278 break;
1279
1280 default:
1281 // something is missing here
1282 assert(0);
1283
1284 // at least use a sane default value
1285 dpb_size = 32 * 1024 * 1024;
1286 break;
1287 }
1288 return dpb_size;
1289 }
1290
1291 /**
1292 * destroy this video decoder
1293 */
1294 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
1295 {
1296 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1297 unsigned i;
1298
1299 assert(decoder);
1300
1301 map_msg_fb_it_probs_buf(dec);
1302 rvcn_dec_message_destroy(dec);
1303 send_msg_buf(dec);
1304
1305 flush(dec, 0);
1306
1307 dec->ws->cs_destroy(dec->cs);
1308
1309 for (i = 0; i < NUM_BUFFERS; ++i) {
1310 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1311 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1312 }
1313
1314 si_vid_destroy_buffer(&dec->dpb);
1315 si_vid_destroy_buffer(&dec->ctx);
1316 si_vid_destroy_buffer(&dec->sessionctx);
1317
1318 FREE(dec);
1319 }
1320
1321 /**
1322 * start decoding of a new frame
1323 */
1324 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
1325 struct pipe_video_buffer *target,
1326 struct pipe_picture_desc *picture)
1327 {
1328 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1329 uintptr_t frame;
1330
1331 assert(decoder);
1332
1333 frame = ++dec->frame_number;
1334 if (dec->stream_type != RDECODE_CODEC_VP9)
1335 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1336 &radeon_dec_destroy_associated_data);
1337
1338 dec->bs_size = 0;
1339 dec->bs_ptr = dec->ws->buffer_map(
1340 dec->bs_buffers[dec->cur_buffer].res->buf,
1341 dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1342 }
1343
1344 /**
1345 * decode a macroblock
1346 */
1347 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
1348 struct pipe_video_buffer *target,
1349 struct pipe_picture_desc *picture,
1350 const struct pipe_macroblock *macroblocks,
1351 unsigned num_macroblocks)
1352 {
1353 /* not supported (yet) */
1354 assert(0);
1355 }
1356
1357 /**
1358 * decode a bitstream
1359 */
1360 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
1361 struct pipe_video_buffer *target,
1362 struct pipe_picture_desc *picture,
1363 unsigned num_buffers,
1364 const void * const *buffers,
1365 const unsigned *sizes)
1366 {
1367 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1368 unsigned i;
1369
1370 assert(decoder);
1371
1372 if (!dec->bs_ptr)
1373 return;
1374
1375 for (i = 0; i < num_buffers; ++i) {
1376 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1377 unsigned new_size = dec->bs_size + sizes[i];
1378
1379 if (new_size > buf->res->buf->size) {
1380 dec->ws->buffer_unmap(buf->res->buf);
1381 if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1382 RVID_ERR("Can't resize bitstream buffer!");
1383 return;
1384 }
1385
1386 dec->bs_ptr = dec->ws->buffer_map(
1387 buf->res->buf, dec->cs,
1388 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1389 if (!dec->bs_ptr)
1390 return;
1391
1392 dec->bs_ptr += dec->bs_size;
1393 }
1394
1395 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1396 dec->bs_size += sizes[i];
1397 dec->bs_ptr += sizes[i];
1398 }
1399 }
1400
1401 /**
1402 * send cmd for vcn dec
1403 */
1404 void send_cmd_dec(struct radeon_decoder *dec,
1405 struct pipe_video_buffer *target,
1406 struct pipe_picture_desc *picture)
1407 {
1408 struct pb_buffer *dt;
1409 struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
1410
1411 msg_fb_it_probs_buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1412 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1413
1414 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
1415 dec->ws->buffer_unmap(bs_buf->res->buf);
1416
1417 map_msg_fb_it_probs_buf(dec);
1418 dt = rvcn_dec_message_decode(dec, target, picture);
1419 rvcn_dec_message_feedback(dec);
1420 send_msg_buf(dec);
1421
1422 send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1423 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1424 if (dec->ctx.res)
1425 send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1426 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1427 send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1428 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1429 send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
1430 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1431 send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf,
1432 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1433 if (have_it(dec))
1434 send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
1435 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1436 else if (have_probs(dec))
1437 send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, msg_fb_it_probs_buf->res->buf,
1438 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1439 set_reg(dec, dec->reg.cntl, 1);
1440 }
1441
1442 /**
1443 * end decoding of the current frame
1444 */
1445 static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
1446 struct pipe_video_buffer *target,
1447 struct pipe_picture_desc *picture)
1448 {
1449 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1450
1451 assert(decoder);
1452
1453 if (!dec->bs_ptr)
1454 return;
1455
1456 dec->send_cmd(dec, target, picture);
1457 flush(dec, PIPE_FLUSH_ASYNC);
1458 next_buffer(dec);
1459 }
1460
1461 /**
1462 * flush any outstanding command buffers to the hardware
1463 */
1464 static void radeon_dec_flush(struct pipe_video_codec *decoder)
1465 {
1466 }
1467
1468 /**
1469 * create and HW decoder
1470 */
1471 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
1472 const struct pipe_video_codec *templ)
1473 {
1474 struct si_context *sctx = (struct si_context*)context;
1475 struct radeon_winsys *ws = sctx->ws;
1476 unsigned width = templ->width, height = templ->height;
1477 unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
1478 struct radeon_decoder *dec;
1479 int r, i;
1480
1481 switch(u_reduce_video_profile(templ->profile)) {
1482 case PIPE_VIDEO_FORMAT_MPEG12:
1483 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1484 return vl_create_mpeg12_decoder(context, templ);
1485 stream_type = RDECODE_CODEC_MPEG2_VLD;
1486 break;
1487 case PIPE_VIDEO_FORMAT_MPEG4:
1488 width = align(width, VL_MACROBLOCK_WIDTH);
1489 height = align(height, VL_MACROBLOCK_HEIGHT);
1490 stream_type = RDECODE_CODEC_MPEG4;
1491 break;
1492 case PIPE_VIDEO_FORMAT_VC1:
1493 stream_type = RDECODE_CODEC_VC1;
1494 break;
1495 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1496 width = align(width, VL_MACROBLOCK_WIDTH);
1497 height = align(height, VL_MACROBLOCK_HEIGHT);
1498 stream_type = RDECODE_CODEC_H264_PERF;
1499 break;
1500 case PIPE_VIDEO_FORMAT_HEVC:
1501 stream_type = RDECODE_CODEC_H265;
1502 break;
1503 case PIPE_VIDEO_FORMAT_VP9:
1504 stream_type = RDECODE_CODEC_VP9;
1505 break;
1506 case PIPE_VIDEO_FORMAT_JPEG:
1507 stream_type = RDECODE_CODEC_JPEG;
1508 ring = RING_VCN_JPEG;
1509 break;
1510 default:
1511 assert(0);
1512 break;
1513 }
1514
1515 dec = CALLOC_STRUCT(radeon_decoder);
1516
1517 if (!dec)
1518 return NULL;
1519
1520 dec->base = *templ;
1521 dec->base.context = context;
1522 dec->base.width = width;
1523 dec->base.height = height;
1524
1525 dec->base.destroy = radeon_dec_destroy;
1526 dec->base.begin_frame = radeon_dec_begin_frame;
1527 dec->base.decode_macroblock = radeon_dec_decode_macroblock;
1528 dec->base.decode_bitstream = radeon_dec_decode_bitstream;
1529 dec->base.end_frame = radeon_dec_end_frame;
1530 dec->base.flush = radeon_dec_flush;
1531
1532 dec->stream_type = stream_type;
1533 dec->stream_handle = si_vid_alloc_stream_handle();
1534 dec->screen = context->screen;
1535 dec->ws = ws;
1536 dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL, false);
1537 if (!dec->cs) {
1538 RVID_ERR("Can't get command submission context.\n");
1539 goto error;
1540 }
1541
1542 for (i = 0; i < 16; i++)
1543 dec->render_pic_list[i] = NULL;
1544 bs_buf_size = width * height * (512 / (16 * 16));
1545 for (i = 0; i < NUM_BUFFERS; ++i) {
1546 unsigned msg_fb_it_probs_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1547 if (have_it(dec))
1548 msg_fb_it_probs_size += IT_SCALING_TABLE_SIZE;
1549 else if (have_probs(dec))
1550 msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
1551 /* use vram to improve performance, workaround an unknown bug */
1552 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i],
1553 msg_fb_it_probs_size, PIPE_USAGE_DEFAULT)) {
1554 RVID_ERR("Can't allocated message buffers.\n");
1555 goto error;
1556 }
1557
1558 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
1559 bs_buf_size, PIPE_USAGE_STAGING)) {
1560 RVID_ERR("Can't allocated bitstream buffers.\n");
1561 goto error;
1562 }
1563
1564 si_vid_clear_buffer(context, &dec->msg_fb_it_probs_buffers[i]);
1565 si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1566
1567 if (have_probs(dec)) {
1568 struct rvid_buffer* buf;
1569 void *ptr;
1570
1571 buf = &dec->msg_fb_it_probs_buffers[i];
1572 ptr = dec->ws->buffer_map(
1573 buf->res->buf, dec->cs,
1574 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1575 ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1576 fill_probs_table(ptr);
1577 dec->ws->buffer_unmap(buf->res->buf);
1578 }
1579 }
1580
1581 dpb_size = calc_dpb_size(dec);
1582 if (dpb_size) {
1583 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1584 RVID_ERR("Can't allocated dpb.\n");
1585 goto error;
1586 }
1587 si_vid_clear_buffer(context, &dec->dpb);
1588 }
1589
1590 if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
1591 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1592 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1593 RVID_ERR("Can't allocated context buffer.\n");
1594 goto error;
1595 }
1596 si_vid_clear_buffer(context, &dec->ctx);
1597 }
1598
1599 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
1600 RDECODE_SESSION_CONTEXT_SIZE,
1601 PIPE_USAGE_DEFAULT)) {
1602 RVID_ERR("Can't allocated session ctx.\n");
1603 goto error;
1604 }
1605 si_vid_clear_buffer(context, &dec->sessionctx);
1606
1607 if (sctx->family == CHIP_ARCTURUS) {
1608 dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
1609 dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
1610 dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
1611 dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
1612 dec->jpg.direct_reg = true;
1613 } else if (sctx->family >= CHIP_NAVI10 || sctx->family == CHIP_RENOIR) {
1614 dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
1615 dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
1616 dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
1617 dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
1618 dec->jpg.direct_reg = true;
1619 } else {
1620 dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
1621 dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
1622 dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
1623 dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
1624 dec->jpg.direct_reg = false;
1625 }
1626
1627 map_msg_fb_it_probs_buf(dec);
1628 rvcn_dec_message_create(dec);
1629 send_msg_buf(dec);
1630 r = flush(dec, 0);
1631 if (r)
1632 goto error;
1633
1634 next_buffer(dec);
1635
1636 if (stream_type == RDECODE_CODEC_JPEG)
1637 dec->send_cmd = send_cmd_jpeg;
1638 else
1639 dec->send_cmd = send_cmd_dec;
1640
1641 return &dec->base;
1642
1643 error:
1644 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1645
1646 for (i = 0; i < NUM_BUFFERS; ++i) {
1647 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1648 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1649 }
1650
1651 si_vid_destroy_buffer(&dec->dpb);
1652 si_vid_destroy_buffer(&dec->ctx);
1653 si_vid_destroy_buffer(&dec->sessionctx);
1654
1655 FREE(dec);
1656
1657 return NULL;
1658 }