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radeon/vcn: add defines for vcn 2.0 jpeg
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.h
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef _RADEON_VCN_DEC_H
29 #define _RADEON_VCN_DEC_H
30
31 #define RDECODE_PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
32 #define RDECODE_PKT_TYPE_G(x) (((x) >> 30) & 0x3)
33 #define RDECODE_PKT_TYPE_C 0x3FFFFFFF
34 #define RDECODE_PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
35 #define RDECODE_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
36 #define RDECODE_PKT_COUNT_C 0xC000FFFF
37 #define RDECODE_PKT0_BASE_INDEX_S(x) (((unsigned)(x) & 0xFFFF) << 0)
38 #define RDECODE_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
39 #define RDECODE_PKT0_BASE_INDEX_C 0xFFFF0000
40 #define RDECODE_PKT0(index, count) (RDECODE_PKT_TYPE_S(0) | \
41 RDECODE_PKT0_BASE_INDEX_S(index) | \
42 RDECODE_PKT_COUNT_S(count))
43
44 #define RDECODE_PKT2() (RDECODE_PKT_TYPE_S(2))
45
46 #define RDECODE_PKT_REG_J(x) ((unsigned)(x) & 0x3FFFF)
47 #define RDECODE_PKT_RES_J(x) (((unsigned)(x) & 0x3F) << 18)
48 #define RDECODE_PKT_COND_J(x) (((unsigned)(x) & 0xF) << 24)
49 #define RDECODE_PKT_TYPE_J(x) (((unsigned)(x) & 0xF) << 28)
50 #define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \
51 RDECODE_PKT_RES_J(0) | \
52 RDECODE_PKT_COND_J(cond) | \
53 RDECODE_PKT_TYPE_J(type))
54
55 #define RDECODE_CMD_MSG_BUFFER 0x00000000
56 #define RDECODE_CMD_DPB_BUFFER 0x00000001
57 #define RDECODE_CMD_DECODING_TARGET_BUFFER 0x00000002
58 #define RDECODE_CMD_FEEDBACK_BUFFER 0x00000003
59 #define RDECODE_CMD_PROB_TBL_BUFFER 0x00000004
60 #define RDECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005
61 #define RDECODE_CMD_BITSTREAM_BUFFER 0x00000100
62 #define RDECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
63 #define RDECODE_CMD_CONTEXT_BUFFER 0x00000206
64
65 #define RDECODE_MSG_CREATE 0x00000000
66 #define RDECODE_MSG_DECODE 0x00000001
67 #define RDECODE_MSG_DESTROY 0x00000002
68
69 #define RDECODE_CODEC_H264 0x00000000
70 #define RDECODE_CODEC_VC1 0x00000001
71 #define RDECODE_CODEC_MPEG2_VLD 0x00000003
72 #define RDECODE_CODEC_MPEG4 0x00000004
73 #define RDECODE_CODEC_H264_PERF 0x00000007
74 #define RDECODE_CODEC_JPEG 0x00000008
75 #define RDECODE_CODEC_H265 0x00000010
76 #define RDECODE_CODEC_VP9 0x00000011
77
78 #define RDECODE_ARRAY_MODE_LINEAR 0x00000000
79 #define RDECODE_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001
80 #define RDECODE_ARRAY_MODE_1D_THIN 0x00000002
81 #define RDECODE_ARRAY_MODE_2D_THIN 0x00000004
82 #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
83 #define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005
84
85 #define RDECODE_H264_PROFILE_BASELINE 0x00000000
86 #define RDECODE_H264_PROFILE_MAIN 0x00000001
87 #define RDECODE_H264_PROFILE_HIGH 0x00000002
88 #define RDECODE_H264_PROFILE_STEREO_HIGH 0x00000003
89 #define RDECODE_H264_PROFILE_MVC 0x00000004
90
91 #define RDECODE_VC1_PROFILE_SIMPLE 0x00000000
92 #define RDECODE_VC1_PROFILE_MAIN 0x00000001
93 #define RDECODE_VC1_PROFILE_ADVANCED 0x00000002
94
95 #define RDECODE_SW_MODE_LINEAR 0x00000000
96 #define RDECODE_256B_S 0x00000001
97 #define RDECODE_256B_D 0x00000002
98 #define RDECODE_4KB_S 0x00000005
99 #define RDECODE_4KB_D 0x00000006
100 #define RDECODE_64KB_S 0x00000009
101 #define RDECODE_64KB_D 0x0000000A
102 #define RDECODE_4KB_S_X 0x00000015
103 #define RDECODE_4KB_D_X 0x00000016
104 #define RDECODE_64KB_S_X 0x00000019
105 #define RDECODE_64KB_D_X 0x0000001A
106
107 #define RDECODE_MESSAGE_NOT_SUPPORTED 0x00000000
108 #define RDECODE_MESSAGE_CREATE 0x00000001
109 #define RDECODE_MESSAGE_DECODE 0x00000002
110 #define RDECODE_MESSAGE_AVC 0x00000006
111 #define RDECODE_MESSAGE_VC1 0x00000007
112 #define RDECODE_MESSAGE_MPEG2_VLD 0x0000000A
113 #define RDECODE_MESSAGE_MPEG4_ASP_VLD 0x0000000B
114 #define RDECODE_MESSAGE_HEVC 0x0000000D
115 #define RDECODE_MESSAGE_VP9 0x0000000E
116
117 #define RDECODE_FEEDBACK_PROFILING 0x00000001
118
119 #define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT 7
120
121 #define NUM_BUFFERS 4
122
123 #define RDECODE_VP9_PROBS_DATA_SIZE 2304
124
125 #define mmUVD_JPEG_CNTL 0x0200
126 #define mmUVD_JPEG_CNTL_BASE_IDX 1
127 #define mmUVD_JPEG_RB_BASE 0x0201
128 #define mmUVD_JPEG_RB_BASE_BASE_IDX 1
129 #define mmUVD_JPEG_RB_WPTR 0x0202
130 #define mmUVD_JPEG_RB_WPTR_BASE_IDX 1
131 #define mmUVD_JPEG_RB_RPTR 0x0203
132 #define mmUVD_JPEG_RB_RPTR_BASE_IDX 1
133 #define mmUVD_JPEG_RB_SIZE 0x0204
134 #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1
135 #define mmUVD_JPEG_TIER_CNTL2 0x021a
136 #define mmUVD_JPEG_TIER_CNTL2_BASE_IDX 1
137 #define mmUVD_JPEG_UV_TILING_CTRL 0x021c
138 #define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX 1
139 #define mmUVD_JPEG_TILING_CTRL 0x021e
140 #define mmUVD_JPEG_TILING_CTRL_BASE_IDX 1
141 #define mmUVD_JPEG_OUTBUF_RPTR 0x0220
142 #define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1
143 #define mmUVD_JPEG_OUTBUF_WPTR 0x0221
144 #define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1
145 #define mmUVD_JPEG_PITCH 0x0222
146 #define mmUVD_JPEG_PITCH_BASE_IDX 1
147 #define mmUVD_JPEG_INT_EN 0x0229
148 #define mmUVD_JPEG_INT_EN_BASE_IDX 1
149 #define mmUVD_JPEG_UV_PITCH 0x022b
150 #define mmUVD_JPEG_UV_PITCH_BASE_IDX 1
151 #define mmUVD_JPEG_INDEX 0x023e
152 #define mmUVD_JPEG_INDEX_BASE_IDX 1
153 #define mmUVD_JPEG_DATA 0x023f
154 #define mmUVD_JPEG_DATA_BASE_IDX 1
155 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438
156 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1
157 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439
158 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1
159 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a
160 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1
161 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b
162 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1
163 #define mmUVD_CTX_INDEX 0x0528
164 #define mmUVD_CTX_INDEX_BASE_IDX 1
165 #define mmUVD_CTX_DATA 0x0529
166 #define mmUVD_CTX_DATA_BASE_IDX 1
167 #define mmUVD_SOFT_RESET 0x05a0
168 #define mmUVD_SOFT_RESET_BASE_IDX 1
169
170 #define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f
171 #define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e
172 #define vcnipUVD_JRBC_IB_REF_DATA 0x408f
173 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1
174 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0
175 #define vcnipUVD_JPEG_RB_BASE 0x4001
176 #define vcnipUVD_JPEG_RB_SIZE 0x4004
177 #define vcnipUVD_JPEG_RB_WPTR 0x4002
178 #define vcnipUVD_JPEG_PITCH 0x401f
179 #define vcnipUVD_JPEG_UV_PITCH 0x4020
180 #define vcnipJPEG_DEC_ADDR_MODE 0x4027
181 #define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024
182 #define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025
183 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3
184 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2
185 #define vcnipUVD_JPEG_INDEX 0x402c
186 #define vcnipUVD_JPEG_DATA 0x402d
187 #define vcnipUVD_JPEG_TIER_CNTL2 0x400f
188 #define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e
189 #define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c
190 #define vcnipUVD_JPEG_INT_EN 0x400a
191 #define vcnipUVD_JPEG_CNTL 0x4000
192 #define vcnipUVD_JPEG_RB_RPTR 0x4003
193 #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d
194
195 #define UVD_BASE_INST0_SEG0 0x00007800
196 #define UVD_BASE_INST0_SEG1 0x00007E00
197 #define UVD_BASE_INST0_SEG2 0
198 #define UVD_BASE_INST0_SEG3 0
199 #define UVD_BASE_INST0_SEG4 0
200
201 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)
202
203 #define COND0 0
204 #define COND1 1
205 #define COND2 2
206 #define COND3 3
207 #define COND4 4
208 #define COND5 5
209 #define COND6 6
210 #define COND7 7
211
212 #define TYPE0 0
213 #define TYPE1 1
214 #define TYPE2 2
215 #define TYPE3 3
216 #define TYPE4 4
217 #define TYPE5 5
218 #define TYPE6 6
219 #define TYPE7 7
220
221 /* VP9 Frame header flags */
222 #define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT (13)
223 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT (12)
224 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT (11)
225 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_SHIFT (10)
226 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT (9)
227 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT (8)
228 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT (7)
229 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT (6)
230 #define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT (5)
231 #define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT (4)
232 #define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT (3)
233 #define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT (2)
234 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT (1)
235 #define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_SHIFT (0)
236
237 #define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK (0x00002000)
238 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK (0x00001000)
239 #define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK (0x00000800)
240 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_MASK (0x00000400)
241 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK (0x00000200)
242 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK (0x00000100)
243 #define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK (0x00000080)
244 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK (0x00000040)
245 #define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK (0x00000020)
246 #define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK (0x00000010)
247 #define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK (0x00000008)
248 #define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK (0x00000004)
249 #define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK (0x00000002)
250 #define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_MASK (0x00000001)
251
252 typedef struct rvcn_dec_message_index_s {
253 unsigned int message_id;
254 unsigned int offset;
255 unsigned int size;
256 unsigned int filled;
257 } rvcn_dec_message_index_t;
258
259 typedef struct rvcn_dec_message_header_s {
260 unsigned int header_size;
261 unsigned int total_size;
262 unsigned int num_buffers;
263 unsigned int msg_type;
264 unsigned int stream_handle;
265 unsigned int status_report_feedback_number;
266
267 rvcn_dec_message_index_t index[1];
268 } rvcn_dec_message_header_t;
269
270 typedef struct rvcn_dec_message_create_s {
271 unsigned int stream_type;
272 unsigned int session_flags;
273 unsigned int width_in_samples;
274 unsigned int height_in_samples;
275 } rvcn_dec_message_create_t;
276
277 typedef struct rvcn_dec_message_decode_s {
278 unsigned int stream_type;
279 unsigned int decode_flags;
280 unsigned int width_in_samples;
281 unsigned int height_in_samples;
282
283 unsigned int bsd_size;
284 unsigned int dpb_size;
285 unsigned int dt_size;
286 unsigned int sct_size;
287 unsigned int sc_coeff_size;
288 unsigned int hw_ctxt_size;
289 unsigned int sw_ctxt_size;
290 unsigned int pic_param_size;
291 unsigned int mb_cntl_size;
292 unsigned int reserved0[4];
293 unsigned int decode_buffer_flags;
294
295 unsigned int db_pitch;
296 unsigned int db_aligned_height;
297 unsigned int db_tiling_mode;
298 unsigned int db_swizzle_mode;
299 unsigned int db_array_mode;
300 unsigned int db_field_mode;
301 unsigned int db_surf_tile_config;
302
303 unsigned int dt_pitch;
304 unsigned int dt_uv_pitch;
305 unsigned int dt_tiling_mode;
306 unsigned int dt_swizzle_mode;
307 unsigned int dt_array_mode;
308 unsigned int dt_field_mode;
309 unsigned int dt_out_format;
310 unsigned int dt_surf_tile_config;
311 unsigned int dt_uv_surf_tile_config;
312 unsigned int dt_luma_top_offset;
313 unsigned int dt_luma_bottom_offset;
314 unsigned int dt_chroma_top_offset;
315 unsigned int dt_chroma_bottom_offset;
316 unsigned int dt_chromaV_top_offset;
317 unsigned int dt_chromaV_bottom_offset;
318
319 unsigned char dpbRefArraySlice[16];
320 unsigned char dpbCurArraySlice;
321 unsigned char dpbReserved[3];
322 } rvcn_dec_message_decode_t;
323
324 typedef struct {
325 unsigned short viewOrderIndex;
326 unsigned short viewId;
327 unsigned short numOfAnchorRefsInL0;
328 unsigned short viewIdOfAnchorRefsInL0[15];
329 unsigned short numOfAnchorRefsInL1;
330 unsigned short viewIdOfAnchorRefsInL1[15];
331 unsigned short numOfNonAnchorRefsInL0;
332 unsigned short viewIdOfNonAnchorRefsInL0[15];
333 unsigned short numOfNonAnchorRefsInL1;
334 unsigned short viewIdOfNonAnchorRefsInL1[15];
335 } radeon_mvcElement_t;
336
337 typedef struct rvcn_dec_message_avc_s {
338 unsigned int profile;
339 unsigned int level;
340
341 unsigned int sps_info_flags;
342 unsigned int pps_info_flags;
343 unsigned char chroma_format;
344 unsigned char bit_depth_luma_minus8;
345 unsigned char bit_depth_chroma_minus8;
346 unsigned char log2_max_frame_num_minus4;
347
348 unsigned char pic_order_cnt_type;
349 unsigned char log2_max_pic_order_cnt_lsb_minus4;
350 unsigned char num_ref_frames;
351 unsigned char reserved_8bit;
352
353 signed char pic_init_qp_minus26;
354 signed char pic_init_qs_minus26;
355 signed char chroma_qp_index_offset;
356 signed char second_chroma_qp_index_offset;
357
358 unsigned char num_slice_groups_minus1;
359 unsigned char slice_group_map_type;
360 unsigned char num_ref_idx_l0_active_minus1;
361 unsigned char num_ref_idx_l1_active_minus1;
362
363 unsigned short slice_group_change_rate_minus1;
364 unsigned short reserved_16bit_1;
365
366 unsigned char scaling_list_4x4[6][16];
367 unsigned char scaling_list_8x8[2][64];
368
369 unsigned int frame_num;
370 unsigned int frame_num_list[16];
371 int curr_field_order_cnt_list[2];
372 int field_order_cnt_list[16][2];
373
374 unsigned int decoded_pic_idx;
375 unsigned int curr_pic_ref_frame_num;
376 unsigned char ref_frame_list[16];
377
378 unsigned int reserved[122];
379
380 struct {
381 unsigned int numViews;
382 unsigned int viewId0;
383 radeon_mvcElement_t mvcElements[1];
384 } mvc;
385
386 } rvcn_dec_message_avc_t;
387
388 typedef struct rvcn_dec_message_vc1_s {
389 unsigned int profile;
390 unsigned int level;
391 unsigned int sps_info_flags;
392 unsigned int pps_info_flags;
393 unsigned int pic_structure;
394 unsigned int chroma_format;
395 unsigned short decoded_pic_idx;
396 unsigned short deblocked_pic_idx;
397 unsigned short forward_ref_idx;
398 unsigned short backward_ref_idx;
399 unsigned int cached_frame_flag;
400 } rvcn_dec_message_vc1_t;
401
402 typedef struct rvcn_dec_message_mpeg2_vld_s {
403 unsigned int decoded_pic_idx;
404 unsigned int forward_ref_pic_idx;
405 unsigned int backward_ref_pic_idx;
406
407 unsigned char load_intra_quantiser_matrix;
408 unsigned char load_nonintra_quantiser_matrix;
409 unsigned char reserved_quantiser_alignement[2];
410 unsigned char intra_quantiser_matrix[64];
411 unsigned char nonintra_quantiser_matrix[64];
412
413 unsigned char profile_and_level_indication;
414 unsigned char chroma_format;
415
416 unsigned char picture_coding_type;
417
418 unsigned char reserved_1;
419
420 unsigned char f_code[2][2];
421 unsigned char intra_dc_precision;
422 unsigned char pic_structure;
423 unsigned char top_field_first;
424 unsigned char frame_pred_frame_dct;
425 unsigned char concealment_motion_vectors;
426 unsigned char q_scale_type;
427 unsigned char intra_vlc_format;
428 unsigned char alternate_scan;
429 } rvcn_dec_message_mpeg2_vld_t;
430
431 typedef struct rvcn_dec_message_mpeg4_asp_vld_s {
432 unsigned int decoded_pic_idx;
433 unsigned int forward_ref_pic_idx;
434 unsigned int backward_ref_pic_idx;
435
436 unsigned int variant_type;
437 unsigned char profile_and_level_indication;
438
439 unsigned char video_object_layer_verid;
440 unsigned char video_object_layer_shape;
441
442 unsigned char reserved_1;
443
444 unsigned short video_object_layer_width;
445 unsigned short video_object_layer_height;
446
447 unsigned short vop_time_increment_resolution;
448
449 unsigned short reserved_2;
450
451 struct {
452 unsigned int short_video_header :1;
453 unsigned int obmc_disable :1;
454 unsigned int interlaced :1;
455 unsigned int load_intra_quant_mat :1;
456 unsigned int load_nonintra_quant_mat :1;
457 unsigned int quarter_sample :1;
458 unsigned int complexity_estimation_disable :1;
459 unsigned int resync_marker_disable :1;
460 unsigned int data_partitioned :1;
461 unsigned int reversible_vlc :1;
462 unsigned int newpred_enable :1;
463 unsigned int reduced_resolution_vop_enable :1;
464 unsigned int scalability :1;
465 unsigned int is_object_layer_identifier :1;
466 unsigned int fixed_vop_rate :1;
467 unsigned int newpred_segment_type :1;
468 unsigned int reserved_bits :16;
469 };
470
471 unsigned char quant_type;
472 unsigned char reserved_3[3];
473 unsigned char intra_quant_mat[64];
474 unsigned char nonintra_quant_mat[64];
475
476 struct {
477 unsigned char sprite_enable;
478
479 unsigned char reserved_4[3];
480
481 unsigned short sprite_width;
482 unsigned short sprite_height;
483 short sprite_left_coordinate;
484 short sprite_top_coordinate;
485
486 unsigned char no_of_sprite_warping_points;
487 unsigned char sprite_warping_accuracy;
488 unsigned char sprite_brightness_change;
489 unsigned char low_latency_sprite_enable;
490 } sprite_config;
491
492 struct {
493 struct {
494 unsigned int check_skip :1;
495 unsigned int switch_rounding :1;
496 unsigned int t311 :1;
497 unsigned int reserved_bits :29;
498 };
499
500 unsigned char vol_mode;
501
502 unsigned char reserved_5[3];
503 } divx_311_config;
504
505 struct {
506 unsigned char vop_data_present;
507 unsigned char vop_coding_type;
508 unsigned char vop_quant;
509 unsigned char vop_coded;
510 unsigned char vop_rounding_type;
511 unsigned char intra_dc_vlc_thr;
512 unsigned char top_field_first;
513 unsigned char alternate_vertical_scan_flag;
514 unsigned char vop_fcode_forward;
515 unsigned char vop_fcode_backward;
516 unsigned int TRB[2];
517 unsigned int TRD[2];
518 } vop;
519
520 } rvcn_dec_message_mpeg4_asp_vld_t;
521
522 typedef struct rvcn_dec_message_hevc_s {
523 unsigned int sps_info_flags;
524 unsigned int pps_info_flags;
525 unsigned char chroma_format;
526 unsigned char bit_depth_luma_minus8;
527 unsigned char bit_depth_chroma_minus8;
528 unsigned char log2_max_pic_order_cnt_lsb_minus4;
529
530 unsigned char sps_max_dec_pic_buffering_minus1;
531 unsigned char log2_min_luma_coding_block_size_minus3;
532 unsigned char log2_diff_max_min_luma_coding_block_size;
533 unsigned char log2_min_transform_block_size_minus2;
534
535 unsigned char log2_diff_max_min_transform_block_size;
536 unsigned char max_transform_hierarchy_depth_inter;
537 unsigned char max_transform_hierarchy_depth_intra;
538 unsigned char pcm_sample_bit_depth_luma_minus1;
539
540 unsigned char pcm_sample_bit_depth_chroma_minus1;
541 unsigned char log2_min_pcm_luma_coding_block_size_minus3;
542 unsigned char log2_diff_max_min_pcm_luma_coding_block_size;
543 unsigned char num_extra_slice_header_bits;
544
545 unsigned char num_short_term_ref_pic_sets;
546 unsigned char num_long_term_ref_pic_sps;
547 unsigned char num_ref_idx_l0_default_active_minus1;
548 unsigned char num_ref_idx_l1_default_active_minus1;
549
550 signed char pps_cb_qp_offset;
551 signed char pps_cr_qp_offset;
552 signed char pps_beta_offset_div2;
553 signed char pps_tc_offset_div2;
554
555 unsigned char diff_cu_qp_delta_depth;
556 unsigned char num_tile_columns_minus1;
557 unsigned char num_tile_rows_minus1;
558 unsigned char log2_parallel_merge_level_minus2;
559
560 unsigned short column_width_minus1[19];
561 unsigned short row_height_minus1[21];
562
563 signed char init_qp_minus26;
564 unsigned char num_delta_pocs_ref_rps_idx;
565 unsigned char curr_idx;
566 unsigned char reserved[1];
567 int curr_poc;
568 unsigned char ref_pic_list[16];
569 int poc_list[16];
570 unsigned char ref_pic_set_st_curr_before[8];
571 unsigned char ref_pic_set_st_curr_after[8];
572 unsigned char ref_pic_set_lt_curr[8];
573
574 unsigned char ucScalingListDCCoefSizeID2[6];
575 unsigned char ucScalingListDCCoefSizeID3[2];
576
577 unsigned char highestTid;
578 unsigned char isNonRef;
579
580 unsigned char p010_mode;
581 unsigned char msb_mode;
582 unsigned char luma_10to8;
583 unsigned char chroma_10to8;
584
585 unsigned char hevc_reserved[2];
586
587 unsigned char direct_reflist[2][15];
588 } rvcn_dec_message_hevc_t;
589
590 typedef struct rvcn_dec_message_vp9_s {
591 unsigned int frame_header_flags;
592
593 unsigned char frame_context_idx;
594 unsigned char reset_frame_context;
595
596 unsigned char curr_pic_idx;
597 unsigned char interp_filter;
598
599 unsigned char filter_level;
600 unsigned char sharpness_level;
601 unsigned char lf_adj_level[8][4][2];
602 unsigned char base_qindex;
603 signed char y_dc_delta_q;
604 signed char uv_ac_delta_q;
605 signed char uv_dc_delta_q;
606
607 unsigned char log2_tile_cols;
608 unsigned char log2_tile_rows;
609 unsigned char tx_mode;
610 unsigned char reference_mode;
611 unsigned char chroma_format;
612
613 unsigned char ref_frame_map[8];
614
615 unsigned char frame_refs[3];
616 unsigned char ref_frame_sign_bias[3];
617 unsigned char frame_to_show;
618 unsigned char bit_depth_luma_minus8;
619 unsigned char bit_depth_chroma_minus8;
620
621 unsigned char p010_mode;
622 unsigned char msb_mode;
623 unsigned char luma_10to8;
624 unsigned char chroma_10to8;
625
626 unsigned int vp9_frame_size;
627 unsigned int compressed_header_size;
628 unsigned int uncompressed_header_size;
629 } rvcn_dec_message_vp9_t;
630
631 typedef struct rvcn_dec_feature_index_s {
632 unsigned int feature_id;
633 unsigned int offset;
634 unsigned int size;
635 unsigned int filled;
636 } rvcn_dec_feature_index_t;
637
638 typedef struct rvcn_dec_feedback_header_s {
639 unsigned int header_size;
640 unsigned int total_size;
641 unsigned int num_buffers;
642 unsigned int status_report_feedback_number;
643 unsigned int status;
644 unsigned int value;
645 unsigned int errorBits;
646 rvcn_dec_feature_index_t index[1];
647 } rvcn_dec_feedback_header_t;
648
649 typedef struct rvcn_dec_feedback_profiling_s {
650 unsigned int size;
651
652 unsigned int decodingTime;
653 unsigned int decodePlusOverhead;
654 unsigned int masterTimerHits;
655 unsigned int uvdLBSIREWaitCount;
656
657 unsigned int avgMPCMemLatency;
658 unsigned int maxMPCMemLatency;
659 unsigned int uvdMPCLumaHits;
660 unsigned int uvdMPCLumaHitPend;
661 unsigned int uvdMPCLumaSearch;
662 unsigned int uvdMPCChromaHits;
663 unsigned int uvdMPCChromaHitPend;
664 unsigned int uvdMPCChromaSearch;
665
666 unsigned int uvdLMIPerfCountLo;
667 unsigned int uvdLMIPerfCountHi;
668 unsigned int uvdLMIAvgLatCntrEnvHit;
669 unsigned int uvdLMILatCntr;
670
671 unsigned int frameCRC0;
672 unsigned int frameCRC1;
673 unsigned int frameCRC2;
674 unsigned int frameCRC3;
675
676 unsigned int uvdLMIPerfMonCtrl;
677 unsigned int uvdLMILatCtrl;
678 unsigned int uvdMPCCntl;
679 unsigned int reserved0[4];
680 unsigned int decoderID;
681 unsigned int codec;
682
683 unsigned int dmaHwCrc32Enable;
684 unsigned int dmaHwCrc32Value;
685 unsigned int dmaHwCrc32Value2;
686 } rvcn_dec_feedback_profiling_t;
687
688 typedef struct rvcn_dec_vp9_nmv_ctx_mask_s {
689 unsigned short classes_mask[2];
690 unsigned short bits_mask[2];
691 unsigned char joints_mask;
692 unsigned char sign_mask[2];
693 unsigned char class0_mask[2];
694 unsigned char class0_fp_mask[2];
695 unsigned char fp_mask[2];
696 unsigned char class0_hp_mask[2];
697 unsigned char hp_mask[2];
698 unsigned char reserve[11];
699 } rvcn_dec_vp9_nmv_ctx_mask_t;
700
701 typedef struct rvcn_dec_vp9_nmv_component_s{
702 unsigned char sign;
703 unsigned char classes[10];
704 unsigned char class0[1];
705 unsigned char bits[10];
706 unsigned char class0_fp[2][3];
707 unsigned char fp[3];
708 unsigned char class0_hp;
709 unsigned char hp;
710 } rvcn_dec_vp9_nmv_component_t;
711
712 typedef struct rvcn_dec_vp9_probs_s {
713 rvcn_dec_vp9_nmv_ctx_mask_t nmvc_mask;
714 unsigned char coef_probs[4][2][2][6][6][3];
715 unsigned char y_mode_prob[4][9];
716 unsigned char uv_mode_prob[10][9];
717 unsigned char single_ref_prob[5][2];
718 unsigned char switchable_interp_prob[4][2];
719 unsigned char partition_prob[16][3];
720 unsigned char inter_mode_probs[7][3];
721 unsigned char mbskip_probs[3];
722 unsigned char intra_inter_prob[4];
723 unsigned char comp_inter_prob[5];
724 unsigned char comp_ref_prob[5];
725 unsigned char tx_probs_32x32[2][3];
726 unsigned char tx_probs_16x16[2][2];
727 unsigned char tx_probs_8x8[2][1];
728 unsigned char mv_joints[3];
729 rvcn_dec_vp9_nmv_component_t mv_comps[2];
730 } rvcn_dec_vp9_probs_t;
731
732 typedef struct rvcn_dec_vp9_probs_segment_s {
733 union {
734 rvcn_dec_vp9_probs_t probs;
735 unsigned char probs_data[RDECODE_VP9_PROBS_DATA_SIZE];
736 };
737
738 union {
739 struct {
740 unsigned int feature_data[8];
741 unsigned char tree_probs[7];
742 unsigned char pred_probs[3];
743 unsigned char abs_delta;
744 unsigned char feature_mask[8];
745 } seg;
746 unsigned char segment_data[256];
747 };
748 } rvcn_dec_vp9_probs_segment_t;
749
750 struct jpeg_params {
751 unsigned bsd_size;
752 unsigned dt_pitch;
753 unsigned dt_uv_pitch;
754 unsigned dt_luma_top_offset;
755 unsigned dt_chroma_top_offset;
756 };
757
758 struct radeon_decoder {
759 struct pipe_video_codec base;
760
761 unsigned stream_handle;
762 unsigned stream_type;
763 unsigned frame_number;
764
765 struct pipe_screen *screen;
766 struct radeon_winsys *ws;
767 struct radeon_cmdbuf *cs;
768
769 void *msg;
770 uint32_t *fb;
771 uint8_t *it;
772 uint8_t *probs;
773 void *bs_ptr;
774
775 struct rvid_buffer msg_fb_it_probs_buffers[NUM_BUFFERS];
776 struct rvid_buffer bs_buffers[NUM_BUFFERS];
777 struct rvid_buffer dpb;
778 struct rvid_buffer ctx;
779 struct rvid_buffer sessionctx;
780
781 unsigned bs_size;
782 unsigned cur_buffer;
783 void *render_pic_list[16];
784 bool show_frame;
785 unsigned ref_idx;
786 struct {
787 unsigned data0;
788 unsigned data1;
789 unsigned cmd;
790 unsigned cntl;
791 } reg;
792 struct jpeg_params jpg;
793 void (*send_cmd)(struct radeon_decoder *dec,
794 struct pipe_video_buffer *target,
795 struct pipe_picture_desc *picture);
796 };
797
798 void send_cmd_dec(struct radeon_decoder *dec,
799 struct pipe_video_buffer *target,
800 struct pipe_picture_desc *picture);
801
802 void send_cmd_jpeg(struct radeon_decoder *dec,
803 struct pipe_video_buffer *target,
804 struct pipe_picture_desc *picture);
805
806 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
807 const struct pipe_video_codec *templat);
808
809 #endif