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radeon/vcn: update for new vcn enc interface
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_enc.h
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef _RADEON_VCN_ENC_H
29 #define _RADEON_VCN_ENC_H
30
31 #define RENCODE_IB_OP_INITIALIZE 0x01000001
32 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002
33 #define RENCODE_IB_OP_ENCODE 0x01000003
34 #define RENCODE_IB_OP_INIT_RC 0x01000004
35 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005
36 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006
37 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007
38 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008
39
40 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000
41 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16
42 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF
43 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
44
45 #define RENCODE_ENCODE_STANDARD_HEVC 0
46 #define RENCODE_ENCODE_STANDARD_H264 1
47
48 #define RENCODE_PREENCODE_MODE_NONE 0x00000000
49 #define RENCODE_PREENCODE_MODE_1X 0x00000001
50 #define RENCODE_PREENCODE_MODE_2X 0x00000002
51 #define RENCODE_PREENCODE_MODE_4X 0x00000004
52
53 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
54 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
55
56 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
57 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
58
59 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
60 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
61 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
62 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003
63
64 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000
65 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001
66 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002
67 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003
68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004
69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005
70
71 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
72 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
73
74 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000
75 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001
76
77 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000
78 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001
79 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002
80 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
81
82 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000
83 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
84
85 #define RENCODE_PICTURE_TYPE_B 0
86 #define RENCODE_PICTURE_TYPE_P 1
87 #define RENCODE_PICTURE_TYPE_I 2
88 #define RENCODE_PICTURE_TYPE_P_SKIP 3
89
90 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0
91 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1
92 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5
93 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9
94
95 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0
96 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1
97 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2
98
99 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0
100 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1
101 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2
102
103 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
104 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
105 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
106
107 #define RENCODE_INTRA_REFRESH_MODE_NONE 0
108 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
109 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
110
111 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34
112
113 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0
114 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1
115
116 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
117 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
118
119 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0
120 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
121
122 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
123 #define RADEON_ENC_BEGIN(cmd) { \
124 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
125 RADEON_ENC_CS(cmd)
126 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
127 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
128 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
129 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
130 enc->total_task_size += *begin;}
131
132 typedef struct rvcn_enc_session_info_s
133 {
134 uint32_t interface_version;
135 uint32_t sw_context_address_hi;
136 uint32_t sw_context_address_lo;
137 } rvcn_enc_session_info_t;
138
139 typedef struct rvcn_enc_task_info_s
140 {
141 uint32_t total_size_of_all_packages;
142 uint32_t task_id;
143 uint32_t allowed_max_num_feedbacks;
144 } rvcn_enc_task_info_t;
145
146 typedef struct rvcn_enc_session_init_s
147 {
148 uint32_t encode_standard;
149 uint32_t aligned_picture_width;
150 uint32_t aligned_picture_height;
151 uint32_t padding_width;
152 uint32_t padding_height;
153 uint32_t pre_encode_mode;
154 uint32_t pre_encode_chroma_enabled;
155 } rvcn_enc_session_init_t;
156
157 typedef struct rvcn_enc_layer_control_s
158 {
159 uint32_t max_num_temporal_layers;
160 uint32_t num_temporal_layers;
161 } rvcn_enc_layer_control_t;
162
163 typedef struct rvcn_enc_layer_select_s
164 {
165 uint32_t temporal_layer_index;
166 } rvcn_enc_layer_select_t;
167
168 typedef struct rvcn_enc_h264_slice_control_s
169 {
170 uint32_t slice_control_mode;
171 union
172 {
173 uint32_t num_mbs_per_slice;
174 uint32_t num_bits_per_slice;
175 };
176 } rvcn_enc_h264_slice_control_t;
177
178 typedef struct rvcn_enc_hevc_slice_control_s
179 {
180 uint32_t slice_control_mode;
181 union
182 {
183 struct
184 {
185 uint32_t num_ctbs_per_slice;
186 uint32_t num_ctbs_per_slice_segment;
187 } fixed_ctbs_per_slice;
188
189 struct
190 {
191 uint32_t num_bits_per_slice;
192 uint32_t num_bits_per_slice_segment;
193 } fixed_bits_per_slice;
194 };
195 } rvcn_enc_hevc_slice_control_t;
196
197 typedef struct rvcn_enc_h264_spec_misc_s
198 {
199 uint32_t constrained_intra_pred_flag;
200 uint32_t cabac_enable;
201 uint32_t cabac_init_idc;
202 uint32_t half_pel_enabled;
203 uint32_t quarter_pel_enabled;
204 uint32_t profile_idc;
205 uint32_t level_idc;
206 } rvcn_enc_h264_spec_misc_t;
207
208 typedef struct rvcn_enc_hevc_spec_misc_s
209 {
210 uint32_t log2_min_luma_coding_block_size_minus3;
211 uint32_t amp_disabled;
212 uint32_t strong_intra_smoothing_enabled;
213 uint32_t constrained_intra_pred_flag;
214 uint32_t cabac_init_flag;
215 uint32_t half_pel_enabled;
216 uint32_t quarter_pel_enabled;
217 } rvcn_enc_hevc_spec_misc_t;
218
219 typedef struct rvcn_enc_rate_ctl_session_init_s
220 {
221 uint32_t rate_control_method;
222 uint32_t vbv_buffer_level;
223 } rvcn_enc_rate_ctl_session_init_t;
224
225 typedef struct rvcn_enc_rate_ctl_layer_init_s
226 {
227 uint32_t target_bit_rate;
228 uint32_t peak_bit_rate;
229 uint32_t frame_rate_num;
230 uint32_t frame_rate_den;
231 uint32_t vbv_buffer_size;
232 uint32_t avg_target_bits_per_picture;
233 uint32_t peak_bits_per_picture_integer;
234 uint32_t peak_bits_per_picture_fractional;
235 } rvcn_enc_rate_ctl_layer_init_t;
236
237 typedef struct rvcn_enc_rate_ctl_per_picture_s
238 {
239 uint32_t qp;
240 uint32_t min_qp_app;
241 uint32_t max_qp_app;
242 uint32_t max_au_size;
243 uint32_t enabled_filler_data;
244 uint32_t skip_frame_enable;
245 uint32_t enforce_hrd;
246 } rvcn_enc_rate_ctl_per_picture_t;
247
248 typedef struct rvcn_enc_quality_params_s
249 {
250 uint32_t vbaq_mode;
251 uint32_t scene_change_sensitivity;
252 uint32_t scene_change_min_idr_interval;
253 uint32_t two_pass_search_center_map_mode;
254 } rvcn_enc_quality_params_t;
255
256 typedef struct rvcn_enc_direct_output_nalu_s
257 {
258 uint32_t type;
259 uint32_t size;
260 uint32_t data[1];
261 } rvcn_enc_direct_output_nalu_t;
262
263 typedef struct rvcn_enc_slice_header_s
264 {
265 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
266 struct {
267 uint32_t instruction;
268 uint32_t num_bits;
269 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
270 } rvcn_enc_slice_header_t;
271
272 typedef struct rvcn_enc_encode_params_s
273 {
274 uint32_t pic_type;
275 uint32_t allowed_max_bitstream_size;
276 uint32_t input_picture_luma_address_hi;
277 uint32_t input_picture_luma_address_lo;
278 uint32_t input_picture_chroma_address_hi;
279 uint32_t input_picture_chroma_address_lo;
280 uint32_t input_pic_luma_pitch;
281 uint32_t input_pic_chroma_pitch;
282 uint8_t input_pic_swizzle_mode;
283 uint32_t reference_picture_index;
284 uint32_t reconstructed_picture_index;
285 } rvcn_enc_encode_params_t;
286
287 typedef struct rvcn_enc_h264_encode_params_s
288 {
289 uint32_t input_picture_structure;
290 uint32_t interlaced_mode;
291 uint32_t reference_picture_structure;
292 uint32_t reference_picture1_index;
293 } rvcn_enc_h264_encode_params_t;
294
295 typedef struct rvcn_enc_h264_deblocking_filter_s
296 {
297 uint32_t disable_deblocking_filter_idc;
298 int32_t alpha_c0_offset_div2;
299 int32_t beta_offset_div2;
300 int32_t cb_qp_offset;
301 int32_t cr_qp_offset;
302 } rvcn_enc_h264_deblocking_filter_t;
303
304 typedef struct rvcn_enc_hevc_deblocking_filter_s
305 {
306 uint32_t loop_filter_across_slices_enabled;
307 int32_t deblocking_filter_disabled;
308 int32_t beta_offset_div2;
309 int32_t tc_offset_div2;
310 int32_t cb_qp_offset;
311 int32_t cr_qp_offset;
312 } rvcn_enc_hevc_deblocking_filter_t;
313
314 typedef struct rvcn_enc_intra_refresh_s
315 {
316 uint32_t intra_refresh_mode;
317 uint32_t offset;
318 uint32_t region_size;
319 } rvcn_enc_intra_refresh_t;
320
321 typedef struct rvcn_enc_reconstructed_picture_s
322 {
323 uint32_t luma_offset;
324 uint32_t chroma_offset;
325 } rvcn_enc_reconstructed_picture_t;
326
327 typedef struct rvcn_enc_encode_context_buffer_s
328 {
329 uint32_t encode_context_address_hi;
330 uint32_t encode_context_address_lo;
331 uint32_t swizzle_mode;
332 uint32_t rec_luma_pitch;
333 uint32_t rec_chroma_pitch;
334 uint32_t num_reconstructed_pictures;
335 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
336 uint32_t pre_encode_picture_luma_pitch;
337 uint32_t pre_encode_picture_chroma_pitch;
338 rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
339 rvcn_enc_reconstructed_picture_t pre_encode_input_picture;
340 } rvcn_enc_encode_context_buffer_t;
341
342 typedef struct rvcn_enc_video_bitstream_buffer_s
343 {
344 uint32_t mode;
345 uint32_t video_bitstream_buffer_address_hi;
346 uint32_t video_bitstream_buffer_address_lo;
347 uint32_t video_bitstream_buffer_size;
348 uint32_t video_bitstream_data_offset;
349 } rvcn_enc_video_bitstream_buffer_t;
350
351 typedef struct rvcn_enc_feedback_buffer_s
352 {
353 uint32_t mode;
354 uint32_t feedback_buffer_address_hi;
355 uint32_t feedback_buffer_address_lo;
356 uint32_t feedback_buffer_size;
357 uint32_t feedback_data_size;
358 } rvcn_enc_feedback_buffer_t;
359
360 typedef struct rvcn_enc_cmd_s
361 {
362 uint32_t session_info;
363 uint32_t task_info;
364 uint32_t session_init;
365 uint32_t layer_control;
366 uint32_t layer_select;
367 uint32_t rc_session_init;
368 uint32_t rc_layer_init;
369 uint32_t rc_per_pic;
370 uint32_t quality_params;
371 uint32_t slice_header;
372 uint32_t enc_params;
373 uint32_t intra_refresh;
374 uint32_t ctx;
375 uint32_t bitstream;
376 uint32_t feedback;
377 uint32_t nalu;
378 uint32_t slice_control_hevc;
379 uint32_t spec_misc_hevc;
380 uint32_t enc_params_hevc;
381 uint32_t deblocking_filter_hevc;
382 uint32_t slice_control_h264;
383 uint32_t spec_misc_h264;
384 uint32_t enc_params_h264;
385 uint32_t deblocking_filter_h264;
386 uint32_t input_format;
387 uint32_t output_format;
388 } rvcn_enc_cmd_t;
389
390 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource,
391 struct pb_buffer **handle,
392 struct radeon_surf **surface);
393
394 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
395 const struct pipe_video_codec *templat,
396 struct radeon_winsys* ws,
397 radeon_enc_get_buffer get_buffer);
398
399 struct radeon_enc_pic {
400 enum pipe_h264_enc_picture_type picture_type;
401
402 unsigned frame_num;
403 unsigned pic_order_cnt;
404 unsigned pic_order_cnt_type;
405 unsigned ref_idx_l0;
406 unsigned ref_idx_l1;
407 unsigned crop_left;
408 unsigned crop_right;
409 unsigned crop_top;
410 unsigned crop_bottom;
411 unsigned general_tier_flag;
412 unsigned general_profile_idc;
413 unsigned general_level_idc;
414 unsigned max_poc;
415 unsigned log2_max_poc;
416 unsigned chroma_format_idc;
417 unsigned pic_width_in_luma_samples;
418 unsigned pic_height_in_luma_samples;
419 unsigned log2_diff_max_min_luma_coding_block_size;
420 unsigned log2_min_transform_block_size_minus2;
421 unsigned log2_diff_max_min_transform_block_size;
422 unsigned max_transform_hierarchy_depth_inter;
423 unsigned max_transform_hierarchy_depth_intra;
424 unsigned log2_parallel_merge_level_minus2;
425 unsigned bit_depth_luma_minus8;
426 unsigned bit_depth_chroma_minus8;
427 unsigned nal_unit_type;
428 unsigned max_num_merge_cand;
429
430 bool not_referenced;
431 bool is_idr;
432 bool is_even_frame;
433 bool sample_adaptive_offset_enabled_flag;
434 bool pcm_enabled_flag;
435 bool sps_temporal_mvp_enabled_flag;
436
437 rvcn_enc_session_info_t session_info;
438 rvcn_enc_task_info_t task_info;
439 rvcn_enc_session_init_t session_init;
440 rvcn_enc_layer_control_t layer_ctrl;
441 rvcn_enc_layer_select_t layer_sel;
442 rvcn_enc_h264_slice_control_t slice_ctrl;
443 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl;
444 rvcn_enc_h264_spec_misc_t spec_misc;
445 rvcn_enc_hevc_spec_misc_t hevc_spec_misc;
446 rvcn_enc_rate_ctl_session_init_t rc_session_init;
447 rvcn_enc_rate_ctl_layer_init_t rc_layer_init;
448 rvcn_enc_h264_encode_params_t h264_enc_params;
449 rvcn_enc_h264_deblocking_filter_t h264_deblock;
450 rvcn_enc_hevc_deblocking_filter_t hevc_deblock;
451 rvcn_enc_rate_ctl_per_picture_t rc_per_pic;
452 rvcn_enc_quality_params_t quality_params;
453 rvcn_enc_encode_context_buffer_t ctx_buf;
454 rvcn_enc_video_bitstream_buffer_t bit_buf;
455 rvcn_enc_feedback_buffer_t fb_buf;
456 rvcn_enc_intra_refresh_t intra_ref;
457 rvcn_enc_encode_params_t enc_params;
458 };
459
460 struct radeon_encoder {
461 struct pipe_video_codec base;
462
463 void (*begin)(struct radeon_encoder *enc);
464 void (*encode)(struct radeon_encoder *enc);
465 void (*destroy)(struct radeon_encoder *enc);
466 void (*session_info)(struct radeon_encoder *enc);
467 void (*task_info)(struct radeon_encoder *enc, bool need_feedback);
468 void (*session_init)(struct radeon_encoder *enc);
469 void (*layer_control)(struct radeon_encoder *enc);
470 void (*layer_select)(struct radeon_encoder *enc);
471 void (*slice_control)(struct radeon_encoder *enc);
472 void (*spec_misc)(struct radeon_encoder *enc);
473 void (*rc_session_init)(struct radeon_encoder *enc);
474 void (*rc_layer_init)(struct radeon_encoder *enc);
475 void (*deblocking_filter)(struct radeon_encoder *enc);
476 void (*quality_params)(struct radeon_encoder *enc);
477 void (*nalu_sps)(struct radeon_encoder *enc);
478 void (*nalu_pps)(struct radeon_encoder *enc);
479 void (*nalu_vps)(struct radeon_encoder *enc);
480 void (*nalu_aud)(struct radeon_encoder *enc);
481 void (*slice_header)(struct radeon_encoder *enc);
482 void (*ctx)(struct radeon_encoder *enc);
483 void (*bitstream)(struct radeon_encoder *enc);
484 void (*feedback)(struct radeon_encoder *enc);
485 void (*intra_refresh)(struct radeon_encoder *enc);
486 void (*rc_per_pic)(struct radeon_encoder *enc);
487 void (*encode_params)(struct radeon_encoder *enc);
488 void (*encode_params_codec_spec)(struct radeon_encoder *enc);
489 void (*op_init)(struct radeon_encoder *enc);
490 void (*op_close)(struct radeon_encoder *enc);
491 void (*op_enc)(struct radeon_encoder *enc);
492 void (*op_init_rc)(struct radeon_encoder *enc);
493 void (*op_init_rc_vbv)(struct radeon_encoder *enc);
494 void (*op_speed)(struct radeon_encoder *enc);
495 void (*encode_headers)(struct radeon_encoder *enc);
496 void (*input_format)(struct radeon_encoder *enc);
497 void (*output_format)(struct radeon_encoder *enc);
498
499 unsigned stream_handle;
500
501 struct pipe_screen *screen;
502 struct radeon_winsys* ws;
503 struct radeon_cmdbuf* cs;
504
505 radeon_enc_get_buffer get_buffer;
506
507 struct pb_buffer* handle;
508 struct radeon_surf* luma;
509 struct radeon_surf* chroma;
510
511 struct pb_buffer* bs_handle;
512 unsigned bs_size;
513
514 unsigned cpb_num;
515
516 struct rvid_buffer *si;
517 struct rvid_buffer *fb;
518 struct rvid_buffer cpb;
519 struct radeon_enc_pic enc_pic;
520 rvcn_enc_cmd_t cmd;
521
522 unsigned alignment;
523 unsigned shifter;
524 unsigned bits_in_shifter;
525 unsigned num_zeros;
526 unsigned byte_index;
527 unsigned bits_output;
528 uint32_t total_task_size;
529 uint32_t* p_task_size;
530
531 bool emulation_prevention;
532 bool need_feedback;
533 };
534
535 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
536 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
537 signed offset);
538
539 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
540
541 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
542
543 void radeon_enc_emulation_prevention(struct radeon_encoder *enc,
544 unsigned char byte);
545
546 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
547 unsigned int num_bits);
548
549 void radeon_enc_reset(struct radeon_encoder *enc);
550
551 void radeon_enc_byte_align(struct radeon_encoder *enc);
552
553 void radeon_enc_flush_headers(struct radeon_encoder *enc);
554
555 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value);
556
557 void radeon_enc_code_se(struct radeon_encoder *enc, int value);
558
559 void radeon_enc_1_2_init(struct radeon_encoder *enc);
560
561 void radeon_enc_2_0_init(struct radeon_encoder *enc);
562
563 #endif // _RADEON_VCN_ENC_H