src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33 #include "util/u_memory.h"
  34
  35 #include "vl/vl_video_buffer.h"
  36
  37 #include "r600_pipe_common.h"
  38 #include "radeon_video.h"
  39 #include "radeon_vcn_enc.h"
  40
  41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
  42 #define RADEON_ENC_BEGIN(cmd) { \
  43         uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
  44 RADEON_ENC_CS(cmd)
  45 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
  46 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
  47 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
  48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
  49         enc->total_task_size += *begin;}
  50
  51 static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
  52 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
  53
  54 static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
  55                                                                   enum radeon_bo_usage usage, enum radeon_bo_domain domain,
  56                                                                   signed offset)
  57 {
  58         enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
  59                                                                            domain, RADEON_PRIO_VCE);
  60         uint64_t addr;
  61         addr = enc->ws->buffer_get_virtual_address(buf);
  62         addr = addr + offset;
  63         RADEON_ENC_CS(addr >> 32);
  64         RADEON_ENC_CS(addr);
  65 }
  66
  67 static void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
  68 {
  69         if (set != enc->emulation_prevention) {
  70                 enc->emulation_prevention = set;
  71                 enc->num_zeros = 0;
  72         }
  73 }
  74
  75 static void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
  76 {
  77         if (enc->byte_index == 0)
  78                 enc->cs->current.buf[enc->cs->current.cdw] = 0;
  79         enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
  80         enc->byte_index++;
  81
  82         if (enc->byte_index >= 4) {
  83                 enc->byte_index = 0;
  84                 enc->cs->current.cdw++;
  85         }
  86 }
  87
  88 static void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
  89 {
  90         if(enc->emulation_prevention) {
  91                 if((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
  92             radeon_enc_output_one_byte(enc, 0x03);
  93             enc->bits_output += 8;
  94             enc->num_zeros = 0;
  95         }
  96         enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
  97     }
  98 }
  99
 100 static void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, unsigned int num_bits)
 101 {
 102         unsigned int bits_to_pack = 0;
 103
 104         while(num_bits > 0) {
 105                 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
 106                 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
 107
 108                 if (bits_to_pack < num_bits)
 109                         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
 110
 111                 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
 112                 num_bits -= bits_to_pack;
 113                 enc->bits_in_shifter += bits_to_pack;
 114
 115                 while(enc->bits_in_shifter >= 8) {
 116                         unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 117                         enc->shifter <<= 8;
 118                         radeon_enc_emulation_prevention(enc, output_byte);
 119                         radeon_enc_output_one_byte(enc, output_byte);
 120                         enc->bits_in_shifter -= 8;
 121                         enc->bits_output += 8;
 122                 }
 123         }
 124 }
 125
 126 static void radeon_enc_reset(struct radeon_encoder *enc)
 127 {
 128         enc->emulation_prevention = false;
 129         enc->shifter = 0;
 130         enc->bits_in_shifter = 0;
 131         enc->bits_output = 0;
 132         enc->num_zeros = 0;
 133         enc->byte_index = 0;
 134 }
 135
 136 static void radeon_enc_byte_align(struct radeon_encoder *enc)
 137 {
 138         unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
 139
 140         if (num_padding_zeros > 0)
 141                 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
 142 }
 143
 144 static void radeon_enc_flush_headers(struct radeon_encoder *enc)
 145 {
 146         if (enc->bits_in_shifter != 0) {
 147                 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 148                 radeon_enc_emulation_prevention(enc, output_byte);
 149                 radeon_enc_output_one_byte(enc, output_byte);
 150                 enc->bits_output += enc->bits_in_shifter;
 151                 enc->shifter = 0;
 152                 enc->bits_in_shifter = 0;
 153                 enc->num_zeros = 0;
 154         }
 155
 156         if (enc->byte_index > 0) {
 157                 enc->cs->current.cdw++;
 158                 enc->byte_index = 0;
 159         }
 160 }
 161
 162 static void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
 163 {
 164         int x = -1;
 165         unsigned int ue_code = value + 1;
 166         value += 1;
 167
 168         while (value) {
 169                 value = (value >> 1);
 170                 x += 1;
 171         }
 172
 173         unsigned int ue_length = (x << 1) + 1;
 174         radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
 175 }
 176
 177 static void radeon_enc_code_se(struct radeon_encoder *enc, int value)
 178 {
 179         unsigned int v = 0;
 180
 181         if (value != 0)
 182                 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
 183
 184         radeon_enc_code_ue(enc, v);
 185 }
 186
 187 static void radeon_enc_session_info(struct radeon_encoder *enc)
 188 {
 189         unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 190                                                                           (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 191         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
 192         RADEON_ENC_CS(interface_version);
 193         RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
 194         RADEON_ENC_END();
 195 }
 196
 197 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
 198 {
 199         enc->enc_pic.task_info.task_id++;
 200
 201         if (need_feedback)
 202                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
 203         else
 204                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
 205
 206         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
 207         enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
 208         RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
 209         RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
 210         RADEON_ENC_END();
 211 }
 212
 213 static void radeon_enc_session_init(struct radeon_encoder *enc)
 214 {
 215         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
 216         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
 217         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 218         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 219         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 220         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 221         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 222
 223         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 224         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 225         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 226         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 227         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 228         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 229         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 230         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 231         RADEON_ENC_END();
 232 }
 233
 234 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
 235 {
 236         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
 237         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
 238         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 239         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 240         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 241         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 242         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 243
 244         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 245         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 246         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 247         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 248         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 249         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 250         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 251         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 252         RADEON_ENC_END();
 253 }
 254
 255 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 256 {
 257         enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 258         enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 259
 260         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
 261         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 262         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 263         RADEON_ENC_END();
 264 }
 265
 266 static void radeon_enc_layer_select(struct radeon_encoder *enc)
 267 {
 268         enc->enc_pic.layer_sel.temporal_layer_index = 0;
 269
 270         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
 271         RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 272         RADEON_ENC_END();
 273 }
 274
 275 static void radeon_enc_slice_control(struct radeon_encoder *enc)
 276 {
 277         enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 278         enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
 279
 280         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
 281         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
 282         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
 283         RADEON_ENC_END();
 284 }
 285
 286 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
 287 {
 288         enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
 289         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 290         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 291
 292         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
 293         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 294         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
 295         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 296         RADEON_ENC_END();
 297 }
 298
 299 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 300 {
 301         enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
 302         enc->enc_pic.spec_misc.cabac_enable = 0;
 303         enc->enc_pic.spec_misc.cabac_init_idc = 0;
 304         enc->enc_pic.spec_misc.half_pel_enabled = 1;
 305         enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
 306         enc->enc_pic.spec_misc.profile_idc = profiles[enc->base.profile - PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE];
 307         enc->enc_pic.spec_misc.level_idc = enc->base.level;
 308
 309         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
 310         RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
 311         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
 312         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
 313         RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
 314         RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
 315         RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
 316         RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
 317         RADEON_ENC_END();
 318 }
 319
 320 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 321 {
 322         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 323         enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = pic->seq.log2_min_luma_coding_block_size_minus3;
 324         enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
 325         enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag;
 326         enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
 327         enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
 328         enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
 329         enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
 330
 331         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
 332         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 333         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 334         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 335         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 336         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 337         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 338         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 339         RADEON_ENC_END();
 340 }
 341
 342 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 343 {
 344         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 345                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 346                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
 347                 switch(pic->rate_ctrl.rate_ctrl_method) {
 348                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE:
 349                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 350                                 break;
 351                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 352                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT:
 353                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 354                                 break;
 355                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 356                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
 357                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 358                                 break;
 359                         default:
 360                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 361                 }
 362         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 363                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 364                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
 365                 switch(pic->rc.rate_ctrl_method) {
 366                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
 367                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 368                                 break;
 369                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 370                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
 371                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 372                                 break;
 373                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 374                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
 375                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 376                                 break;
 377                         default:
 378                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 379                 }
 380         }
 381
 382         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT);
 383         RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 384         RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 385         RADEON_ENC_END();
 386 }
 387
 388 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 389 {
 390         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 391                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 392                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate;
 393                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
 394                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num;
 395                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
 396                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
 397                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
 398                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer;
 399                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction;
 400         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 401                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 402                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
 403                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
 404                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
 405                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
 406                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
 407                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
 408                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
 409                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
 410         }
 411
 412         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT);
 413         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 414         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 415         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 416         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 417         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 418         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 419         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 420         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 421         RADEON_ENC_END();
 422 }
 423
 424 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
 425 {
 426         enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
 427         enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
 428         enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
 429         enc->enc_pic.h264_deblock.cb_qp_offset = 0;
 430         enc->enc_pic.h264_deblock.cr_qp_offset = 0;
 431
 432         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER);
 433         RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
 434         RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 435         RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
 436         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
 437         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
 438         RADEON_ENC_END();
 439 }
 440
 441 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 442 {
 443         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 444         enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
 445         enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
 446         enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
 447         enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
 448         enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
 449         enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
 450
 451         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER);
 452         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 453         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 454         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 455         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 456         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 457         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 458         RADEON_ENC_END();
 459 }
 460
 461 static void radeon_enc_quality_params(struct radeon_encoder *enc)
 462 {
 463         enc->enc_pic.quality_params.vbaq_mode = 0;
 464         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 465         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 466
 467         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS);
 468         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 469         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 470         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 471         RADEON_ENC_END();
 472 }
 473
 474 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
 475 {
 476         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 477         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 478         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 479         radeon_enc_reset(enc);
 480         radeon_enc_set_emulation_prevention(enc, false);
 481         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 482         radeon_enc_code_fixed_bits(enc, 0x67, 8);
 483         radeon_enc_byte_align(enc);
 484         radeon_enc_set_emulation_prevention(enc, true);
 485         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
 486         radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
 487         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
 488         radeon_enc_code_ue(enc, 0x0);
 489
 490         if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
 491                         enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
 492                         enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
 493                         enc->enc_pic.spec_misc.profile_idc == 138) {
 494                 radeon_enc_code_ue(enc, 0x1);
 495                 radeon_enc_code_ue(enc, 0x0);
 496                 radeon_enc_code_ue(enc, 0x0);
 497                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 498         }
 499
 500         radeon_enc_code_ue(enc, 1);
 501         radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
 502
 503         if (enc->enc_pic.pic_order_cnt_type == 0)
 504                 radeon_enc_code_ue(enc, 1);
 505
 506         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 507         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
 508         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
 509         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
 510         bool progressive_only = true;
 511         radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
 512
 513         if (!progressive_only)
 514                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 515
 516         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 517
 518         if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
 519                         (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
 520                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 521                 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
 522                 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
 523                 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
 524                 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 525         } else
 526                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 527
 528         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 529         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 530         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 531         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 532         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 533         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 534         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 535         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 536         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 537         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 538         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 539         radeon_enc_code_ue(enc, 0x0);
 540         radeon_enc_code_ue(enc, 0x0);
 541         radeon_enc_code_ue(enc, 16);
 542         radeon_enc_code_ue(enc, 16);
 543         radeon_enc_code_ue(enc, 0x0);
 544         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 545
 546         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 547
 548         radeon_enc_byte_align(enc);
 549         radeon_enc_flush_headers(enc);
 550         *size_in_bytes = (enc->bits_output + 7) / 8;
 551         RADEON_ENC_END();
 552 }
 553
 554 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 555 {
 556         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 557         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 558         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 559         int i;
 560
 561         radeon_enc_reset(enc);
 562         radeon_enc_set_emulation_prevention(enc, false);
 563         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 564         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 565         radeon_enc_byte_align(enc);
 566         radeon_enc_set_emulation_prevention(enc, true);
 567         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 568         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 569         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 570         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 571         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 572         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 573         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 574         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 575         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 576         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 577
 578         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 579                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 580
 581         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 582                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 583                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 584         }
 585
 586         radeon_enc_code_ue(enc, 0x0);
 587         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 588         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 589         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 590         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 591         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 592         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 593         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 594         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 595         radeon_enc_code_ue(enc, 1);
 596         radeon_enc_code_ue(enc, 0x0);
 597         radeon_enc_code_ue(enc, 0x0);
 598         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 599         //Only support CTBSize 64
 600         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 601         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 602         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 603         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 604         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 605
 606         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 607         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 608         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 609         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 610
 611         radeon_enc_code_ue(enc, 1);
 612         radeon_enc_code_ue(enc, 1);
 613         radeon_enc_code_ue(enc, 0);
 614         radeon_enc_code_ue(enc, 0);
 615         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 616
 617         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 618
 619         radeon_enc_code_fixed_bits(enc, 0, 1);
 620         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 621
 622         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 623
 624         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 625
 626         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 627
 628         radeon_enc_byte_align(enc);
 629         radeon_enc_flush_headers(enc);
 630         *size_in_bytes = (enc->bits_output + 7) / 8;
 631         RADEON_ENC_END();
 632 }
 633
 634 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 635 {
 636         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 637         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 638         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 639         radeon_enc_reset(enc);
 640         radeon_enc_set_emulation_prevention(enc, false);
 641         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 642         radeon_enc_code_fixed_bits(enc, 0x68, 8);
 643         radeon_enc_byte_align(enc);
 644         radeon_enc_set_emulation_prevention(enc, true);
 645         radeon_enc_code_ue(enc, 0x0);
 646         radeon_enc_code_ue(enc, 0x0);
 647         radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
 648         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 649         radeon_enc_code_ue(enc, 0x0);
 650         radeon_enc_code_ue(enc, 0x0);
 651         radeon_enc_code_ue(enc, 0x0);
 652         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 653         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 654         radeon_enc_code_se(enc, 0x0);
 655         radeon_enc_code_se(enc, 0x0);
 656         radeon_enc_code_se(enc, 0x0);
 657         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 658         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 659         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 660
 661         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 662
 663         radeon_enc_byte_align(enc);
 664         radeon_enc_flush_headers(enc);
 665         *size_in_bytes = (enc->bits_output + 7) / 8;
 666         RADEON_ENC_END();
 667 }
 668
 669 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 670 {
 671         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 672         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 673         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 674         radeon_enc_reset(enc);
 675         radeon_enc_set_emulation_prevention(enc, false);
 676         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 677         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 678         radeon_enc_byte_align(enc);
 679         radeon_enc_set_emulation_prevention(enc, true);
 680         radeon_enc_code_ue(enc, 0x0);
 681         radeon_enc_code_ue(enc, 0x0);
 682         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 683         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 684         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 685         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 686         radeon_enc_code_ue(enc, 0x0);
 687         radeon_enc_code_ue(enc, 0x0);
 688         radeon_enc_code_se(enc, 0x0);
 689         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 690         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 691         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 692         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 693         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 694         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 695         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 696         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 697         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 698         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 699         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 700         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 701         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 702         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 703
 704         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 705                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 706                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 707         }
 708
 709         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 710         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 711         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 712         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 713
 714         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 715
 716         radeon_enc_byte_align(enc);
 717         radeon_enc_flush_headers(enc);
 718         *size_in_bytes = (enc->bits_output + 7) / 8;
 719         RADEON_ENC_END();
 720 }
 721
 722 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
 723 {
 724         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 725         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
 726         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 727         int i;
 728
 729         radeon_enc_reset(enc);
 730         radeon_enc_set_emulation_prevention(enc, false);
 731         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 732         radeon_enc_code_fixed_bits(enc, 0x4001, 16);
 733         radeon_enc_byte_align(enc);
 734         radeon_enc_set_emulation_prevention(enc, true);
 735
 736         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 737         radeon_enc_code_fixed_bits(enc, 0x3, 2);
 738         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 739         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 740         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 741         radeon_enc_code_fixed_bits(enc, 0xffff, 16);
 742         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 743         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 744         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 745         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 746         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 747         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 748         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 749
 750         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 751                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 752
 753         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 754                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 755                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 756         }
 757
 758         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 759         radeon_enc_code_ue(enc, 0x1);
 760         radeon_enc_code_ue(enc, 0x0);
 761         radeon_enc_code_ue(enc, 0x0);
 762
 763         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 764         radeon_enc_code_ue(enc, 0x0);
 765         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 766         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 767
 768         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 769
 770         radeon_enc_byte_align(enc);
 771         radeon_enc_flush_headers(enc);
 772         *size_in_bytes = (enc->bits_output + 7) / 8;
 773         RADEON_ENC_END();
 774 }
 775
 776 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
 777 {
 778         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 779         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
 780         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 781         radeon_enc_reset(enc);
 782         radeon_enc_set_emulation_prevention(enc, false);
 783         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 784         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 785         radeon_enc_code_fixed_bits(enc, 35, 6);
 786         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 787         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 788         radeon_enc_byte_align(enc);
 789         radeon_enc_set_emulation_prevention(enc, true);
 790         switch(enc->enc_pic.picture_type) {
 791                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 792                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 793                         radeon_enc_code_fixed_bits(enc, 0x00, 3);
 794                         break;
 795                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 796                         radeon_enc_code_fixed_bits(enc, 0x01, 3);
 797                         break;
 798                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 799                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 800                         break;
 801                 default:
 802                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 803         }
 804
 805     radeon_enc_code_fixed_bits(enc, 0x1, 1);
 806
 807         radeon_enc_byte_align(enc);
 808         radeon_enc_flush_headers(enc);
 809         *size_in_bytes = (enc->bits_output + 7) / 8;
 810         RADEON_ENC_END();
 811 }
 812
 813 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 814 {
 815         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 816         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 817         unsigned int inst_index = 0;
 818         unsigned int bit_index = 0;
 819         unsigned int bits_copied = 0;
 820         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 821         radeon_enc_reset(enc);
 822         radeon_enc_set_emulation_prevention(enc, false);
 823
 824         if (enc->enc_pic.is_idr)
 825                 radeon_enc_code_fixed_bits(enc, 0x65, 8);
 826         else if (enc->enc_pic.not_referenced)
 827                 radeon_enc_code_fixed_bits(enc, 0x01, 8);
 828         else
 829                 radeon_enc_code_fixed_bits(enc, 0x41, 8);
 830
 831         radeon_enc_flush_headers(enc);
 832         bit_index ++;
 833         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 834         num_bits[inst_index] = enc->bits_output - bits_copied;
 835         bits_copied = enc->bits_output;
 836         inst_index++;
 837
 838         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
 839         inst_index++;
 840
 841         switch(enc->enc_pic.picture_type) {
 842                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 843                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 844                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 845                         break;
 846                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 847                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 848                         radeon_enc_code_fixed_bits(enc, 0x06, 5);
 849                         break;
 850                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 851                         radeon_enc_code_fixed_bits(enc, 0x07, 5);
 852                         break;
 853                 default:
 854                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 855         }
 856
 857         radeon_enc_code_ue(enc, 0x0);
 858         radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
 859
 860         if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
 861                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 862                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
 863         }
 864
 865         if (enc->enc_pic.is_idr)
 866                 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
 867
 868         enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
 869
 870         if (enc->enc_pic.pic_order_cnt_type == 0)
 871                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
 872
 873         if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
 874                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 875
 876                 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
 877                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 878                         radeon_enc_code_ue(enc, 0x0);
 879                         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
 880                         radeon_enc_code_ue(enc, 0x3);
 881                 } else
 882                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 883         }
 884
 885         if (enc->enc_pic.is_idr) {
 886                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 887                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 888         } else
 889                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 890
 891         if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
 892                 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
 893
 894         radeon_enc_flush_headers(enc);
 895         bit_index ++;
 896         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 897         num_bits[inst_index] = enc->bits_output - bits_copied;
 898         bits_copied = enc->bits_output;
 899         inst_index++;
 900
 901         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 902         inst_index++;
 903
 904         radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
 905
 906         if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
 907                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 908                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
 909         }
 910
 911         radeon_enc_flush_headers(enc);
 912         bit_index ++;
 913         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 914         num_bits[inst_index] = enc->bits_output - bits_copied;
 915         bits_copied = enc->bits_output;
 916         inst_index++;
 917
 918         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 919
 920         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 921                 RADEON_ENC_CS(0x00000000);
 922
 923         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 924                 RADEON_ENC_CS(instruction[j]);
 925                 RADEON_ENC_CS(num_bits[j]);
 926         }
 927
 928         RADEON_ENC_END();
 929 }
 930
 931 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 932 {
 933         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 934         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 935         unsigned int inst_index = 0;
 936         unsigned int bit_index = 0;
 937         unsigned int bits_copied = 0;
 938         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 939         radeon_enc_reset(enc);
 940         radeon_enc_set_emulation_prevention(enc, false);
 941
 942         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 943         radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
 944         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 945         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 946
 947         radeon_enc_flush_headers(enc);
 948         bit_index ++;
 949         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 950         num_bits[inst_index] = enc->bits_output - bits_copied;
 951         bits_copied = enc->bits_output;
 952         inst_index++;
 953
 954         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
 955         inst_index++;
 956
 957         if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
 958                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 959
 960         radeon_enc_code_ue(enc, 0x0);
 961
 962         radeon_enc_flush_headers(enc);
 963         bit_index ++;
 964         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 965         num_bits[inst_index] = enc->bits_output - bits_copied;
 966         bits_copied = enc->bits_output;
 967         inst_index++;
 968
 969         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
 970         inst_index++;
 971
 972         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
 973         inst_index++;
 974
 975         switch(enc->enc_pic.picture_type) {
 976                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 977                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 978                         radeon_enc_code_ue(enc, 0x2);
 979                         break;
 980                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 981                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 982                         radeon_enc_code_ue(enc, 0x1);
 983                         break;
 984                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 985                         radeon_enc_code_ue(enc, 0x0);
 986                         break;
 987                 default:
 988                         radeon_enc_code_ue(enc, 0x1);
 989         }
 990
 991         if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
 992                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
 993                 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
 994                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 995                 else {
 996                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 997                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 998                         radeon_enc_code_ue(enc, 0x0);
 999                         radeon_enc_code_ue(enc, 0x0);
1000                 }
1001         }
1002
1003         if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
1004                 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
1005                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1006                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
1007                 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
1008         }
1009
1010         radeon_enc_flush_headers(enc);
1011         bit_index ++;
1012         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1013         num_bits[inst_index] = enc->bits_output - bits_copied;
1014         bits_copied = enc->bits_output;
1015         inst_index++;
1016
1017         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1018         inst_index++;
1019
1020         if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
1021                 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)){
1022                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
1023
1024                 radeon_enc_flush_headers(enc);
1025                 bit_index ++;
1026                 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1027                 num_bits[inst_index] = enc->bits_output - bits_copied;
1028                 bits_copied = enc->bits_output;
1029                 inst_index++;
1030         }
1031
1032         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1033
1034         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
1035                 RADEON_ENC_CS(0x00000000);
1036
1037         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1038                 RADEON_ENC_CS(instruction[j]);
1039                 RADEON_ENC_CS(num_bits[j]);
1040         }
1041
1042         RADEON_ENC_END();
1043 }
1044
1045 static void radeon_enc_ctx(struct radeon_encoder *enc)
1046 {
1047         enc->enc_pic.ctx_buf.swizzle_mode = 0;
1048         enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
1049         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
1050         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
1051
1052         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER);
1053         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
1054         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1055         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1056         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1057         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1058         /* reconstructed_picture_1_luma_offset */
1059         RADEON_ENC_CS(0x00000000);
1060         /* reconstructed_picture_1_chroma_offset */
1061         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
1062         /* reconstructed_picture_2_luma_offset */
1063         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
1064         /* reconstructed_picture_2_chroma_offset */
1065         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
1066
1067         for (int i = 0; i < 136 ; i++)
1068                 RADEON_ENC_CS(0x00000000);
1069
1070         RADEON_ENC_END();
1071 }
1072
1073 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1074 {
1075         enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1076         enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1077         enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
1078
1079         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
1080         RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1081         RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1082         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1083         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1084         RADEON_ENC_END();
1085 }
1086
1087 static void radeon_enc_feedback(struct radeon_encoder *enc)
1088 {
1089         enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1090         enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1091         enc->enc_pic.fb_buf.feedback_data_size = 40;
1092
1093         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER);
1094         RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1095         RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1096         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1097         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1098         RADEON_ENC_END();
1099 }
1100
1101 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1102 {
1103         enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
1104         enc->enc_pic.intra_ref.offset = 0;
1105         enc->enc_pic.intra_ref.region_size = 0;
1106
1107         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH);
1108         RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
1109         RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
1110         RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
1111         RADEON_ENC_END();
1112 }
1113
1114 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
1115 {
1116         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1117                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
1118                 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
1119                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
1120                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
1121                 enc->enc_pic.rc_per_pic.max_au_size = 0;
1122                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable;
1123                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
1124                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd;
1125         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1126                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
1127                 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
1128                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
1129                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
1130                 enc->enc_pic.rc_per_pic.max_au_size = 0;
1131                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
1132                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
1133                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
1134         }
1135
1136         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE);
1137         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
1138         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
1139         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
1140         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
1141         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1142         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1143         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1144         RADEON_ENC_END();
1145 }
1146
1147 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1148 {
1149         switch(enc->enc_pic.picture_type) {
1150                 case PIPE_H264_ENC_PICTURE_TYPE_I:
1151                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
1152                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1153                         break;
1154                 case PIPE_H264_ENC_PICTURE_TYPE_P:
1155                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1156                         break;
1157                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
1158                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1159                         break;
1160                 case PIPE_H264_ENC_PICTURE_TYPE_B:
1161                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1162                         break;
1163                 default:
1164                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1165         }
1166
1167         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1168         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1169         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1170         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1171
1172         if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
1173                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1174         else
1175                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1176
1177         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1178
1179         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1180         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1181         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1182         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1183         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1184         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1185         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1186         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1187         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1188         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1189         RADEON_ENC_END();
1190 }
1191
1192 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1193 {
1194         switch(enc->enc_pic.picture_type) {
1195                 case PIPE_H265_ENC_PICTURE_TYPE_I:
1196                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
1197                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1198                         break;
1199                 case PIPE_H265_ENC_PICTURE_TYPE_P:
1200                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1201                         break;
1202                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
1203                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1204                         break;
1205                 case PIPE_H265_ENC_PICTURE_TYPE_B:
1206                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1207                         break;
1208                 default:
1209                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1210         }
1211
1212         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1213         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1214         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1215         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1216
1217         if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1218                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1219         else
1220                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1221
1222         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1223
1224         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1225         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1226         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1227         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1228         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1229         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1230         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1231         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1232         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1233         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1234         RADEON_ENC_END();
1235 }
1236
1237 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1238 {
1239         enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1240         enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1241         enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1242         enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1243
1244         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS);
1245         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1246         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1247         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1248         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1249         RADEON_ENC_END();
1250 }
1251
1252 static void radeon_enc_op_init(struct radeon_encoder *enc)
1253 {
1254         RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1255         RADEON_ENC_END();
1256 }
1257
1258 static void radeon_enc_op_close(struct radeon_encoder *enc)
1259 {
1260         RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1261         RADEON_ENC_END();
1262 }
1263
1264 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1265 {
1266         RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1267         RADEON_ENC_END();
1268 }
1269
1270 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1271 {
1272         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1273         RADEON_ENC_END();
1274 }
1275
1276 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1277 {
1278         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1279         RADEON_ENC_END();
1280 }
1281
1282 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1283 {
1284         RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1285         RADEON_ENC_END();
1286 }
1287
1288 static void begin(struct radeon_encoder *enc, struct pipe_picture_desc *pic)
1289 {
1290         radeon_enc_session_info(enc);
1291         enc->total_task_size = 0;
1292         radeon_enc_task_info(enc, enc->need_feedback);
1293         radeon_enc_op_init(enc);
1294
1295         if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1296                 radeon_enc_session_init(enc);
1297                 radeon_enc_slice_control(enc);
1298                 radeon_enc_spec_misc(enc);
1299                 radeon_enc_deblocking_filter_h264(enc);
1300         } else if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1301                 radeon_enc_session_init_hevc(enc);
1302                 radeon_enc_slice_control_hevc(enc);
1303                 radeon_enc_spec_misc_hevc(enc, pic);
1304                 radeon_enc_deblocking_filter_hevc(enc, pic);
1305         }
1306
1307         radeon_enc_layer_control(enc);
1308         radeon_enc_rc_session_init(enc, pic);
1309         radeon_enc_quality_params(enc);
1310         radeon_enc_layer_select(enc);
1311         radeon_enc_rc_layer_init(enc, pic);
1312         radeon_enc_layer_select(enc);
1313         radeon_enc_rc_per_pic(enc, pic);
1314         radeon_enc_op_init_rc(enc);
1315         radeon_enc_op_init_rc_vbv(enc);
1316         *enc->p_task_size = (enc->total_task_size);
1317 }
1318
1319 static void encode(struct radeon_encoder *enc)
1320 {
1321         radeon_enc_session_info(enc);
1322         enc->total_task_size = 0;
1323         radeon_enc_task_info(enc, enc->need_feedback);
1324
1325         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1326                 if (enc->enc_pic.is_idr) {
1327                         radeon_enc_nalu_sps(enc);
1328                         radeon_enc_nalu_pps(enc);
1329                 }
1330                 radeon_enc_slice_header(enc);
1331                 radeon_enc_encode_params(enc);
1332                 radeon_enc_encode_params_h264(enc);
1333         } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1334                 radeon_enc_nalu_aud_hevc(enc);
1335                 if (enc->enc_pic.is_idr) {
1336                         radeon_enc_nalu_vps(enc);
1337                         radeon_enc_nalu_pps_hevc(enc);
1338                         radeon_enc_nalu_sps_hevc(enc);
1339                 }
1340                 radeon_enc_slice_header_hevc(enc);
1341                 radeon_enc_encode_params_hevc(enc);
1342         }
1343
1344         radeon_enc_ctx(enc);
1345         radeon_enc_bitstream(enc);
1346         radeon_enc_feedback(enc);
1347         radeon_enc_intra_refresh(enc);
1348
1349         radeon_enc_op_speed(enc);
1350         radeon_enc_op_enc(enc);
1351         *enc->p_task_size = (enc->total_task_size);
1352 }
1353
1354 static void destroy(struct radeon_encoder *enc)
1355 {
1356         radeon_enc_session_info(enc);
1357         enc->total_task_size = 0;
1358         radeon_enc_task_info(enc, enc->need_feedback);
1359         radeon_enc_op_close(enc);
1360         *enc->p_task_size = (enc->total_task_size);
1361 }
1362
1363 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1364 {
1365         enc->begin = begin;
1366         enc->encode = encode;
1367         enc->destroy = destroy;
1368 }