src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33 #include "util/u_memory.h"
  34
  35 #include "vl/vl_video_buffer.h"
  36
  37 #include "r600_pipe_common.h"
  38 #include "radeon_video.h"
  39 #include "radeon_vcn_enc.h"
  40
  41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
  42 #define RADEON_ENC_BEGIN(cmd) { \
  43         uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
  44 RADEON_ENC_CS(cmd)
  45 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
  46 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
  47 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
  48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
  49         enc->total_task_size += *begin;}
  50
  51 static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
  52 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
  53
  54 static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
  55                                                                   enum radeon_bo_usage usage, enum radeon_bo_domain domain,
  56                                                                   signed offset)
  57 {
  58         enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
  59                                                                            domain, RADEON_PRIO_VCE);
  60         uint64_t addr;
  61         addr = enc->ws->buffer_get_virtual_address(buf);
  62         addr = addr + offset;
  63         RADEON_ENC_CS(addr >> 32);
  64         RADEON_ENC_CS(addr);
  65 }
  66
  67 static void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
  68 {
  69         if (set != enc->emulation_prevention) {
  70                 enc->emulation_prevention = set;
  71                 enc->num_zeros = 0;
  72         }
  73 }
  74
  75 static void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
  76 {
  77         if (enc->byte_index == 0)
  78                 enc->cs->current.buf[enc->cs->current.cdw] = 0;
  79         enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
  80         enc->byte_index++;
  81
  82         if (enc->byte_index >= 4) {
  83                 enc->byte_index = 0;
  84                 enc->cs->current.cdw++;
  85         }
  86 }
  87
  88 static void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
  89 {
  90         if(enc->emulation_prevention) {
  91                 if((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
  92             radeon_enc_output_one_byte(enc, 0x03);
  93             enc->bits_output += 8;
  94             enc->num_zeros = 0;
  95         }
  96         enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
  97     }
  98 }
  99
 100 static void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, unsigned int num_bits)
 101 {
 102         unsigned int bits_to_pack = 0;
 103
 104         while(num_bits > 0) {
 105                 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
 106                 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
 107
 108                 if (bits_to_pack < num_bits)
 109                         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
 110
 111                 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
 112                 num_bits -= bits_to_pack;
 113                 enc->bits_in_shifter += bits_to_pack;
 114
 115                 while(enc->bits_in_shifter >= 8) {
 116                         unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 117                         enc->shifter <<= 8;
 118                         radeon_enc_emulation_prevention(enc, output_byte);
 119                         radeon_enc_output_one_byte(enc, output_byte);
 120                         enc->bits_in_shifter -= 8;
 121                         enc->bits_output += 8;
 122                 }
 123         }
 124 }
 125
 126 static void radeon_enc_reset(struct radeon_encoder *enc)
 127 {
 128         enc->emulation_prevention = false;
 129         enc->shifter = 0;
 130         enc->bits_in_shifter = 0;
 131         enc->bits_output = 0;
 132         enc->num_zeros = 0;
 133         enc->byte_index = 0;
 134 }
 135
 136 static void radeon_enc_byte_align(struct radeon_encoder *enc)
 137 {
 138         unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
 139
 140         if (num_padding_zeros > 0)
 141                 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
 142 }
 143
 144 static void radeon_enc_flush_headers(struct radeon_encoder *enc)
 145 {
 146         if (enc->bits_in_shifter != 0) {
 147                 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 148                 radeon_enc_emulation_prevention(enc, output_byte);
 149                 radeon_enc_output_one_byte(enc, output_byte);
 150                 enc->bits_output += enc->bits_in_shifter;
 151                 enc->shifter = 0;
 152                 enc->bits_in_shifter = 0;
 153                 enc->num_zeros = 0;
 154         }
 155
 156         if (enc->byte_index > 0) {
 157                 enc->cs->current.cdw++;
 158                 enc->byte_index = 0;
 159         }
 160 }
 161
 162 static void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
 163 {
 164         int x = -1;
 165         unsigned int ue_code = value + 1;
 166         value += 1;
 167
 168         while (value) {
 169                 value = (value >> 1);
 170                 x += 1;
 171         }
 172
 173         unsigned int ue_length = (x << 1) + 1;
 174         radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
 175 }
 176
 177 static void radeon_enc_code_se(struct radeon_encoder *enc, int value)
 178 {
 179         unsigned int v = 0;
 180
 181         if (value != 0)
 182                 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
 183
 184         radeon_enc_code_ue(enc, v);
 185 }
 186
 187 static void radeon_enc_session_info(struct radeon_encoder *enc)
 188 {
 189         unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 190                                                                           (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 191         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
 192         RADEON_ENC_CS(interface_version);
 193         RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
 194         RADEON_ENC_END();
 195 }
 196
 197 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
 198 {
 199         enc->enc_pic.task_info.task_id++;
 200
 201         if (need_feedback)
 202                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
 203         else
 204                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
 205
 206         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
 207         enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
 208         RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
 209         RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
 210         RADEON_ENC_END();
 211 }
 212
 213 static void radeon_enc_session_init(struct radeon_encoder *enc)
 214 {
 215         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
 216         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
 217         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 218         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 219         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 220         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 221         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 222
 223         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 224         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 225         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 226         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 227         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 228         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 229         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 230         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 231         RADEON_ENC_END();
 232 }
 233
 234 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
 235 {
 236         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
 237         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
 238         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 239         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 240         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 241         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 242         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 243
 244         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 245         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 246         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 247         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 248         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 249         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 250         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 251         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 252         RADEON_ENC_END();
 253 }
 254
 255 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 256 {
 257         enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 258         enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 259
 260         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
 261         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 262         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 263         RADEON_ENC_END();
 264 }
 265
 266 static void radeon_enc_layer_select(struct radeon_encoder *enc)
 267 {
 268         enc->enc_pic.layer_sel.temporal_layer_index = 0;
 269
 270         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
 271         RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 272         RADEON_ENC_END();
 273 }
 274
 275 static void radeon_enc_slice_control(struct radeon_encoder *enc)
 276 {
 277         enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 278         enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
 279
 280         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
 281         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
 282         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
 283         RADEON_ENC_END();
 284 }
 285
 286 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
 287 {
 288         enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
 289         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 290         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 291
 292         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
 293         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 294         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
 295         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 296         RADEON_ENC_END();
 297 }
 298
 299 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 300 {
 301         enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
 302         enc->enc_pic.spec_misc.cabac_enable = 0;
 303         enc->enc_pic.spec_misc.cabac_init_idc = 0;
 304         enc->enc_pic.spec_misc.half_pel_enabled = 1;
 305         enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
 306         enc->enc_pic.spec_misc.profile_idc = profiles[enc->base.profile - PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE];
 307         enc->enc_pic.spec_misc.level_idc = enc->base.level;
 308
 309         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
 310         RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
 311         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
 312         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
 313         RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
 314         RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
 315         RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
 316         RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
 317         RADEON_ENC_END();
 318 }
 319
 320 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 321 {
 322         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 323         enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = pic->seq.log2_min_luma_coding_block_size_minus3;
 324         enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
 325         enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag;
 326         enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
 327         enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
 328         enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
 329         enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
 330
 331         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
 332         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 333         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 334         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 335         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 336         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 337         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 338         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 339         RADEON_ENC_END();
 340 }
 341
 342 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 343 {
 344         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 345                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 346                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
 347                 switch(pic->rate_ctrl.rate_ctrl_method) {
 348                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE:
 349                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 350                                 break;
 351                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 352                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT:
 353                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 354                                 break;
 355                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 356                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
 357                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 358                                 break;
 359                         default:
 360                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 361                 }
 362         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 363                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 364                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
 365                 switch(pic->rc.rate_ctrl_method) {
 366                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
 367                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 368                                 break;
 369                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 370                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
 371                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 372                                 break;
 373                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 374                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
 375                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 376                                 break;
 377                         default:
 378                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 379                 }
 380         }
 381
 382         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT);
 383         RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 384         RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 385         RADEON_ENC_END();
 386 }
 387
 388 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 389 {
 390         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 391                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 392                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate;
 393                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
 394                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num;
 395                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
 396                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
 397                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
 398                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer;
 399                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction;
 400         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 401                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 402                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
 403                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
 404                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
 405                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
 406                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
 407                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
 408                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
 409                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
 410         }
 411
 412         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT);
 413         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 414         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 415         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 416         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 417         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 418         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 419         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 420         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 421         RADEON_ENC_END();
 422 }
 423
 424 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
 425 {
 426         enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
 427         enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
 428         enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
 429         enc->enc_pic.h264_deblock.cb_qp_offset = 0;
 430         enc->enc_pic.h264_deblock.cr_qp_offset = 0;
 431
 432         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER);
 433         RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
 434         RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 435         RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
 436         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
 437         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
 438         RADEON_ENC_END();
 439 }
 440
 441 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 442 {
 443         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 444         enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
 445         enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
 446         enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
 447         enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
 448         enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
 449         enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
 450
 451         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER);
 452         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 453         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 454         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 455         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 456         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 457         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 458         RADEON_ENC_END();
 459 }
 460
 461 static void radeon_enc_quality_params(struct radeon_encoder *enc)
 462 {
 463         enc->enc_pic.quality_params.vbaq_mode = 0;
 464         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 465         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 466
 467         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS);
 468         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 469         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 470         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 471         RADEON_ENC_END();
 472 }
 473
 474 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
 475 {
 476         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 477         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 478         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 479         radeon_enc_reset(enc);
 480         radeon_enc_set_emulation_prevention(enc, false);
 481         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 482         radeon_enc_code_fixed_bits(enc, 0x67, 8);
 483         radeon_enc_byte_align(enc);
 484         radeon_enc_set_emulation_prevention(enc, true);
 485         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
 486         radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
 487         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
 488         radeon_enc_code_ue(enc, 0x0);
 489
 490         if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
 491                         enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
 492                         enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
 493                         enc->enc_pic.spec_misc.profile_idc == 138) {
 494                 radeon_enc_code_ue(enc, 0x1);
 495                 radeon_enc_code_ue(enc, 0x0);
 496                 radeon_enc_code_ue(enc, 0x0);
 497                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 498         }
 499
 500         radeon_enc_code_ue(enc, 1);
 501         radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
 502
 503         if (enc->enc_pic.pic_order_cnt_type == 0)
 504                 radeon_enc_code_ue(enc, 1);
 505
 506         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 507         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
 508         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
 509         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
 510         bool progressive_only = true;
 511         radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
 512
 513         if (!progressive_only)
 514                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 515
 516         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 517
 518         if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
 519                         (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
 520                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 521                 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
 522                 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
 523                 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
 524                 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 525         } else
 526                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 527
 528         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 529         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 530         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 531         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 532         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 533         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 534         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 535         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 536         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 537         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 538         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 539         radeon_enc_code_ue(enc, 0x0);
 540         radeon_enc_code_ue(enc, 0x0);
 541         radeon_enc_code_ue(enc, 16);
 542         radeon_enc_code_ue(enc, 16);
 543         radeon_enc_code_ue(enc, 0x0);
 544         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 545
 546         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 547
 548         radeon_enc_byte_align(enc);
 549         radeon_enc_flush_headers(enc);
 550         *size_in_bytes = (enc->bits_output + 7) / 8;
 551         RADEON_ENC_END();
 552 }
 553
 554 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 555 {
 556         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 557         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 558         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 559         radeon_enc_reset(enc);
 560         radeon_enc_set_emulation_prevention(enc, false);
 561         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 562         radeon_enc_code_fixed_bits(enc, 0x68, 8);
 563         radeon_enc_byte_align(enc);
 564         radeon_enc_set_emulation_prevention(enc, true);
 565         radeon_enc_code_ue(enc, 0x0);
 566         radeon_enc_code_ue(enc, 0x0);
 567         radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
 568         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 569         radeon_enc_code_ue(enc, 0x0);
 570         radeon_enc_code_ue(enc, 0x0);
 571         radeon_enc_code_ue(enc, 0x0);
 572         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 573         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 574         radeon_enc_code_se(enc, 0x0);
 575         radeon_enc_code_se(enc, 0x0);
 576         radeon_enc_code_se(enc, 0x0);
 577         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 578         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 579         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 580
 581         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 582
 583         radeon_enc_byte_align(enc);
 584         radeon_enc_flush_headers(enc);
 585         *size_in_bytes = (enc->bits_output + 7) / 8;
 586         RADEON_ENC_END();
 587 }
 588
 589 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 590 {
 591         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 592         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 593         unsigned int inst_index = 0;
 594         unsigned int bit_index = 0;
 595         unsigned int bits_copied = 0;
 596         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 597         radeon_enc_reset(enc);
 598         radeon_enc_set_emulation_prevention(enc, false);
 599
 600         if (enc->enc_pic.is_idr)
 601                 radeon_enc_code_fixed_bits(enc, 0x65, 8);
 602         else if (enc->enc_pic.not_referenced)
 603                 radeon_enc_code_fixed_bits(enc, 0x01, 8);
 604         else
 605                 radeon_enc_code_fixed_bits(enc, 0x41, 8);
 606
 607         radeon_enc_flush_headers(enc);
 608         bit_index ++;
 609         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 610         num_bits[inst_index] = enc->bits_output - bits_copied;
 611         bits_copied = enc->bits_output;
 612         inst_index++;
 613
 614         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
 615         inst_index++;
 616
 617         switch(enc->enc_pic.picture_type) {
 618                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 619                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 620                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 621                         break;
 622                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 623                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 624                         radeon_enc_code_fixed_bits(enc, 0x06, 5);
 625                         break;
 626                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 627                         radeon_enc_code_fixed_bits(enc, 0x07, 5);
 628                         break;
 629                 default:
 630                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 631         }
 632
 633         radeon_enc_code_ue(enc, 0x0);
 634         radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
 635
 636         if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
 637                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 638                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
 639         }
 640
 641         if (enc->enc_pic.is_idr)
 642                 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
 643
 644         enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
 645
 646         if (enc->enc_pic.pic_order_cnt_type == 0)
 647                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
 648
 649         if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
 650                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 651
 652                 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
 653                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 654                         radeon_enc_code_ue(enc, 0x0);
 655                         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
 656                         radeon_enc_code_ue(enc, 0x3);
 657                 } else
 658                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 659         }
 660
 661         if (enc->enc_pic.is_idr) {
 662                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 663                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 664         } else
 665                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 666
 667         if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
 668                 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
 669
 670         radeon_enc_flush_headers(enc);
 671         bit_index ++;
 672         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 673         num_bits[inst_index] = enc->bits_output - bits_copied;
 674         bits_copied = enc->bits_output;
 675         inst_index++;
 676
 677         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 678         inst_index++;
 679
 680         radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
 681
 682         if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
 683                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 684                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
 685         }
 686
 687         radeon_enc_flush_headers(enc);
 688         bit_index ++;
 689         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 690         num_bits[inst_index] = enc->bits_output - bits_copied;
 691         bits_copied = enc->bits_output;
 692         inst_index++;
 693
 694         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 695
 696         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 697                 RADEON_ENC_CS(0x00000000);
 698
 699         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 700                 RADEON_ENC_CS(instruction[j]);
 701                 RADEON_ENC_CS(num_bits[j]);
 702         }
 703
 704         RADEON_ENC_END();
 705 }
 706
 707 static void radeon_enc_ctx(struct radeon_encoder *enc)
 708 {
 709         enc->enc_pic.ctx_buf.swizzle_mode = 0;
 710         enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
 711         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
 712         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 713
 714         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER);
 715         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 716         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 717         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 718         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 719         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 720         /* reconstructed_picture_1_luma_offset */
 721         RADEON_ENC_CS(0x00000000);
 722         /* reconstructed_picture_1_chroma_offset */
 723         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
 724         /* reconstructed_picture_2_luma_offset */
 725         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
 726         /* reconstructed_picture_2_chroma_offset */
 727         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
 728
 729         for (int i = 0; i < 136 ; i++)
 730                 RADEON_ENC_CS(0x00000000);
 731
 732         RADEON_ENC_END();
 733 }
 734
 735 static void radeon_enc_bitstream(struct radeon_encoder *enc)
 736 {
 737         enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
 738         enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
 739         enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
 740
 741         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
 742         RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
 743         RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
 744         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
 745         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
 746         RADEON_ENC_END();
 747 }
 748
 749 static void radeon_enc_feedback(struct radeon_encoder *enc)
 750 {
 751         enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
 752         enc->enc_pic.fb_buf.feedback_buffer_size = 16;
 753         enc->enc_pic.fb_buf.feedback_data_size = 40;
 754
 755         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER);
 756         RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
 757         RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
 758         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
 759         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
 760         RADEON_ENC_END();
 761 }
 762
 763 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
 764 {
 765         enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
 766         enc->enc_pic.intra_ref.offset = 0;
 767         enc->enc_pic.intra_ref.region_size = 0;
 768
 769         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH);
 770         RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
 771         RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
 772         RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
 773         RADEON_ENC_END();
 774 }
 775
 776 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 777 {
 778         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 779                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 780                 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
 781                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
 782                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
 783                 enc->enc_pic.rc_per_pic.max_au_size = 0;
 784                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable;
 785                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
 786                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd;
 787         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 788                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 789                 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
 790                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
 791                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
 792                 enc->enc_pic.rc_per_pic.max_au_size = 0;
 793                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
 794                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
 795                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
 796         }
 797
 798         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE);
 799         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
 800         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
 801         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
 802         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
 803         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
 804         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
 805         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
 806         RADEON_ENC_END();
 807 }
 808
 809 static void radeon_enc_encode_params(struct radeon_encoder *enc)
 810 {
 811         switch(enc->enc_pic.picture_type) {
 812                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 813                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 814                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 815                         break;
 816                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 817                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
 818                         break;
 819                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 820                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
 821                         break;
 822                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 823                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
 824                         break;
 825                 default:
 826                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 827         }
 828
 829         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
 830         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
 831         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
 832         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
 833
 834         if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
 835                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
 836         else
 837                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
 838
 839         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
 840
 841         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
 842         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
 843         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
 844         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
 845         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
 846         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
 847         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
 848         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
 849         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
 850         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
 851         RADEON_ENC_END();
 852 }
 853
 854 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
 855 {
 856         switch(enc->enc_pic.picture_type) {
 857                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 858                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 859                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 860                         break;
 861                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 862                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
 863                         break;
 864                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 865                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
 866                         break;
 867                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 868                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
 869                         break;
 870                 default:
 871                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 872         }
 873
 874         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
 875         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
 876         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
 877         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
 878
 879         if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
 880                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
 881         else
 882                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
 883
 884         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
 885
 886         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
 887         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
 888         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
 889         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
 890         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
 891         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
 892         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
 893         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
 894         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
 895         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
 896         RADEON_ENC_END();
 897 }
 898
 899 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
 900 {
 901         enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
 902         enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
 903         enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
 904         enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
 905
 906         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS);
 907         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
 908         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
 909         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
 910         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
 911         RADEON_ENC_END();
 912 }
 913
 914 static void radeon_enc_op_init(struct radeon_encoder *enc)
 915 {
 916         RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
 917         RADEON_ENC_END();
 918 }
 919
 920 static void radeon_enc_op_close(struct radeon_encoder *enc)
 921 {
 922         RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
 923         RADEON_ENC_END();
 924 }
 925
 926 static void radeon_enc_op_enc(struct radeon_encoder *enc)
 927 {
 928         RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
 929         RADEON_ENC_END();
 930 }
 931
 932 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
 933 {
 934         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
 935         RADEON_ENC_END();
 936 }
 937
 938 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
 939 {
 940         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
 941         RADEON_ENC_END();
 942 }
 943
 944 static void radeon_enc_op_speed(struct radeon_encoder *enc)
 945 {
 946         RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
 947         RADEON_ENC_END();
 948 }
 949
 950 static void begin(struct radeon_encoder *enc, struct pipe_picture_desc *pic)
 951 {
 952         radeon_enc_session_info(enc);
 953         enc->total_task_size = 0;
 954         radeon_enc_task_info(enc, enc->need_feedback);
 955         radeon_enc_op_init(enc);
 956
 957         if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 958                 radeon_enc_session_init(enc);
 959                 radeon_enc_slice_control(enc);
 960                 radeon_enc_spec_misc(enc);
 961                 radeon_enc_deblocking_filter_h264(enc);
 962         } else if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 963                 radeon_enc_session_init_hevc(enc);
 964                 radeon_enc_slice_control_hevc(enc);
 965                 radeon_enc_spec_misc_hevc(enc, pic);
 966                 radeon_enc_deblocking_filter_hevc(enc, pic);
 967         }
 968
 969         radeon_enc_layer_control(enc);
 970         radeon_enc_rc_session_init(enc, pic);
 971         radeon_enc_quality_params(enc);
 972         radeon_enc_layer_select(enc);
 973         radeon_enc_rc_layer_init(enc, pic);
 974         radeon_enc_layer_select(enc);
 975         radeon_enc_rc_per_pic(enc, pic);
 976         radeon_enc_op_init_rc(enc);
 977         radeon_enc_op_init_rc_vbv(enc);
 978         *enc->p_task_size = (enc->total_task_size);
 979 }
 980
 981 static void encode(struct radeon_encoder *enc)
 982 {
 983         radeon_enc_session_info(enc);
 984         enc->total_task_size = 0;
 985         radeon_enc_task_info(enc, enc->need_feedback);
 986
 987         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 988                 if (enc->enc_pic.is_idr) {
 989                         radeon_enc_nalu_sps(enc);
 990                         radeon_enc_nalu_pps(enc);
 991                 }
 992                 radeon_enc_slice_header(enc);
 993                 radeon_enc_encode_params(enc);
 994                 radeon_enc_encode_params_h264(enc);
 995         } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)
 996                 radeon_enc_encode_params_hevc(enc);
 997
 998         radeon_enc_ctx(enc);
 999         radeon_enc_bitstream(enc);
1000         radeon_enc_feedback(enc);
1001         radeon_enc_intra_refresh(enc);
1002
1003         radeon_enc_op_speed(enc);
1004         radeon_enc_op_enc(enc);
1005         *enc->p_task_size = (enc->total_task_size);
1006 }
1007
1008 static void destroy(struct radeon_encoder *enc)
1009 {
1010         radeon_enc_session_info(enc);
1011         enc->total_task_size = 0;
1012         radeon_enc_task_info(enc, enc->need_feedback);
1013         radeon_enc_op_close(enc);
1014         *enc->p_task_size = (enc->total_task_size);
1015 }
1016
1017 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1018 {
1019         enc->begin = begin;
1020         enc->encode = encode;
1021         enc->destroy = destroy;
1022 }