src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33
  34 #include "si_pipe.h"
  35 #include "radeon_video.h"
  36 #include "radeon_vcn_enc.h"
  37
  38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION              1
  39 #define RENCODE_FW_INTERFACE_MINOR_VERSION              2
  40
  41 #define RENCODE_IB_PARAM_SESSION_INFO                           0x00000001
  42 #define RENCODE_IB_PARAM_TASK_INFO                              0x00000002
  43 #define RENCODE_IB_PARAM_SESSION_INIT                           0x00000003
  44 #define RENCODE_IB_PARAM_LAYER_CONTROL                          0x00000004
  45 #define RENCODE_IB_PARAM_LAYER_SELECT                           0x00000005
  46 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT              0x00000006
  47 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT                0x00000007
  48 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE               0x00000008
  49 #define RENCODE_IB_PARAM_QUALITY_PARAMS                         0x00000009
  50 #define RENCODE_IB_PARAM_SLICE_HEADER                           0x0000000a
  51 #define RENCODE_IB_PARAM_ENCODE_PARAMS                          0x0000000b
  52 #define RENCODE_IB_PARAM_INTRA_REFRESH                          0x0000000c
  53 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER                  0x0000000d
  54 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER                 0x0000000e
  55 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER                        0x00000010
  56 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU                     0x00000020
  57
  58 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL                     0x00100001
  59 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC                         0x00100002
  60 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER                 0x00100003
  61
  62 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL                     0x00200001
  63 #define RENCODE_H264_IB_PARAM_SPEC_MISC                         0x00200002
  64 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS                     0x00200003
  65 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER                 0x00200004
  66
  67 static void radeon_enc_session_info(struct radeon_encoder *enc)
  68 {
  69         RADEON_ENC_BEGIN(enc->cmd.session_info);
  70         RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
  71         RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
  72         RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
  73         RADEON_ENC_END();
  74 }
  75
  76 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
  77 {
  78         enc->enc_pic.task_info.task_id++;
  79
  80         if (need_feedback)
  81                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
  82         else
  83                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
  84
  85         RADEON_ENC_BEGIN(enc->cmd.task_info);
  86         enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
  87         RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
  88         RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
  89         RADEON_ENC_END();
  90 }
  91
  92 static void radeon_enc_session_init(struct radeon_encoder *enc)
  93 {
  94         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
  95         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
  96         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
  97         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
  98         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
  99         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 100         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 101
 102         RADEON_ENC_BEGIN(enc->cmd.session_init);
 103         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 104         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 105         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 106         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 107         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 108         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 109         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 110         RADEON_ENC_END();
 111 }
 112
 113 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
 114 {
 115         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
 116         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
 117         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 118         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 119         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 120         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 121         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 122
 123         RADEON_ENC_BEGIN(enc->cmd.session_init);
 124         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 125         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 126         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 127         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 128         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 129         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 130         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 131         RADEON_ENC_END();
 132 }
 133
 134 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 135 {
 136         enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 137         enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 138
 139         RADEON_ENC_BEGIN(enc->cmd.layer_control);
 140         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 141         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 142         RADEON_ENC_END();
 143 }
 144
 145 static void radeon_enc_layer_select(struct radeon_encoder *enc)
 146 {
 147         enc->enc_pic.layer_sel.temporal_layer_index = 0;
 148
 149         RADEON_ENC_BEGIN(enc->cmd.layer_select);
 150         RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 151         RADEON_ENC_END();
 152 }
 153
 154 static void radeon_enc_slice_control(struct radeon_encoder *enc)
 155 {
 156         enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 157         enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
 158
 159         RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
 160         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
 161         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
 162         RADEON_ENC_END();
 163 }
 164
 165 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
 166 {
 167         enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
 168         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 169         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 170
 171         RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
 172         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 173         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
 174         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 175         RADEON_ENC_END();
 176 }
 177
 178 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 179 {
 180         enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
 181         enc->enc_pic.spec_misc.cabac_enable = 0;
 182         enc->enc_pic.spec_misc.cabac_init_idc = 0;
 183         enc->enc_pic.spec_misc.half_pel_enabled = 1;
 184         enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
 185         enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
 186         enc->enc_pic.spec_misc.level_idc = enc->base.level;
 187
 188         RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
 189         RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
 190         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
 191         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
 192         RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
 193         RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
 194         RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
 195         RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
 196         RADEON_ENC_END();
 197 }
 198
 199 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
 200 {
 201         RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
 202         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 203         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 204         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 205         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 206         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 207         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 208         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 209         RADEON_ENC_END();
 210 }
 211
 212 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
 213 {
 214         RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
 215         RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 216         RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 217         RADEON_ENC_END();
 218 }
 219
 220 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
 221 {
 222         RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
 223         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 224         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 225         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 226         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 227         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 228         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 229         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 230         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 231         RADEON_ENC_END();
 232 }
 233
 234 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
 235 {
 236         enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
 237         enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
 238         enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
 239         enc->enc_pic.h264_deblock.cb_qp_offset = 0;
 240         enc->enc_pic.h264_deblock.cr_qp_offset = 0;
 241
 242         RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
 243         RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
 244         RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 245         RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
 246         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
 247         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
 248         RADEON_ENC_END();
 249 }
 250
 251 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
 252 {
 253         RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
 254         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 255         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 256         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 257         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 258         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 259         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 260         RADEON_ENC_END();
 261 }
 262
 263 static void radeon_enc_quality_params(struct radeon_encoder *enc)
 264 {
 265         enc->enc_pic.quality_params.vbaq_mode = 0;
 266         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 267         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 268
 269         RADEON_ENC_BEGIN(enc->cmd.quality_params);
 270         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 271         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 272         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 273         RADEON_ENC_END();
 274 }
 275
 276 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
 277 {
 278         RADEON_ENC_BEGIN(enc->cmd.nalu);
 279         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 280         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 281         radeon_enc_reset(enc);
 282         radeon_enc_set_emulation_prevention(enc, false);
 283         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 284         radeon_enc_code_fixed_bits(enc, 0x67, 8);
 285         radeon_enc_byte_align(enc);
 286         radeon_enc_set_emulation_prevention(enc, true);
 287         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
 288         radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
 289         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
 290         radeon_enc_code_ue(enc, 0x0);
 291
 292         if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
 293                         enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
 294                         enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
 295                         enc->enc_pic.spec_misc.profile_idc == 138) {
 296                 radeon_enc_code_ue(enc, 0x1);
 297                 radeon_enc_code_ue(enc, 0x0);
 298                 radeon_enc_code_ue(enc, 0x0);
 299                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 300         }
 301
 302         radeon_enc_code_ue(enc, 1);
 303         radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
 304
 305         if (enc->enc_pic.pic_order_cnt_type == 0)
 306                 radeon_enc_code_ue(enc, 1);
 307
 308         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 309         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
 310         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
 311         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
 312         bool progressive_only = true;
 313         radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
 314
 315         if (!progressive_only)
 316                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 317
 318         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 319
 320         if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
 321                         (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
 322                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 323                 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
 324                 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
 325                 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
 326                 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 327         } else
 328                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 329
 330         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 331         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 332         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 333         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 334         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 335         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 336         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 337         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 338         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 339         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 340         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 341         radeon_enc_code_ue(enc, 0x0);
 342         radeon_enc_code_ue(enc, 0x0);
 343         radeon_enc_code_ue(enc, 16);
 344         radeon_enc_code_ue(enc, 16);
 345         radeon_enc_code_ue(enc, 0x0);
 346         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 347
 348         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 349
 350         radeon_enc_byte_align(enc);
 351         radeon_enc_flush_headers(enc);
 352         *size_in_bytes = (enc->bits_output + 7) / 8;
 353         RADEON_ENC_END();
 354 }
 355
 356 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 357 {
 358         RADEON_ENC_BEGIN(enc->cmd.nalu);
 359         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 360         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 361         int i;
 362
 363         radeon_enc_reset(enc);
 364         radeon_enc_set_emulation_prevention(enc, false);
 365         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 366         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 367         radeon_enc_byte_align(enc);
 368         radeon_enc_set_emulation_prevention(enc, true);
 369         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 370         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 371         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 372         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 373         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 374         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 375         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 376         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 377         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 378         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 379
 380         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 381                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 382
 383         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 384                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 385                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 386         }
 387
 388         radeon_enc_code_ue(enc, 0x0);
 389         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 390         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 391         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 392         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 393         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 394         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 395         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 396         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 397         radeon_enc_code_ue(enc, 1);
 398         radeon_enc_code_ue(enc, 0x0);
 399         radeon_enc_code_ue(enc, 0x0);
 400         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 401         //Only support CTBSize 64
 402         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 403         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 404         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 405         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 406         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 407
 408         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 409         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 410         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 411         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 412
 413         radeon_enc_code_ue(enc, 1);
 414         radeon_enc_code_ue(enc, 1);
 415         radeon_enc_code_ue(enc, 0);
 416         radeon_enc_code_ue(enc, 0);
 417         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 418
 419         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 420
 421         radeon_enc_code_fixed_bits(enc, 0, 1);
 422         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 423
 424         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 425
 426         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 427
 428         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 429
 430         radeon_enc_byte_align(enc);
 431         radeon_enc_flush_headers(enc);
 432         *size_in_bytes = (enc->bits_output + 7) / 8;
 433         RADEON_ENC_END();
 434 }
 435
 436 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 437 {
 438         RADEON_ENC_BEGIN(enc->cmd.nalu);
 439         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 440         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 441         radeon_enc_reset(enc);
 442         radeon_enc_set_emulation_prevention(enc, false);
 443         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 444         radeon_enc_code_fixed_bits(enc, 0x68, 8);
 445         radeon_enc_byte_align(enc);
 446         radeon_enc_set_emulation_prevention(enc, true);
 447         radeon_enc_code_ue(enc, 0x0);
 448         radeon_enc_code_ue(enc, 0x0);
 449         radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
 450         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 451         radeon_enc_code_ue(enc, 0x0);
 452         radeon_enc_code_ue(enc, 0x0);
 453         radeon_enc_code_ue(enc, 0x0);
 454         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 455         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 456         radeon_enc_code_se(enc, 0x0);
 457         radeon_enc_code_se(enc, 0x0);
 458         radeon_enc_code_se(enc, 0x0);
 459         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 460         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 461         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 462
 463         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 464
 465         radeon_enc_byte_align(enc);
 466         radeon_enc_flush_headers(enc);
 467         *size_in_bytes = (enc->bits_output + 7) / 8;
 468         RADEON_ENC_END();
 469 }
 470
 471 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 472 {
 473         RADEON_ENC_BEGIN(enc->cmd.nalu);
 474         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 475         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 476         radeon_enc_reset(enc);
 477         radeon_enc_set_emulation_prevention(enc, false);
 478         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 479         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 480         radeon_enc_byte_align(enc);
 481         radeon_enc_set_emulation_prevention(enc, true);
 482         radeon_enc_code_ue(enc, 0x0);
 483         radeon_enc_code_ue(enc, 0x0);
 484         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 485         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 486         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 487         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 488         radeon_enc_code_ue(enc, 0x0);
 489         radeon_enc_code_ue(enc, 0x0);
 490         radeon_enc_code_se(enc, 0x0);
 491         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 492         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 493         if (enc->enc_pic.rc_session_init.rate_control_method ==
 494                 RENCODE_RATE_CONTROL_METHOD_NONE)
 495                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 496         else {
 497                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 498                 radeon_enc_code_ue(enc, 0x0);
 499         }
 500         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 501         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 502         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 503         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 504         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 505         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 506         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 507         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 508         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 509         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 510         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 511
 512         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 513                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 514                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 515         }
 516
 517         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 518         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 519         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 520         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 521
 522         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 523
 524         radeon_enc_byte_align(enc);
 525         radeon_enc_flush_headers(enc);
 526         *size_in_bytes = (enc->bits_output + 7) / 8;
 527         RADEON_ENC_END();
 528 }
 529
 530 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
 531 {
 532         RADEON_ENC_BEGIN(enc->cmd.nalu);
 533         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
 534         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 535         int i;
 536
 537         radeon_enc_reset(enc);
 538         radeon_enc_set_emulation_prevention(enc, false);
 539         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 540         radeon_enc_code_fixed_bits(enc, 0x4001, 16);
 541         radeon_enc_byte_align(enc);
 542         radeon_enc_set_emulation_prevention(enc, true);
 543
 544         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 545         radeon_enc_code_fixed_bits(enc, 0x3, 2);
 546         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 547         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 548         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 549         radeon_enc_code_fixed_bits(enc, 0xffff, 16);
 550         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 551         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 552         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 553         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 554         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 555         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 556         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 557
 558         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 559                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 560
 561         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 562                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 563                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 564         }
 565
 566         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 567         radeon_enc_code_ue(enc, 0x1);
 568         radeon_enc_code_ue(enc, 0x0);
 569         radeon_enc_code_ue(enc, 0x0);
 570
 571         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 572         radeon_enc_code_ue(enc, 0x0);
 573         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 574         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 575
 576         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 577
 578         radeon_enc_byte_align(enc);
 579         radeon_enc_flush_headers(enc);
 580         *size_in_bytes = (enc->bits_output + 7) / 8;
 581         RADEON_ENC_END();
 582 }
 583
 584 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
 585 {
 586         RADEON_ENC_BEGIN(enc->cmd.nalu);
 587         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
 588         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 589         radeon_enc_reset(enc);
 590         radeon_enc_set_emulation_prevention(enc, false);
 591         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 592         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 593         radeon_enc_code_fixed_bits(enc, 35, 6);
 594         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 595         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 596         radeon_enc_byte_align(enc);
 597         radeon_enc_set_emulation_prevention(enc, true);
 598         switch(enc->enc_pic.picture_type) {
 599                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 600                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 601                         radeon_enc_code_fixed_bits(enc, 0x00, 3);
 602                         break;
 603                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 604                         radeon_enc_code_fixed_bits(enc, 0x01, 3);
 605                         break;
 606                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 607                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 608                         break;
 609                 default:
 610                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 611         }
 612
 613     radeon_enc_code_fixed_bits(enc, 0x1, 1);
 614
 615         radeon_enc_byte_align(enc);
 616         radeon_enc_flush_headers(enc);
 617         *size_in_bytes = (enc->bits_output + 7) / 8;
 618         RADEON_ENC_END();
 619 }
 620
 621 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 622 {
 623         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 624         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 625         unsigned int inst_index = 0;
 626         unsigned int bit_index = 0;
 627         unsigned int bits_copied = 0;
 628         RADEON_ENC_BEGIN(enc->cmd.slice_header);
 629         radeon_enc_reset(enc);
 630         radeon_enc_set_emulation_prevention(enc, false);
 631
 632         if (enc->enc_pic.is_idr)
 633                 radeon_enc_code_fixed_bits(enc, 0x65, 8);
 634         else if (enc->enc_pic.not_referenced)
 635                 radeon_enc_code_fixed_bits(enc, 0x01, 8);
 636         else
 637                 radeon_enc_code_fixed_bits(enc, 0x41, 8);
 638
 639         radeon_enc_flush_headers(enc);
 640         bit_index ++;
 641         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 642         num_bits[inst_index] = enc->bits_output - bits_copied;
 643         bits_copied = enc->bits_output;
 644         inst_index++;
 645
 646         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
 647         inst_index++;
 648
 649         switch(enc->enc_pic.picture_type) {
 650                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 651                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 652                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 653                         break;
 654                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 655                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 656                         radeon_enc_code_fixed_bits(enc, 0x06, 5);
 657                         break;
 658                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 659                         radeon_enc_code_fixed_bits(enc, 0x07, 5);
 660                         break;
 661                 default:
 662                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 663         }
 664
 665         radeon_enc_code_ue(enc, 0x0);
 666         radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
 667
 668         if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
 669                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 670                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
 671         }
 672
 673         if (enc->enc_pic.is_idr)
 674                 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
 675
 676         enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
 677
 678         if (enc->enc_pic.pic_order_cnt_type == 0)
 679                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
 680
 681         if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
 682                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 683
 684                 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
 685                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 686                         radeon_enc_code_ue(enc, 0x0);
 687                         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
 688                         radeon_enc_code_ue(enc, 0x3);
 689                 } else
 690                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 691         }
 692
 693         if (enc->enc_pic.is_idr) {
 694                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 695                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 696         } else
 697                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 698
 699         if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
 700                 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
 701
 702         radeon_enc_flush_headers(enc);
 703         bit_index ++;
 704         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 705         num_bits[inst_index] = enc->bits_output - bits_copied;
 706         bits_copied = enc->bits_output;
 707         inst_index++;
 708
 709         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 710         inst_index++;
 711
 712         radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
 713
 714         if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
 715                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 716                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
 717         }
 718
 719         radeon_enc_flush_headers(enc);
 720         bit_index ++;
 721         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 722         num_bits[inst_index] = enc->bits_output - bits_copied;
 723         bits_copied = enc->bits_output;
 724         inst_index++;
 725
 726         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 727
 728         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 729                 RADEON_ENC_CS(0x00000000);
 730
 731         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 732                 RADEON_ENC_CS(instruction[j]);
 733                 RADEON_ENC_CS(num_bits[j]);
 734         }
 735
 736         RADEON_ENC_END();
 737 }
 738
 739 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 740 {
 741         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 742         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 743         unsigned int inst_index = 0;
 744         unsigned int bit_index = 0;
 745         unsigned int bits_copied = 0;
 746         RADEON_ENC_BEGIN(enc->cmd.slice_header);
 747         radeon_enc_reset(enc);
 748         radeon_enc_set_emulation_prevention(enc, false);
 749
 750         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 751         radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
 752         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 753         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 754
 755         radeon_enc_flush_headers(enc);
 756         bit_index ++;
 757         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 758         num_bits[inst_index] = enc->bits_output - bits_copied;
 759         bits_copied = enc->bits_output;
 760         inst_index++;
 761
 762         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
 763         inst_index++;
 764
 765         if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
 766                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 767
 768         radeon_enc_code_ue(enc, 0x0);
 769
 770         radeon_enc_flush_headers(enc);
 771         bit_index ++;
 772         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 773         num_bits[inst_index] = enc->bits_output - bits_copied;
 774         bits_copied = enc->bits_output;
 775         inst_index++;
 776
 777         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
 778         inst_index++;
 779
 780         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
 781         inst_index++;
 782
 783         switch(enc->enc_pic.picture_type) {
 784                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 785                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 786                         radeon_enc_code_ue(enc, 0x2);
 787                         break;
 788                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 789                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 790                         radeon_enc_code_ue(enc, 0x1);
 791                         break;
 792                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 793                         radeon_enc_code_ue(enc, 0x0);
 794                         break;
 795                 default:
 796                         radeon_enc_code_ue(enc, 0x1);
 797         }
 798
 799         if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
 800                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
 801                 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
 802                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 803                 else {
 804                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 805                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 806                         radeon_enc_code_ue(enc, 0x0);
 807                         radeon_enc_code_ue(enc, 0x0);
 808                 }
 809         }
 810
 811         if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
 812                 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
 813                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 814                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
 815                 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
 816         }
 817
 818         radeon_enc_flush_headers(enc);
 819         bit_index ++;
 820         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 821         num_bits[inst_index] = enc->bits_output - bits_copied;
 822         bits_copied = enc->bits_output;
 823         inst_index++;
 824
 825         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 826         inst_index++;
 827
 828         if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
 829                 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)){
 830                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 831
 832                 radeon_enc_flush_headers(enc);
 833                 bit_index ++;
 834                 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 835                 num_bits[inst_index] = enc->bits_output - bits_copied;
 836                 bits_copied = enc->bits_output;
 837                 inst_index++;
 838         }
 839
 840         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 841
 842         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 843                 RADEON_ENC_CS(0x00000000);
 844
 845         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 846                 RADEON_ENC_CS(instruction[j]);
 847                 RADEON_ENC_CS(num_bits[j]);
 848         }
 849
 850         RADEON_ENC_END();
 851 }
 852
 853 static void radeon_enc_ctx(struct radeon_encoder *enc)
 854 {
 855         enc->enc_pic.ctx_buf.swizzle_mode = 0;
 856         enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
 857         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
 858         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 859
 860         RADEON_ENC_BEGIN(enc->cmd.ctx);
 861         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 862         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 863         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 864         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 865         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 866         /* reconstructed_picture_1_luma_offset */
 867         RADEON_ENC_CS(0x00000000);
 868         /* reconstructed_picture_1_chroma_offset */
 869         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
 870         /* reconstructed_picture_2_luma_offset */
 871         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
 872         /* reconstructed_picture_2_chroma_offset */
 873         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
 874
 875         for (int i = 0; i < 136 ; i++)
 876                 RADEON_ENC_CS(0x00000000);
 877
 878         RADEON_ENC_END();
 879 }
 880
 881 static void radeon_enc_bitstream(struct radeon_encoder *enc)
 882 {
 883         enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
 884         enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
 885         enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
 886
 887         RADEON_ENC_BEGIN(enc->cmd.bitstream);
 888         RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
 889         RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
 890         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
 891         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
 892         RADEON_ENC_END();
 893 }
 894
 895 static void radeon_enc_feedback(struct radeon_encoder *enc)
 896 {
 897         enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
 898         enc->enc_pic.fb_buf.feedback_buffer_size = 16;
 899         enc->enc_pic.fb_buf.feedback_data_size = 40;
 900
 901         RADEON_ENC_BEGIN(enc->cmd.feedback);
 902         RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
 903         RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
 904         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
 905         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
 906         RADEON_ENC_END();
 907 }
 908
 909 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
 910 {
 911         enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
 912         enc->enc_pic.intra_ref.offset = 0;
 913         enc->enc_pic.intra_ref.region_size = 0;
 914
 915         RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
 916         RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
 917         RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
 918         RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
 919         RADEON_ENC_END();
 920 }
 921
 922 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
 923 {
 924         RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
 925         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
 926         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
 927         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
 928         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
 929         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
 930         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
 931         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
 932         RADEON_ENC_END();
 933 }
 934
 935 static void radeon_enc_encode_params(struct radeon_encoder *enc)
 936 {
 937         switch(enc->enc_pic.picture_type) {
 938                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 939                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 940                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 941                         break;
 942                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 943                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
 944                         break;
 945                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 946                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
 947                         break;
 948                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 949                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
 950                         break;
 951                 default:
 952                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 953         }
 954
 955         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
 956         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
 957         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
 958         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
 959
 960         if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
 961                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
 962         else
 963                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
 964
 965         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
 966
 967         RADEON_ENC_BEGIN(enc->cmd.enc_params);
 968         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
 969         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
 970         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
 971         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
 972         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
 973         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
 974         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
 975         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
 976         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
 977         RADEON_ENC_END();
 978 }
 979
 980 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
 981 {
 982         switch(enc->enc_pic.picture_type) {
 983                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 984                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 985                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 986                         break;
 987                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 988                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
 989                         break;
 990                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 991                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
 992                         break;
 993                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 994                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
 995                         break;
 996                 default:
 997                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 998         }
 999
1000         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1001         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1002         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1003         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1004
1005         if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1006                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1007         else
1008                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1009
1010         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1011
1012         RADEON_ENC_BEGIN(enc->cmd.enc_params);
1013         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1014         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1015         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1016         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1017         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1018         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1019         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1020         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1021         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1022         RADEON_ENC_END();
1023 }
1024
1025 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1026 {
1027         enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1028         enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1029         enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1030         enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1031
1032         RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1033         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1034         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1035         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1036         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1037         RADEON_ENC_END();
1038 }
1039
1040 static void radeon_enc_op_init(struct radeon_encoder *enc)
1041 {
1042         RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1043         RADEON_ENC_END();
1044 }
1045
1046 static void radeon_enc_op_close(struct radeon_encoder *enc)
1047 {
1048         RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1049         RADEON_ENC_END();
1050 }
1051
1052 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1053 {
1054         RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1055         RADEON_ENC_END();
1056 }
1057
1058 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1059 {
1060         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1061         RADEON_ENC_END();
1062 }
1063
1064 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1065 {
1066         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1067         RADEON_ENC_END();
1068 }
1069
1070 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1071 {
1072         RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1073         RADEON_ENC_END();
1074 }
1075
1076 static void begin(struct radeon_encoder *enc)
1077 {
1078         enc->session_info(enc);
1079         enc->total_task_size = 0;
1080         enc->task_info(enc, enc->need_feedback);
1081         enc->op_init(enc);
1082
1083         enc->session_init(enc);
1084         enc->slice_control(enc);
1085         enc->spec_misc(enc);
1086         enc->deblocking_filter(enc);
1087
1088         enc->layer_control(enc);
1089         enc->rc_session_init(enc);
1090         enc->quality_params(enc);
1091         enc->layer_select(enc);
1092         enc->rc_layer_init(enc);
1093         enc->layer_select(enc);
1094         enc->rc_per_pic(enc);
1095         enc->op_init_rc(enc);
1096         enc->op_init_rc_vbv(enc);
1097         *enc->p_task_size = (enc->total_task_size);
1098 }
1099
1100 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1101 {
1102         if (enc->enc_pic.is_idr) {
1103                 enc->nalu_sps(enc);
1104                 enc->nalu_pps(enc);
1105         }
1106         enc->slice_header(enc);
1107         enc->encode_params(enc);
1108         enc->encode_params_codec_spec(enc);
1109 }
1110
1111 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1112 {
1113         enc->nalu_aud(enc);
1114         if (enc->enc_pic.is_idr) {
1115                 enc->nalu_vps(enc);
1116                 enc->nalu_pps(enc);
1117                 enc->nalu_sps(enc);
1118         }
1119         enc->slice_header(enc);
1120         enc->encode_params(enc);
1121 }
1122
1123 static void encode(struct radeon_encoder *enc)
1124 {
1125         enc->session_info(enc);
1126         enc->total_task_size = 0;
1127         enc->task_info(enc, enc->need_feedback);
1128
1129         enc->encode_headers(enc);
1130         enc->ctx(enc);
1131         enc->bitstream(enc);
1132         enc->feedback(enc);
1133         enc->intra_refresh(enc);
1134
1135         enc->op_speed(enc);
1136         enc->op_enc(enc);
1137         *enc->p_task_size = (enc->total_task_size);
1138 }
1139
1140 static void destroy(struct radeon_encoder *enc)
1141 {
1142         enc->session_info(enc);
1143         enc->total_task_size = 0;
1144         enc->task_info(enc, enc->need_feedback);
1145         enc->op_close(enc);
1146         *enc->p_task_size = (enc->total_task_size);
1147 }
1148
1149 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1150 {
1151         enc->begin = begin;
1152         enc->encode = encode;
1153         enc->destroy = destroy;
1154         enc->session_info = radeon_enc_session_info;
1155         enc->task_info = radeon_enc_task_info;
1156         enc->layer_control = radeon_enc_layer_control;
1157         enc->layer_select = radeon_enc_layer_select;
1158         enc->rc_session_init = radeon_enc_rc_session_init;
1159         enc->rc_layer_init = radeon_enc_rc_layer_init;
1160         enc->quality_params = radeon_enc_quality_params;
1161         enc->ctx = radeon_enc_ctx;
1162         enc->bitstream = radeon_enc_bitstream;
1163         enc->feedback = radeon_enc_feedback;
1164         enc->intra_refresh = radeon_enc_intra_refresh;
1165         enc->rc_per_pic = radeon_enc_rc_per_pic;
1166         enc->encode_params = radeon_enc_encode_params;
1167         enc->op_init = radeon_enc_op_init;
1168         enc->op_close = radeon_enc_op_close;
1169         enc->op_enc = radeon_enc_op_enc;
1170         enc->op_init_rc = radeon_enc_op_init_rc;
1171         enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1172         enc->op_speed = radeon_enc_op_speed;
1173
1174         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1175                 enc->session_init = radeon_enc_session_init;
1176                 enc->slice_control = radeon_enc_slice_control;
1177                 enc->spec_misc = radeon_enc_spec_misc;
1178                 enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1179                 enc->nalu_sps = radeon_enc_nalu_sps;
1180                 enc->nalu_pps = radeon_enc_nalu_pps;
1181                 enc->slice_header = radeon_enc_slice_header;
1182                 enc->encode_params = radeon_enc_encode_params;
1183                 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1184                 enc->encode_headers = radeon_enc_headers_h264;
1185         } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1186                 enc->session_init = radeon_enc_session_init_hevc;
1187                 enc->slice_control = radeon_enc_slice_control_hevc;
1188                 enc->spec_misc = radeon_enc_spec_misc_hevc;
1189                 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1190                 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1191                 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1192                 enc->nalu_vps = radeon_enc_nalu_vps;
1193                 enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1194                 enc->slice_header = radeon_enc_slice_header_hevc;
1195                 enc->encode_params = radeon_enc_encode_params_hevc;
1196                 enc->encode_headers = radeon_enc_headers_hevc;
1197         }
1198
1199         enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1200         enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1201         enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1202         enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1203         enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1204         enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1205         enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1206         enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1207         enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1208         enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1209         enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1210         enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1211         enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1212         enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1213         enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1214         enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1215         enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1216         enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1217         enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1218         enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1219         enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1220         enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1221         enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1222
1223         enc->enc_pic.session_info.interface_version =
1224                 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1225                  (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1226 }