2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #define RADEON_FLUSH_ASYNC (1 << 0)
32 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
35 enum radeon_bo_layout
{
36 RADEON_LAYOUT_LINEAR
= 0,
38 RADEON_LAYOUT_SQUARETILED
,
43 enum radeon_bo_domain
{ /* bitfield */
44 RADEON_DOMAIN_GTT
= 2,
45 RADEON_DOMAIN_VRAM
= 4,
46 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
49 enum radeon_bo_flag
{ /* bitfield */
50 RADEON_FLAG_GTT_WC
= (1 << 0),
51 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
52 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 enum radeon_bo_usage
{ /* bitfield */
56 RADEON_USAGE_READ
= 2,
57 RADEON_USAGE_WRITE
= 4,
58 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
63 CHIP_R300
, /* R3xx-based cores. */
71 CHIP_R420
, /* R4xx-based cores. */
80 CHIP_RV515
, /* R5xx-based cores. */
154 enum radeon_value_id
{
155 RADEON_REQUESTED_VRAM_MEMORY
,
156 RADEON_REQUESTED_GTT_MEMORY
,
159 RADEON_BUFFER_WAIT_TIME_NS
,
161 RADEON_NUM_CS_FLUSHES
,
162 RADEON_NUM_BYTES_MOVED
,
163 RADEON_NUM_EVICTIONS
,
166 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
169 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
172 /* Each group of four has the same priority. */
173 enum radeon_bo_priority
{
174 RADEON_PRIO_FENCE
= 0,
176 RADEON_PRIO_SO_FILLED_SIZE
,
179 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
180 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
181 RADEON_PRIO_DRAW_INDIRECT
,
182 RADEON_PRIO_INDEX_BUFFER
,
186 RADEON_PRIO_SDMA_BUFFER
,
187 RADEON_PRIO_SDMA_TEXTURE
,
189 RADEON_PRIO_CP_DMA
= 12,
191 RADEON_PRIO_CONST_BUFFER
= 16,
192 RADEON_PRIO_DESCRIPTORS
,
193 RADEON_PRIO_BORDER_COLORS
,
195 RADEON_PRIO_SAMPLER_BUFFER
= 20,
196 RADEON_PRIO_VERTEX_BUFFER
,
198 RADEON_PRIO_SHADER_RW_BUFFER
= 24,
199 RADEON_PRIO_COMPUTE_GLOBAL
,
201 RADEON_PRIO_SAMPLER_TEXTURE
= 28,
202 RADEON_PRIO_SHADER_RW_IMAGE
,
204 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 32,
206 RADEON_PRIO_COLOR_BUFFER
= 36,
208 RADEON_PRIO_DEPTH_BUFFER
= 40,
210 RADEON_PRIO_COLOR_BUFFER_MSAA
= 44,
212 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 48,
214 RADEON_PRIO_CMASK
= 52,
217 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
219 RADEON_PRIO_SHADER_RINGS
= 56,
221 RADEON_PRIO_SCRATCH_BUFFER
= 60,
222 /* 63 is the maximum value */
225 struct winsys_handle
;
226 struct radeon_winsys_ctx
;
228 struct radeon_winsys_cs_chunk
{
229 unsigned cdw
; /* Number of used dwords. */
230 unsigned max_dw
; /* Maximum number of dwords. */
231 uint32_t *buf
; /* The base pointer of the chunk. */
234 struct radeon_winsys_cs
{
235 struct radeon_winsys_cs_chunk current
;
236 struct radeon_winsys_cs_chunk
*prev
;
237 unsigned num_prev
; /* Number of previous chunks. */
238 unsigned max_prev
; /* Space in array pointed to by prev. */
239 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
241 /* Memory usage of the buffer list. These are always 0 for CE and preamble
248 /* PCI info: domain:bus:dev:func */
256 enum radeon_family family
;
257 enum chip_class chip_class
;
258 uint32_t gart_page_size
;
261 uint64_t max_alloc_size
;
262 bool has_dedicated_vram
;
263 bool has_virtual_memory
;
264 bool gfx_ib_pad_with_type2
;
267 uint32_t uvd_fw_version
;
268 uint32_t vce_fw_version
;
269 uint32_t me_fw_version
;
270 uint32_t pfp_fw_version
;
271 uint32_t ce_fw_version
;
272 uint32_t vce_harvest_config
;
273 uint32_t clock_crystal_freq
;
276 uint32_t drm_major
; /* version */
278 uint32_t drm_patchlevel
;
282 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
283 uint32_t max_shader_clock
;
284 uint32_t num_good_compute_units
;
285 uint32_t max_se
; /* shader engines */
286 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
288 /* Render backends (color + depth blocks). */
289 uint32_t r300_num_gb_pipes
;
290 uint32_t r300_num_z_pipes
;
291 uint32_t r600_gb_backend_map
; /* R600 harvest config */
292 bool r600_gb_backend_map_valid
;
293 uint32_t r600_num_banks
;
294 uint32_t num_render_backends
;
295 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
296 uint32_t pipe_interleave_bytes
;
297 uint32_t enabled_rb_mask
; /* GCN harvest config */
300 uint32_t si_tile_mode_array
[32];
301 uint32_t cik_macrotile_mode_array
[16];
304 /* Tiling info for display code, DRI sharing, and other data. */
305 struct radeon_bo_metadata
{
306 /* Tiling flags describing the texture layout for display code
309 enum radeon_bo_layout microtile
;
310 enum radeon_bo_layout macrotile
;
311 unsigned pipe_config
;
320 /* Additional metadata associated with the buffer, in bytes.
321 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
322 * Supported by amdgpu only.
324 uint32_t size_metadata
;
325 uint32_t metadata
[64];
328 enum radeon_feature_id
{
329 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
330 RADEON_FID_R300_CMASK_ACCESS
,
333 #define RADEON_SURF_MAX_LEVEL 32
335 #define RADEON_SURF_TYPE_MASK 0xFF
336 #define RADEON_SURF_TYPE_SHIFT 0
337 #define RADEON_SURF_TYPE_1D 0
338 #define RADEON_SURF_TYPE_2D 1
339 #define RADEON_SURF_TYPE_3D 2
340 #define RADEON_SURF_TYPE_CUBEMAP 3
341 #define RADEON_SURF_TYPE_1D_ARRAY 4
342 #define RADEON_SURF_TYPE_2D_ARRAY 5
343 #define RADEON_SURF_MODE_MASK 0xFF
344 #define RADEON_SURF_MODE_SHIFT 8
345 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
346 #define RADEON_SURF_MODE_1D 2
347 #define RADEON_SURF_MODE_2D 3
348 #define RADEON_SURF_SCANOUT (1 << 16)
349 #define RADEON_SURF_ZBUFFER (1 << 17)
350 #define RADEON_SURF_SBUFFER (1 << 18)
351 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
352 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
353 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
354 #define RADEON_SURF_FMASK (1 << 21)
355 #define RADEON_SURF_DISABLE_DCC (1 << 22)
357 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
358 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
359 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
361 struct radeon_surf_level
{
370 uint32_t pitch_bytes
;
373 uint64_t dcc_fast_clear_size
;
378 /* These are inputs to the calculator. */
391 /* These are return values. Some of them can be set by the caller, but
392 * they will be treated as hints (e.g. bankw, bankh) and might be
393 * changed by the calculator.
396 uint64_t bo_alignment
;
397 /* This applies to EG and later. */
402 uint32_t stencil_tile_split
;
403 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
404 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
405 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
406 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
407 uint32_t pipe_config
;
409 uint32_t macro_tile_index
;
410 uint32_t micro_tile_mode
; /* displayable, thin, depth, rotated */
412 /* Whether the depth miptree or stencil miptree as used by the DB are
413 * adjusted from their TC compatible form to ensure depth/stencil
414 * compatibility. If either is true, the corresponding plane cannot be
418 bool stencil_adjusted
;
421 uint64_t dcc_alignment
;
424 struct radeon_bo_list_item
{
427 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
430 struct radeon_winsys
{
432 * The screen object this winsys was created for
434 struct pipe_screen
*screen
;
437 * Decrement the winsys reference count.
439 * \param ws The winsys this function is called for.
440 * \return True if the winsys and screen should be destroyed.
442 bool (*unref
)(struct radeon_winsys
*ws
);
445 * Destroy this winsys.
447 * \param ws The winsys this function is called from.
449 void (*destroy
)(struct radeon_winsys
*ws
);
452 * Query an info structure from winsys.
454 * \param ws The winsys this function is called from.
455 * \param info Return structure
457 void (*query_info
)(struct radeon_winsys
*ws
,
458 struct radeon_info
*info
);
460 /**************************************************************************
461 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
463 * Remember that gallium gets to choose the interface it needs, and the
464 * window systems must then implement that interface (rather than the
465 * other way around...).
466 *************************************************************************/
469 * Create a buffer object.
471 * \param ws The winsys this function is called from.
472 * \param size The size to allocate.
473 * \param alignment An alignment of the buffer in memory.
474 * \param use_reusable_pool Whether the cache buffer manager should be used.
475 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
476 * \return The created buffer object.
478 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
481 enum radeon_bo_domain domain
,
482 enum radeon_bo_flag flags
);
485 * Map the entire data store of a buffer object into the client's address
488 * \param buf A winsys buffer object to map.
489 * \param cs A command stream to flush if the buffer is referenced by it.
490 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
491 * \return The pointer at the beginning of the buffer.
493 void *(*buffer_map
)(struct pb_buffer
*buf
,
494 struct radeon_winsys_cs
*cs
,
495 enum pipe_transfer_usage usage
);
498 * Unmap a buffer object from the client's address space.
500 * \param buf A winsys buffer object to unmap.
502 void (*buffer_unmap
)(struct pb_buffer
*buf
);
505 * Wait for the buffer and return true if the buffer is not used
508 * The timeout of 0 will only return the status.
509 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
512 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
513 enum radeon_bo_usage usage
);
516 * Return buffer metadata.
517 * (tiling info for display code, DRI sharing, and other data)
519 * \param buf A winsys buffer object to get the flags from.
522 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
523 struct radeon_bo_metadata
*md
);
526 * Set buffer metadata.
527 * (tiling info for display code, DRI sharing, and other data)
529 * \param buf A winsys buffer object to set the flags for.
532 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
533 struct radeon_bo_metadata
*md
);
536 * Get a winsys buffer from a winsys handle. The internal structure
537 * of the handle is platform-specific and only a winsys should access it.
539 * \param ws The winsys this function is called from.
540 * \param whandle A winsys handle pointer as was received from a state
542 * \param stride The returned buffer stride in bytes.
544 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
545 struct winsys_handle
*whandle
,
546 unsigned *stride
, unsigned *offset
);
549 * Get a winsys buffer from a user pointer. The resulting buffer can't
550 * be exported. Both pointer and size must be page aligned.
552 * \param ws The winsys this function is called from.
553 * \param pointer User pointer to turn into a buffer object.
554 * \param Size Size in bytes for the new buffer.
556 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
557 void *pointer
, uint64_t size
);
560 * Whether the buffer was created from a user pointer.
562 * \param buf A winsys buffer object
563 * \return whether \p buf was created via buffer_from_ptr
565 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
568 * Get a winsys handle from a winsys buffer. The internal structure
569 * of the handle is platform-specific and only a winsys should access it.
571 * \param buf A winsys buffer object to get the handle from.
572 * \param whandle A winsys handle pointer.
573 * \param stride A stride of the buffer in bytes, for texturing.
574 * \return true on success.
576 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
577 unsigned stride
, unsigned offset
,
579 struct winsys_handle
*whandle
);
582 * Return the virtual address of a buffer.
584 * \param buf A winsys buffer object
585 * \return virtual address
587 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
590 * Query the initial placement of the buffer from the kernel driver.
592 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
594 /**************************************************************************
595 * Command submission.
597 * Each pipe context should create its own command stream and submit
598 * commands independently of other contexts.
599 *************************************************************************/
602 * Create a command submission context.
603 * Various command streams can be submitted to the same context.
605 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
610 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
613 * Query a GPU reset status.
615 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
618 * Create a command stream.
620 * \param ctx The submission context
621 * \param ring_type The ring type (GFX, DMA, UVD)
622 * \param flush Flush callback function associated with the command stream.
623 * \param user User pointer that will be passed to the flush callback.
625 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
626 enum ring_type ring_type
,
627 void (*flush
)(void *ctx
, unsigned flags
,
628 struct pipe_fence_handle
**fence
),
632 * Add a constant engine IB to a graphics CS. This makes the graphics CS
633 * from "cs_create" a group of two IBs that share a buffer list and are
636 * The returned constant CS is only a stream for writing packets to the new
637 * IB. Calling other winsys functions with it is not allowed, not even
640 * In order to add buffers and check memory usage, use the graphics CS.
641 * In order to flush it, use the graphics CS, which will flush both IBs.
642 * Destroying the graphics CS will destroy both of them.
644 * \param cs The graphics CS from "cs_create" that will hold the buffer
645 * list and will be used for flushing.
647 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
650 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
651 * in similar manner to cs_add_const_ib. This should always be called after
654 * The returned IB is a constant engine IB that only gets flushed if the
657 * \param cs The graphics CS from "cs_create" that will hold the buffer
658 * list and will be used for flushing.
660 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
662 * Destroy a command stream.
664 * \param cs A command stream to destroy.
666 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
669 * Add a buffer. Each buffer used by a CS must be added using this function.
671 * \param cs Command stream
673 * \param usage Whether the buffer is used for read and/or write.
674 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
675 * \param priority A higher number means a greater chance of being
676 * placed in the requested domain. 15 is the maximum.
677 * \return Buffer index.
679 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
680 struct pb_buffer
*buf
,
681 enum radeon_bo_usage usage
,
682 enum radeon_bo_domain domain
,
683 enum radeon_bo_priority priority
);
686 * Return the index of an already-added buffer.
688 * \param cs Command stream
690 * \return The buffer index, or -1 if the buffer has not been added.
692 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
693 struct pb_buffer
*buf
);
696 * Return true if there is enough memory in VRAM and GTT for the buffers
697 * added so far. If the validation fails, all buffers which have
698 * been added since the last call of cs_validate will be removed and
699 * the CS will be flushed (provided there are still any buffers).
701 * \param cs A command stream to validate.
703 bool (*cs_validate
)(struct radeon_winsys_cs
*cs
);
706 * Check whether the given number of dwords is available in the IB.
707 * Optionally chain a new chunk of the IB if necessary and supported.
709 * \param cs A command stream.
710 * \param dw Number of CS dwords requested by the caller.
712 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
715 * Return the buffer list.
717 * \param cs Command stream
718 * \param list Returned buffer list. Set to NULL to query the count only.
719 * \return The buffer count.
721 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
722 struct radeon_bo_list_item
*list
);
725 * Flush a command stream.
727 * \param cs A command stream to flush.
728 * \param flags, RADEON_FLUSH_ASYNC or 0.
729 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
730 * after the CS and is returned through this parameter.
731 * \return Negative POSIX error code or 0 for success.
732 * Asynchronous submissions never return an error.
734 int (*cs_flush
)(struct radeon_winsys_cs
*cs
,
736 struct pipe_fence_handle
**fence
);
739 * Create a fence before the CS is flushed.
740 * The user must flush manually to complete the initializaton of the fence.
741 * The fence must not be used before the flush.
743 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_winsys_cs
*cs
);
746 * Return true if a buffer is referenced by a command stream.
748 * \param cs A command stream.
749 * \param buf A winsys buffer.
751 bool (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
752 struct pb_buffer
*buf
,
753 enum radeon_bo_usage usage
);
756 * Request access to a feature for a command stream.
758 * \param cs A command stream.
759 * \param fid Feature ID, one of RADEON_FID_*
760 * \param enable Whether to enable or disable the feature.
762 bool (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
763 enum radeon_feature_id fid
,
766 * Make sure all asynchronous flush of the cs have completed
768 * \param cs A command stream.
770 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
773 * Wait for the fence and return true if the fence has been signalled.
774 * The timeout of 0 will only return the status.
775 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
778 bool (*fence_wait
)(struct radeon_winsys
*ws
,
779 struct pipe_fence_handle
*fence
,
783 * Reference counting for fences.
785 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
786 struct pipe_fence_handle
*src
);
791 * \param ws The winsys this function is called from.
792 * \param surf Surface structure ptr
794 int (*surface_init
)(struct radeon_winsys
*ws
,
795 struct radeon_surf
*surf
);
798 * Find best values for a surface
800 * \param ws The winsys this function is called from.
801 * \param surf Surface structure ptr
803 int (*surface_best
)(struct radeon_winsys
*ws
,
804 struct radeon_surf
*surf
);
806 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
807 enum radeon_value_id value
);
809 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
810 unsigned num_registers
, uint32_t *out
);
813 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
815 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
818 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
820 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
823 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
824 const uint32_t *values
, unsigned count
)
826 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
827 cs
->current
.cdw
+= count
;