2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #define RADEON_FLUSH_ASYNC (1 << 0)
32 #define RADEON_FLUSH_KEEP_TILING_FLAGS (1 << 1)
33 #define RADEON_FLUSH_END_OF_FRAME (1 << 2)
36 enum radeon_bo_layout
{
37 RADEON_LAYOUT_LINEAR
= 0,
39 RADEON_LAYOUT_SQUARETILED
,
44 enum radeon_bo_domain
{ /* bitfield */
45 RADEON_DOMAIN_GTT
= 2,
46 RADEON_DOMAIN_VRAM
= 4,
47 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
50 enum radeon_bo_flag
{ /* bitfield */
51 RADEON_FLAG_GTT_WC
= (1 << 0),
52 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
53 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
56 enum radeon_bo_usage
{ /* bitfield */
57 RADEON_USAGE_READ
= 2,
58 RADEON_USAGE_WRITE
= 4,
59 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
64 CHIP_R300
, /* R3xx-based cores. */
72 CHIP_R420
, /* R4xx-based cores. */
81 CHIP_RV515
, /* R5xx-based cores. */
155 enum radeon_value_id
{
156 RADEON_REQUESTED_VRAM_MEMORY
,
157 RADEON_REQUESTED_GTT_MEMORY
,
158 RADEON_BUFFER_WAIT_TIME_NS
,
160 RADEON_NUM_CS_FLUSHES
,
161 RADEON_NUM_BYTES_MOVED
,
164 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
167 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
170 /* Each group of four has the same priority. */
171 enum radeon_bo_priority
{
172 RADEON_PRIO_FENCE
= 0,
174 RADEON_PRIO_SO_FILLED_SIZE
,
177 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
178 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
179 RADEON_PRIO_DRAW_INDIRECT
,
180 RADEON_PRIO_INDEX_BUFFER
,
182 RADEON_PRIO_CP_DMA
= 8,
184 RADEON_PRIO_VCE
= 12,
186 RADEON_PRIO_SDMA_BUFFER
,
187 RADEON_PRIO_SDMA_TEXTURE
,
189 RADEON_PRIO_USER_SHADER
= 16,
190 RADEON_PRIO_INTERNAL_SHADER
, /* fetch shader, etc. */
194 RADEON_PRIO_CONST_BUFFER
= 24,
195 RADEON_PRIO_DESCRIPTORS
,
196 RADEON_PRIO_BORDER_COLORS
,
198 RADEON_PRIO_SAMPLER_BUFFER
= 28,
199 RADEON_PRIO_VERTEX_BUFFER
,
201 RADEON_PRIO_SHADER_RW_BUFFER
= 32,
202 RADEON_PRIO_RINGS_STREAMOUT
,
203 RADEON_PRIO_SCRATCH_BUFFER
,
204 RADEON_PRIO_COMPUTE_GLOBAL
,
206 RADEON_PRIO_SAMPLER_TEXTURE
= 36,
207 RADEON_PRIO_SHADER_RW_IMAGE
,
209 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 40,
211 RADEON_PRIO_COLOR_BUFFER
= 44,
213 RADEON_PRIO_DEPTH_BUFFER
= 48,
215 RADEON_PRIO_COLOR_BUFFER_MSAA
= 52,
217 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 56,
219 RADEON_PRIO_CMASK
= 60,
222 /* 63 is the maximum value */
225 struct winsys_handle
;
226 struct radeon_winsys_ctx
;
228 struct radeon_winsys_cs_chunk
{
229 unsigned cdw
; /* Number of used dwords. */
230 unsigned max_dw
; /* Maximum number of dwords. */
231 uint32_t *buf
; /* The base pointer of the chunk. */
234 struct radeon_winsys_cs
{
235 struct radeon_winsys_cs_chunk current
;
236 struct radeon_winsys_cs_chunk
*prev
;
237 unsigned num_prev
; /* Number of previous chunks. */
238 unsigned max_prev
; /* Space in array pointed to by prev. */
239 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
243 /* PCI info: domain:bus:dev:func */
251 enum radeon_family family
;
252 enum chip_class chip_class
;
253 uint32_t gart_page_size
;
256 bool has_dedicated_vram
;
257 boolean has_virtual_memory
;
258 bool gfx_ib_pad_with_type2
;
261 uint32_t vce_fw_version
;
262 uint32_t vce_harvest_config
;
263 uint32_t clock_crystal_freq
;
266 uint32_t drm_major
; /* version */
268 uint32_t drm_patchlevel
;
272 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
273 uint32_t max_shader_clock
;
274 uint32_t num_good_compute_units
;
275 uint32_t max_se
; /* shader engines */
276 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
278 /* Render backends (color + depth blocks). */
279 uint32_t r300_num_gb_pipes
;
280 uint32_t r300_num_z_pipes
;
281 uint32_t r600_gb_backend_map
; /* R600 harvest config */
282 boolean r600_gb_backend_map_valid
;
283 uint32_t r600_num_banks
;
284 uint32_t num_render_backends
;
285 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
286 uint32_t pipe_interleave_bytes
;
287 uint32_t enabled_rb_mask
; /* GCN harvest config */
290 uint32_t si_tile_mode_array
[32];
291 uint32_t cik_macrotile_mode_array
[16];
294 /* Tiling info for display code, DRI sharing, and other data. */
295 struct radeon_bo_metadata
{
296 /* Tiling flags describing the texture layout for display code
299 enum radeon_bo_layout microtile
;
300 enum radeon_bo_layout macrotile
;
301 unsigned pipe_config
;
310 /* Additional metadata associated with the buffer, in bytes.
311 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
312 * Supported by amdgpu only.
314 uint32_t size_metadata
;
315 uint32_t metadata
[64];
318 enum radeon_feature_id
{
319 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
320 RADEON_FID_R300_CMASK_ACCESS
,
323 #define RADEON_SURF_MAX_LEVEL 32
325 #define RADEON_SURF_TYPE_MASK 0xFF
326 #define RADEON_SURF_TYPE_SHIFT 0
327 #define RADEON_SURF_TYPE_1D 0
328 #define RADEON_SURF_TYPE_2D 1
329 #define RADEON_SURF_TYPE_3D 2
330 #define RADEON_SURF_TYPE_CUBEMAP 3
331 #define RADEON_SURF_TYPE_1D_ARRAY 4
332 #define RADEON_SURF_TYPE_2D_ARRAY 5
333 #define RADEON_SURF_MODE_MASK 0xFF
334 #define RADEON_SURF_MODE_SHIFT 8
335 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
336 #define RADEON_SURF_MODE_1D 2
337 #define RADEON_SURF_MODE_2D 3
338 #define RADEON_SURF_SCANOUT (1 << 16)
339 #define RADEON_SURF_ZBUFFER (1 << 17)
340 #define RADEON_SURF_SBUFFER (1 << 18)
341 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
342 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
343 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
344 #define RADEON_SURF_FMASK (1 << 21)
345 #define RADEON_SURF_DISABLE_DCC (1 << 22)
347 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
348 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
349 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
351 struct radeon_surf_level
{
360 uint32_t pitch_bytes
;
363 uint64_t dcc_fast_clear_size
;
368 /* These are inputs to the calculator. */
381 /* These are return values. Some of them can be set by the caller, but
382 * they will be treated as hints (e.g. bankw, bankh) and might be
383 * changed by the calculator.
386 uint64_t bo_alignment
;
387 /* This applies to EG and later. */
392 uint32_t stencil_tile_split
;
393 uint64_t stencil_offset
;
394 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
395 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
396 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
397 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
398 uint32_t pipe_config
;
400 uint32_t macro_tile_index
;
401 uint32_t micro_tile_mode
; /* displayable, thin, depth, rotated */
404 uint64_t dcc_alignment
;
407 struct radeon_bo_list_item
{
408 struct pb_buffer
*buf
;
410 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
413 struct radeon_winsys
{
415 * The screen object this winsys was created for
417 struct pipe_screen
*screen
;
420 * Decrement the winsys reference count.
422 * \param ws The winsys this function is called for.
423 * \return True if the winsys and screen should be destroyed.
425 bool (*unref
)(struct radeon_winsys
*ws
);
428 * Destroy this winsys.
430 * \param ws The winsys this function is called from.
432 void (*destroy
)(struct radeon_winsys
*ws
);
435 * Query an info structure from winsys.
437 * \param ws The winsys this function is called from.
438 * \param info Return structure
440 void (*query_info
)(struct radeon_winsys
*ws
,
441 struct radeon_info
*info
);
443 /**************************************************************************
444 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
446 * Remember that gallium gets to choose the interface it needs, and the
447 * window systems must then implement that interface (rather than the
448 * other way around...).
449 *************************************************************************/
452 * Create a buffer object.
454 * \param ws The winsys this function is called from.
455 * \param size The size to allocate.
456 * \param alignment An alignment of the buffer in memory.
457 * \param use_reusable_pool Whether the cache buffer manager should be used.
458 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
459 * \return The created buffer object.
461 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
464 enum radeon_bo_domain domain
,
465 enum radeon_bo_flag flags
);
468 * Map the entire data store of a buffer object into the client's address
471 * \param buf A winsys buffer object to map.
472 * \param cs A command stream to flush if the buffer is referenced by it.
473 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
474 * \return The pointer at the beginning of the buffer.
476 void *(*buffer_map
)(struct pb_buffer
*buf
,
477 struct radeon_winsys_cs
*cs
,
478 enum pipe_transfer_usage usage
);
481 * Unmap a buffer object from the client's address space.
483 * \param buf A winsys buffer object to unmap.
485 void (*buffer_unmap
)(struct pb_buffer
*buf
);
488 * Wait for the buffer and return true if the buffer is not used
491 * The timeout of 0 will only return the status.
492 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
495 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
496 enum radeon_bo_usage usage
);
499 * Return buffer metadata.
500 * (tiling info for display code, DRI sharing, and other data)
502 * \param buf A winsys buffer object to get the flags from.
505 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
506 struct radeon_bo_metadata
*md
);
509 * Set buffer metadata.
510 * (tiling info for display code, DRI sharing, and other data)
512 * \param buf A winsys buffer object to set the flags for.
515 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
516 struct radeon_bo_metadata
*md
);
519 * Get a winsys buffer from a winsys handle. The internal structure
520 * of the handle is platform-specific and only a winsys should access it.
522 * \param ws The winsys this function is called from.
523 * \param whandle A winsys handle pointer as was received from a state
525 * \param stride The returned buffer stride in bytes.
527 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
528 struct winsys_handle
*whandle
,
529 unsigned *stride
, unsigned *offset
);
532 * Get a winsys buffer from a user pointer. The resulting buffer can't
533 * be exported. Both pointer and size must be page aligned.
535 * \param ws The winsys this function is called from.
536 * \param pointer User pointer to turn into a buffer object.
537 * \param Size Size in bytes for the new buffer.
539 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
540 void *pointer
, uint64_t size
);
543 * Whether the buffer was created from a user pointer.
545 * \param buf A winsys buffer object
546 * \return whether \p buf was created via buffer_from_ptr
548 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
551 * Get a winsys handle from a winsys buffer. The internal structure
552 * of the handle is platform-specific and only a winsys should access it.
554 * \param buf A winsys buffer object to get the handle from.
555 * \param whandle A winsys handle pointer.
556 * \param stride A stride of the buffer in bytes, for texturing.
557 * \return TRUE on success.
559 boolean (*buffer_get_handle
)(struct pb_buffer
*buf
,
560 unsigned stride
, unsigned offset
,
562 struct winsys_handle
*whandle
);
565 * Return the virtual address of a buffer.
567 * \param buf A winsys buffer object
568 * \return virtual address
570 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
573 * Query the initial placement of the buffer from the kernel driver.
575 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
577 /**************************************************************************
578 * Command submission.
580 * Each pipe context should create its own command stream and submit
581 * commands independently of other contexts.
582 *************************************************************************/
585 * Create a command submission context.
586 * Various command streams can be submitted to the same context.
588 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
593 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
596 * Query a GPU reset status.
598 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
601 * Create a command stream.
603 * \param ctx The submission context
604 * \param ring_type The ring type (GFX, DMA, UVD)
605 * \param flush Flush callback function associated with the command stream.
606 * \param user User pointer that will be passed to the flush callback.
608 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
609 enum ring_type ring_type
,
610 void (*flush
)(void *ctx
, unsigned flags
,
611 struct pipe_fence_handle
**fence
),
615 * Add a constant engine IB to a graphics CS. This makes the graphics CS
616 * from "cs_create" a group of two IBs that share a buffer list and are
619 * The returned constant CS is only a stream for writing packets to the new
620 * IB. Calling other winsys functions with it is not allowed, not even
623 * In order to add buffers and check memory usage, use the graphics CS.
624 * In order to flush it, use the graphics CS, which will flush both IBs.
625 * Destroying the graphics CS will destroy both of them.
627 * \param cs The graphics CS from "cs_create" that will hold the buffer
628 * list and will be used for flushing.
630 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
633 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
634 * in similar manner to cs_add_const_ib. This should always be called after
637 * The returned IB is a constant engine IB that only gets flushed if the
640 * \param cs The graphics CS from "cs_create" that will hold the buffer
641 * list and will be used for flushing.
643 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
645 * Destroy a command stream.
647 * \param cs A command stream to destroy.
649 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
652 * Add a buffer. Each buffer used by a CS must be added using this function.
654 * \param cs Command stream
656 * \param usage Whether the buffer is used for read and/or write.
657 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
658 * \param priority A higher number means a greater chance of being
659 * placed in the requested domain. 15 is the maximum.
660 * \return Buffer index.
662 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
663 struct pb_buffer
*buf
,
664 enum radeon_bo_usage usage
,
665 enum radeon_bo_domain domain
,
666 enum radeon_bo_priority priority
);
669 * Return the index of an already-added buffer.
671 * \param cs Command stream
673 * \return The buffer index, or -1 if the buffer has not been added.
675 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
676 struct pb_buffer
*buf
);
679 * Return TRUE if there is enough memory in VRAM and GTT for the buffers
680 * added so far. If the validation fails, all buffers which have
681 * been added since the last call of cs_validate will be removed and
682 * the CS will be flushed (provided there are still any buffers).
684 * \param cs A command stream to validate.
686 boolean (*cs_validate
)(struct radeon_winsys_cs
*cs
);
689 * Check whether the given number of dwords is available in the IB.
690 * Optionally chain a new chunk of the IB if necessary and supported.
692 * \param cs A command stream.
693 * \param dw Number of CS dwords requested by the caller.
695 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
698 * Return TRUE if there is enough memory in VRAM and GTT for the buffers
701 * \param cs A command stream to validate.
702 * \param vram VRAM memory size pending to be use
703 * \param gtt GTT memory size pending to be use
705 boolean (*cs_memory_below_limit
)(struct radeon_winsys_cs
*cs
, uint64_t vram
, uint64_t gtt
);
707 uint64_t (*cs_query_memory_usage
)(struct radeon_winsys_cs
*cs
);
710 * Return the buffer list.
712 * \param cs Command stream
713 * \param list Returned buffer list. Set to NULL to query the count only.
714 * \return The buffer count.
716 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
717 struct radeon_bo_list_item
*list
);
720 * Flush a command stream.
722 * \param cs A command stream to flush.
723 * \param flags, RADEON_FLUSH_ASYNC or 0.
724 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
725 * after the CS and is returned through this parameter.
727 void (*cs_flush
)(struct radeon_winsys_cs
*cs
,
729 struct pipe_fence_handle
**fence
);
732 * Return TRUE if a buffer is referenced by a command stream.
734 * \param cs A command stream.
735 * \param buf A winsys buffer.
737 boolean (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
738 struct pb_buffer
*buf
,
739 enum radeon_bo_usage usage
);
742 * Request access to a feature for a command stream.
744 * \param cs A command stream.
745 * \param fid Feature ID, one of RADEON_FID_*
746 * \param enable Whether to enable or disable the feature.
748 boolean (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
749 enum radeon_feature_id fid
,
752 * Make sure all asynchronous flush of the cs have completed
754 * \param cs A command stream.
756 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
759 * Wait for the fence and return true if the fence has been signalled.
760 * The timeout of 0 will only return the status.
761 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
764 bool (*fence_wait
)(struct radeon_winsys
*ws
,
765 struct pipe_fence_handle
*fence
,
769 * Reference counting for fences.
771 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
772 struct pipe_fence_handle
*src
);
777 * \param ws The winsys this function is called from.
778 * \param surf Surface structure ptr
780 int (*surface_init
)(struct radeon_winsys
*ws
,
781 struct radeon_surf
*surf
);
784 * Find best values for a surface
786 * \param ws The winsys this function is called from.
787 * \param surf Surface structure ptr
789 int (*surface_best
)(struct radeon_winsys
*ws
,
790 struct radeon_surf
*surf
);
792 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
793 enum radeon_value_id value
);
795 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
796 unsigned num_registers
, uint32_t *out
);
799 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
801 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
804 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
806 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
809 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
810 const uint32_t *values
, unsigned count
)
812 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
813 cs
->current
.cdw
+= count
;