src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "r600.h"
  47 #include "sid.h"
  48 #include "r600_resource.h"
  49 #include "radeonsi_pipe.h"
  50 #include "r600_hw_context_priv.h"
  51 #include "si_state.h"
  52
  53 /*
  54  * pipe_context
  55  */
  56 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  57 {
  58         struct r600_screen *rscreen = rctx->screen;
  59         struct r600_fence *fence = NULL;
  60
  61         pipe_mutex_lock(rscreen->fences.mutex);
  62
  63         if (!rscreen->fences.bo) {
  64                 /* Create the shared buffer object */
  65                 rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
  66                                                                PIPE_USAGE_STAGING,
  67                                                                4096);
  68                 if (!rscreen->fences.bo) {
  69                         R600_ERR("r600: failed to create bo for fence objects\n");
  70                         goto out;
  71                 }
  72                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  73                                                            rctx->cs,
  74                                                            PIPE_TRANSFER_READ_WRITE);
  75         }
  76
  77         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  78                 struct r600_fence *entry;
  79
  80                 /* Try to find a freed fence that has been signalled */
  81                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  82                         if (rscreen->fences.data[entry->index] != 0) {
  83                                 LIST_DELINIT(&entry->head);
  84                                 fence = entry;
  85                                 break;
  86                         }
  87                 }
  88         }
  89
  90         if (!fence) {
  91                 /* Allocate a new fence */
  92                 struct r600_fence_block *block;
  93                 unsigned index;
  94
  95                 if ((rscreen->fences.next_index + 1) >= 1024) {
  96                         R600_ERR("r600: too many concurrent fences\n");
  97                         goto out;
  98                 }
  99
 100                 index = rscreen->fences.next_index++;
 101
 102                 if (!(index % FENCE_BLOCK_SIZE)) {
 103                         /* Allocate a new block */
 104                         block = CALLOC_STRUCT(r600_fence_block);
 105                         if (block == NULL)
 106                                 goto out;
 107
 108                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 109                 } else {
 110                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 111                 }
 112
 113                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 114                 fence->index = index;
 115         }
 116
 117         pipe_reference_init(&fence->reference, 1);
 118
 119         rscreen->fences.data[fence->index] = 0;
 120         si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 121
 122         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 123         fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
 124
 125         /* Add the fence as a dummy relocation. */
 126         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 127
 128 out:
 129         pipe_mutex_unlock(rscreen->fences.mutex);
 130         return fence;
 131 }
 132
 133
 134 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 135                     unsigned flags)
 136 {
 137         struct r600_context *rctx = (struct r600_context *)ctx;
 138         struct r600_fence **rfence = (struct r600_fence**)fence;
 139         struct pipe_query *render_cond = NULL;
 140         unsigned render_cond_mode = 0;
 141
 142         if (rfence)
 143                 *rfence = r600_create_fence(rctx);
 144
 145         /* Disable render condition. */
 146         if (rctx->current_render_cond) {
 147                 render_cond = rctx->current_render_cond;
 148                 render_cond_mode = rctx->current_render_cond_mode;
 149                 ctx->render_condition(ctx, NULL, 0);
 150         }
 151
 152         si_context_flush(rctx, flags);
 153
 154         /* Re-enable render condition. */
 155         if (render_cond) {
 156                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 157         }
 158 }
 159
 160 static void r600_flush_from_st(struct pipe_context *ctx,
 161                                struct pipe_fence_handle **fence,
 162                                enum pipe_flush_flags flags)
 163 {
 164         radeonsi_flush(ctx, fence,
 165                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 166 }
 167
 168 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 169 {
 170         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 171 }
 172
 173 static void r600_destroy_context(struct pipe_context *context)
 174 {
 175         struct r600_context *rctx = (struct r600_context *)context;
 176
 177         si_resource_reference(&rctx->border_color_table, NULL);
 178
 179         if (rctx->dummy_pixel_shader) {
 180                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 181         }
 182         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
 183         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
 184         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
 185         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
 186         util_unreference_framebuffer_state(&rctx->framebuffer);
 187
 188         util_blitter_destroy(rctx->blitter);
 189
 190         if (rctx->uploader) {
 191                 u_upload_destroy(rctx->uploader);
 192         }
 193         util_slab_destroy(&rctx->pool_transfers);
 194         FREE(rctx);
 195 }
 196
 197 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 198 {
 199         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 200         struct r600_screen* rscreen = (struct r600_screen *)screen;
 201
 202         if (rctx == NULL)
 203                 return NULL;
 204
 205         rctx->context.screen = screen;
 206         rctx->context.priv = priv;
 207         rctx->context.destroy = r600_destroy_context;
 208         rctx->context.flush = r600_flush_from_st;
 209
 210         /* Easy accessing of screen/winsys. */
 211         rctx->screen = rscreen;
 212         rctx->ws = rscreen->ws;
 213         rctx->family = rscreen->family;
 214         rctx->chip_class = rscreen->chip_class;
 215
 216         si_init_blit_functions(rctx);
 217         r600_init_query_functions(rctx);
 218         r600_init_context_resource_functions(rctx);
 219         si_init_surface_functions(rctx);
 220
 221         rctx->context.create_video_decoder = vl_create_decoder;
 222         rctx->context.create_video_buffer = vl_video_buffer_create;
 223
 224         switch (rctx->chip_class) {
 225         case TAHITI:
 226                 si_init_state_functions(rctx);
 227                 LIST_INITHEAD(&rctx->active_query_list);
 228                 rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX);
 229                 rctx->max_db = 8;
 230                 si_init_config(rctx);
 231                 break;
 232         default:
 233                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 234                 r600_destroy_context(&rctx->context);
 235                 return NULL;
 236         }
 237
 238         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 239
 240         util_slab_create(&rctx->pool_transfers,
 241                          sizeof(struct pipe_transfer), 64,
 242                          UTIL_SLAB_SINGLETHREADED);
 243
 244         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 245                                          PIPE_BIND_INDEX_BUFFER |
 246                                          PIPE_BIND_CONSTANT_BUFFER);
 247         if (!rctx->uploader) {
 248                 r600_destroy_context(&rctx->context);
 249                 return NULL;
 250         }
 251
 252         rctx->blitter = util_blitter_create(&rctx->context);
 253         if (rctx->blitter == NULL) {
 254                 r600_destroy_context(&rctx->context);
 255                 return NULL;
 256         }
 257
 258         si_get_backend_mask(rctx); /* this emits commands and must be last */
 259
 260         rctx->dummy_pixel_shader =
 261                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 262                                                      TGSI_SEMANTIC_GENERIC,
 263                                                      TGSI_INTERPOLATE_CONSTANT);
 264         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 265
 266         return &rctx->context;
 267 }
 268
 269 /*
 270  * pipe_screen
 271  */
 272 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 273 {
 274         return "X.Org";
 275 }
 276
 277 static const char *r600_get_family_name(enum radeon_family family)
 278 {
 279         switch(family) {
 280         case CHIP_TAHITI: return "AMD TAHITI";
 281         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 282         case CHIP_VERDE: return "AMD CAPE VERDE";
 283         case CHIP_OLAND: return "AMD OLAND";
 284         default: return "AMD unknown";
 285         }
 286 }
 287
 288 static const char* r600_get_name(struct pipe_screen* pscreen)
 289 {
 290         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 291
 292         return r600_get_family_name(rscreen->family);
 293 }
 294
 295 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 296 {
 297         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 298
 299         switch (param) {
 300         /* Supported features (boolean caps). */
 301         case PIPE_CAP_TWO_SIDED_STENCIL:
 302         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 303         case PIPE_CAP_ANISOTROPIC_FILTER:
 304         case PIPE_CAP_POINT_SPRITE:
 305         case PIPE_CAP_OCCLUSION_QUERY:
 306         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 307         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 308         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 309         case PIPE_CAP_TEXTURE_SWIZZLE:
 310         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 311         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 312         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 313         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 314         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 315         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 316         case PIPE_CAP_SM3:
 317         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 318         case PIPE_CAP_PRIMITIVE_RESTART:
 319         case PIPE_CAP_CONDITIONAL_RENDER:
 320         case PIPE_CAP_TEXTURE_BARRIER:
 321         case PIPE_CAP_INDEP_BLEND_ENABLE:
 322         case PIPE_CAP_INDEP_BLEND_FUNC:
 323         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 324         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 325         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 326         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 327         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 328         case PIPE_CAP_USER_INDEX_BUFFERS:
 329         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 330         case PIPE_CAP_START_INSTANCE:
 331         case PIPE_CAP_NPOT_TEXTURES:
 332         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 333         case PIPE_CAP_TGSI_INSTANCEID:
 334                 return 1;
 335         case PIPE_CAP_TGSI_TEXCOORD:
 336                 return 0;
 337
 338         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 339                 return 64;
 340
 341         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 342                 return 256;
 343
 344         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 345                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 346
 347         /* Unsupported features. */
 348         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 349         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 350         case PIPE_CAP_SCALED_RESOLVE:
 351         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 352         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 353         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 354         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 355         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 356         case PIPE_CAP_USER_VERTEX_BUFFERS:
 357         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 358         case PIPE_CAP_COMPUTE:
 359         case PIPE_CAP_QUERY_TIMESTAMP:
 360         case PIPE_CAP_CUBE_MAP_ARRAY:
 361         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 362         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 363                 return 0;
 364
 365         /* Stream output. */
 366 #if 0
 367         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 368                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 369         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 370                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 373                 return 16*4;
 374 #endif
 375         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 376         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 377         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 378         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 379                 return 0;
 380
 381         /* Texturing. */
 382         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 383         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 384         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 385                         return 15;
 386         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 387                 return 16384;
 388         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 389                 return 32;
 390
 391         /* Render targets. */
 392         case PIPE_CAP_MAX_RENDER_TARGETS:
 393                 /* FIXME some r6xx are buggy and can only do 4 */
 394                 return 8;
 395
 396         /* Timer queries, present when the clock frequency is non zero. */
 397         case PIPE_CAP_QUERY_TIME_ELAPSED:
 398                 return rscreen->info.r600_clock_crystal_freq != 0;
 399
 400         case PIPE_CAP_MIN_TEXEL_OFFSET:
 401                 return -8;
 402
 403         case PIPE_CAP_MAX_TEXEL_OFFSET:
 404                 return 7;
 405         }
 406         return 0;
 407 }
 408
 409 static float r600_get_paramf(struct pipe_screen* pscreen,
 410                              enum pipe_capf param)
 411 {
 412         switch (param) {
 413         case PIPE_CAPF_MAX_LINE_WIDTH:
 414         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 415         case PIPE_CAPF_MAX_POINT_WIDTH:
 416         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 417                 return 16384.0f;
 418         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 419                 return 16.0f;
 420         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 421                 return 16.0f;
 422         case PIPE_CAPF_GUARD_BAND_LEFT:
 423         case PIPE_CAPF_GUARD_BAND_TOP:
 424         case PIPE_CAPF_GUARD_BAND_RIGHT:
 425         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 426                 return 0.0f;
 427         }
 428         return 0.0f;
 429 }
 430
 431 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 432 {
 433         switch(shader)
 434         {
 435         case PIPE_SHADER_FRAGMENT:
 436         case PIPE_SHADER_VERTEX:
 437                 break;
 438         case PIPE_SHADER_GEOMETRY:
 439                 /* TODO: support and enable geometry programs */
 440                 return 0;
 441         default:
 442                 /* TODO: support tessellation */
 443                 return 0;
 444         }
 445
 446         switch (param) {
 447         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 449         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 450         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 451                 return 16384;
 452         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 453                 return 32;
 454         case PIPE_SHADER_CAP_MAX_INPUTS:
 455                 return 32;
 456         case PIPE_SHADER_CAP_MAX_TEMPS:
 457                 return 256; /* Max native temporaries. */
 458         case PIPE_SHADER_CAP_MAX_ADDRS:
 459                 /* FIXME Isn't this equal to TEMPS? */
 460                 return 1; /* Max native address registers */
 461         case PIPE_SHADER_CAP_MAX_CONSTS:
 462                 return 4096; /* actually only memory limits this */
 463         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 464                 return 1;
 465         case PIPE_SHADER_CAP_MAX_PREDS:
 466                 return 0; /* FIXME */
 467         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 468                 return 1;
 469         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 470                 return 0;
 471         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 472         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 473         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 474         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 475                 return 1;
 476         case PIPE_SHADER_CAP_INTEGERS:
 477                 return 1;
 478         case PIPE_SHADER_CAP_SUBROUTINES:
 479                 return 0;
 480         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 481                 return 16;
 482         case PIPE_SHADER_CAP_PREFERRED_IR:
 483                 return PIPE_SHADER_IR_TGSI;
 484         }
 485         return 0;
 486 }
 487
 488 static int r600_get_video_param(struct pipe_screen *screen,
 489                                 enum pipe_video_profile profile,
 490                                 enum pipe_video_cap param)
 491 {
 492         switch (param) {
 493         case PIPE_VIDEO_CAP_SUPPORTED:
 494                 return vl_profile_supported(screen, profile);
 495         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 496                 return 1;
 497         case PIPE_VIDEO_CAP_MAX_WIDTH:
 498         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 499                 return vl_video_buffer_max_size(screen);
 500         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 501                 return PIPE_FORMAT_NV12;
 502         default:
 503                 return 0;
 504         }
 505 }
 506
 507 static void r600_destroy_screen(struct pipe_screen* pscreen)
 508 {
 509         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 510
 511         if (rscreen == NULL)
 512                 return;
 513
 514         if (rscreen->fences.bo) {
 515                 struct r600_fence_block *entry, *tmp;
 516
 517                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 518                         LIST_DEL(&entry->head);
 519                         FREE(entry);
 520                 }
 521
 522                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 523                 si_resource_reference(&rscreen->fences.bo, NULL);
 524         }
 525
 526 #if R600_TRACE_CS
 527         if (rscreen->trace_bo) {
 528                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 529                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 530         }
 531 #endif
 532
 533         pipe_mutex_destroy(rscreen->fences.mutex);
 534
 535         rscreen->ws->destroy(rscreen->ws);
 536         FREE(rscreen);
 537 }
 538
 539 static void r600_fence_reference(struct pipe_screen *pscreen,
 540                                  struct pipe_fence_handle **ptr,
 541                                  struct pipe_fence_handle *fence)
 542 {
 543         struct r600_fence **oldf = (struct r600_fence**)ptr;
 544         struct r600_fence *newf = (struct r600_fence*)fence;
 545
 546         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 547                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 548                 pipe_mutex_lock(rscreen->fences.mutex);
 549                 si_resource_reference(&(*oldf)->sleep_bo, NULL);
 550                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 551                 pipe_mutex_unlock(rscreen->fences.mutex);
 552         }
 553
 554         *ptr = fence;
 555 }
 556
 557 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 558                                     struct pipe_fence_handle *fence)
 559 {
 560         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 561         struct r600_fence *rfence = (struct r600_fence*)fence;
 562
 563         return rscreen->fences.data[rfence->index] != 0;
 564 }
 565
 566 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 567                                  struct pipe_fence_handle *fence,
 568                                  uint64_t timeout)
 569 {
 570         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 571         struct r600_fence *rfence = (struct r600_fence*)fence;
 572         int64_t start_time = 0;
 573         unsigned spins = 0;
 574
 575         if (timeout != PIPE_TIMEOUT_INFINITE) {
 576                 start_time = os_time_get();
 577
 578                 /* Convert to microseconds. */
 579                 timeout /= 1000;
 580         }
 581
 582         while (rscreen->fences.data[rfence->index] == 0) {
 583                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 584                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 585                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 586                         break;
 587                 }
 588
 589                 /* The dummy BO will be busy until the CS including the fence has completed, or
 590                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 591                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 592                         break;
 593
 594                 if (++spins % 256)
 595                         continue;
 596 #ifdef PIPE_OS_UNIX
 597                 sched_yield();
 598 #else
 599                 os_time_sleep(10);
 600 #endif
 601                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 602                     os_time_get() - start_time >= timeout) {
 603                         break;
 604                 }
 605         }
 606
 607         return rscreen->fences.data[rfence->index] != 0;
 608 }
 609
 610 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 611 {
 612         switch (tiling_config & 0xf) {
 613         case 0:
 614                 rscreen->tiling_info.num_channels = 1;
 615                 break;
 616         case 1:
 617                 rscreen->tiling_info.num_channels = 2;
 618                 break;
 619         case 2:
 620                 rscreen->tiling_info.num_channels = 4;
 621                 break;
 622         case 3:
 623                 rscreen->tiling_info.num_channels = 8;
 624                 break;
 625         default:
 626                 return -EINVAL;
 627         }
 628
 629         switch ((tiling_config & 0xf0) >> 4) {
 630         case 0:
 631                 rscreen->tiling_info.num_banks = 4;
 632                 break;
 633         case 1:
 634                 rscreen->tiling_info.num_banks = 8;
 635                 break;
 636         case 2:
 637                 rscreen->tiling_info.num_banks = 16;
 638                 break;
 639         default:
 640                 return -EINVAL;
 641         }
 642
 643         switch ((tiling_config & 0xf00) >> 8) {
 644         case 0:
 645                 rscreen->tiling_info.group_bytes = 256;
 646                 break;
 647         case 1:
 648                 rscreen->tiling_info.group_bytes = 512;
 649                 break;
 650         default:
 651                 return -EINVAL;
 652         }
 653         return 0;
 654 }
 655
 656 static int r600_init_tiling(struct r600_screen *rscreen)
 657 {
 658         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 659
 660         /* set default group bytes, overridden by tiling info ioctl */
 661         rscreen->tiling_info.group_bytes = 512;
 662
 663         if (!tiling_config)
 664                 return 0;
 665
 666         return evergreen_interpret_tiling(rscreen, tiling_config);
 667 }
 668
 669 static unsigned radeon_family_from_device(unsigned device)
 670 {
 671         switch (device) {
 672 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 673 #include "pci_ids/radeonsi_pci_ids.h"
 674 #undef CHIPSET
 675         default:
 676                 return CHIP_UNKNOWN;
 677         }
 678 }
 679
 680 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 681 {
 682         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 683         if (rscreen == NULL) {
 684                 return NULL;
 685         }
 686
 687         rscreen->ws = ws;
 688         ws->query_info(ws, &rscreen->info);
 689
 690         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 691         if (rscreen->family == CHIP_UNKNOWN) {
 692                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 693                 FREE(rscreen);
 694                 return NULL;
 695         }
 696
 697         /* setup class */
 698         if (rscreen->family >= CHIP_TAHITI) {
 699                 rscreen->chip_class = TAHITI;
 700         } else {
 701                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 702                 FREE(rscreen);
 703                 return NULL;
 704         }
 705
 706         if (r600_init_tiling(rscreen)) {
 707                 FREE(rscreen);
 708                 return NULL;
 709         }
 710
 711         rscreen->screen.destroy = r600_destroy_screen;
 712         rscreen->screen.get_name = r600_get_name;
 713         rscreen->screen.get_vendor = r600_get_vendor;
 714         rscreen->screen.get_param = r600_get_param;
 715         rscreen->screen.get_shader_param = r600_get_shader_param;
 716         rscreen->screen.get_paramf = r600_get_paramf;
 717         rscreen->screen.get_video_param = r600_get_video_param;
 718         rscreen->screen.is_format_supported = si_is_format_supported;
 719         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 720         rscreen->screen.context_create = r600_create_context;
 721         rscreen->screen.fence_reference = r600_fence_reference;
 722         rscreen->screen.fence_signalled = r600_fence_signalled;
 723         rscreen->screen.fence_finish = r600_fence_finish;
 724         r600_init_screen_resource_functions(&rscreen->screen);
 725
 726         util_format_s3tc_init();
 727
 728         rscreen->fences.bo = NULL;
 729         rscreen->fences.data = NULL;
 730         rscreen->fences.next_index = 0;
 731         LIST_INITHEAD(&rscreen->fences.pool);
 732         LIST_INITHEAD(&rscreen->fences.blocks);
 733         pipe_mutex_init(rscreen->fences.mutex);
 734
 735 #if R600_TRACE_CS
 736         rscreen->cs_count = 0;
 737         if (rscreen->info.drm_minor >= 28) {
 738                 rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
 739                                                                                 PIPE_BIND_CUSTOM,
 740                                                                                 PIPE_USAGE_STAGING,
 741                                                                                 4096);
 742                 if (rscreen->trace_bo) {
 743                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 744                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 745                 }
 746         }
 747 #endif
 748
 749         return &rscreen->screen;
 750 }