src/gallium/drivers/radeonsi/radeonsi_pm4.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef RADEONSI_PM4_H
  28 #define RADEONSI_PM4_H
  29
  30 #include "../../winsys/radeon/drm/radeon_winsys.h"
  31
  32 #define SI_PM4_MAX_DW           256
  33 #define SI_PM4_MAX_BO           32
  34 #define SI_PM4_MAX_RELOCS       4
  35
  36 // forward defines
  37 struct r600_context;
  38 enum chip_class;
  39
  40 struct si_pm4_state
  41 {
  42         /* family specific handling */
  43         enum chip_class chip_class;
  44         /* PKT3_SET_*_REG handling */
  45         unsigned        last_opcode;
  46         unsigned        last_reg;
  47         unsigned        last_pm4;
  48
  49         /* flush flags for SURFACE_SYNC */
  50         uint32_t        cp_coher_cntl;
  51
  52         /* commands for the DE */
  53         unsigned        ndw;
  54         uint32_t        pm4[SI_PM4_MAX_DW];
  55
  56         /* BO's referenced by this state */
  57         unsigned                nbo;
  58         struct r600_resource    *bo[SI_PM4_MAX_BO];
  59         enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
  60
  61         /* relocs for shader data */
  62         unsigned        nrelocs;
  63         unsigned        relocs[SI_PM4_MAX_RELOCS];
  64
  65         bool compute_pkt;
  66 };
  67
  68 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
  69 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
  70 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
  71
  72 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
  73 void si_pm4_add_bo(struct si_pm4_state *state,
  74                    struct r600_resource *bo,
  75                    enum radeon_bo_usage usage);
  76
  77 void si_pm4_sh_data_begin(struct si_pm4_state *state);
  78 void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
  79 void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
  80
  81 void si_pm4_inval_shader_cache(struct si_pm4_state *state);
  82 void si_pm4_inval_texture_cache(struct si_pm4_state *state);
  83
  84 void si_pm4_free_state(struct r600_context *rctx,
  85                        struct si_pm4_state *state,
  86                        unsigned idx);
  87 struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
  88
  89 uint32_t si_pm4_sync_flags(struct r600_context *rctx);
  90 unsigned si_pm4_dirty_dw(struct r600_context *rctx);
  91 void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state);
  92 void si_pm4_emit_dirty(struct r600_context *rctx);
  93 void si_pm4_reset_emitted(struct r600_context *rctx);
  94
  95 #endif