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radeonsi: fix an assertion failure in si_decompress_sampler_color_textures
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
56 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
57 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
58 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
59 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
60 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
61 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
62 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
63 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
64
65 if (op & SI_SAVE_FRAGMENT_STATE) {
66 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
67 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
68 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
69 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
70 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
71 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
72 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
73 }
74
75 if (op & SI_SAVE_FRAMEBUFFER)
76 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
77
78 if (op & SI_SAVE_TEXTURES) {
79 util_blitter_save_fragment_sampler_states(
80 sctx->blitter, 2,
81 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
82
83 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
84 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
85 }
86
87 if (op & SI_DISABLE_RENDER_COND)
88 sctx->b.render_cond_force_off = true;
89 }
90
91 static void si_blitter_end(struct pipe_context *ctx)
92 {
93 struct si_context *sctx = (struct si_context *)ctx;
94
95 sctx->b.render_cond_force_off = false;
96 }
97
98 static unsigned u_max_sample(struct pipe_resource *r)
99 {
100 return r->nr_samples ? r->nr_samples - 1 : 0;
101 }
102
103 static unsigned
104 si_blit_dbcb_copy(struct si_context *sctx,
105 struct r600_texture *src,
106 struct r600_texture *dst,
107 unsigned planes, unsigned level_mask,
108 unsigned first_layer, unsigned last_layer,
109 unsigned first_sample, unsigned last_sample)
110 {
111 struct pipe_surface surf_tmpl = {{0}};
112 unsigned layer, sample, checked_last_layer, max_layer;
113 unsigned fully_copied_levels = 0;
114
115 if (planes & PIPE_MASK_Z)
116 sctx->dbcb_depth_copy_enabled = true;
117 if (planes & PIPE_MASK_S)
118 sctx->dbcb_stencil_copy_enabled = true;
119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
120
121 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
122
123 while (level_mask) {
124 unsigned level = u_bit_scan(&level_mask);
125
126 /* The smaller the mipmap level, the less layers there are
127 * as far as 3D textures are concerned. */
128 max_layer = util_max_layer(&src->resource.b.b, level);
129 checked_last_layer = MIN2(last_layer, max_layer);
130
131 surf_tmpl.u.tex.level = level;
132
133 for (layer = first_layer; layer <= checked_last_layer; layer++) {
134 struct pipe_surface *zsurf, *cbsurf;
135
136 surf_tmpl.format = src->resource.b.b.format;
137 surf_tmpl.u.tex.first_layer = layer;
138 surf_tmpl.u.tex.last_layer = layer;
139
140 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
141
142 surf_tmpl.format = dst->resource.b.b.format;
143 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
144
145 for (sample = first_sample; sample <= last_sample; sample++) {
146 if (sample != sctx->dbcb_copy_sample) {
147 sctx->dbcb_copy_sample = sample;
148 si_mark_atom_dirty(sctx, &sctx->db_render_state);
149 }
150
151 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
152 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
153 sctx->custom_dsa_flush, 1.0f);
154 si_blitter_end(&sctx->b.b);
155 }
156
157 pipe_surface_reference(&zsurf, NULL);
158 pipe_surface_reference(&cbsurf, NULL);
159 }
160
161 if (first_layer == 0 && last_layer >= max_layer &&
162 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
163 fully_copied_levels |= 1u << level;
164 }
165
166 sctx->dbcb_depth_copy_enabled = false;
167 sctx->dbcb_stencil_copy_enabled = false;
168 si_mark_atom_dirty(sctx, &sctx->db_render_state);
169
170 return fully_copied_levels;
171 }
172
173 static void si_blit_decompress_depth(struct pipe_context *ctx,
174 struct r600_texture *texture,
175 struct r600_texture *staging,
176 unsigned first_level, unsigned last_level,
177 unsigned first_layer, unsigned last_layer,
178 unsigned first_sample, unsigned last_sample)
179 {
180 const struct util_format_description *desc;
181 unsigned planes = 0;
182
183 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
184
185 desc = util_format_description(staging->resource.b.b.format);
186
187 if (util_format_has_depth(desc))
188 planes |= PIPE_MASK_Z;
189 if (util_format_has_stencil(desc))
190 planes |= PIPE_MASK_S;
191
192 si_blit_dbcb_copy(
193 (struct si_context *)ctx, texture, staging, planes,
194 u_bit_consecutive(first_level, last_level - first_level + 1),
195 first_layer, last_layer, first_sample, last_sample);
196 }
197
198 /* Helper function for si_blit_decompress_zs_in_place.
199 */
200 static void
201 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
202 struct r600_texture *texture,
203 unsigned planes, unsigned level_mask,
204 unsigned first_layer, unsigned last_layer)
205 {
206 struct pipe_surface *zsurf, surf_tmpl = {{0}};
207 unsigned layer, max_layer, checked_last_layer;
208 unsigned fully_decompressed_mask = 0;
209
210 if (!level_mask)
211 return;
212
213 if (planes & PIPE_MASK_S)
214 sctx->db_flush_stencil_inplace = true;
215 if (planes & PIPE_MASK_Z)
216 sctx->db_flush_depth_inplace = true;
217 si_mark_atom_dirty(sctx, &sctx->db_render_state);
218
219 surf_tmpl.format = texture->resource.b.b.format;
220
221 while (level_mask) {
222 unsigned level = u_bit_scan(&level_mask);
223
224 surf_tmpl.u.tex.level = level;
225
226 /* The smaller the mipmap level, the less layers there are
227 * as far as 3D textures are concerned. */
228 max_layer = util_max_layer(&texture->resource.b.b, level);
229 checked_last_layer = MIN2(last_layer, max_layer);
230
231 for (layer = first_layer; layer <= checked_last_layer; layer++) {
232 surf_tmpl.u.tex.first_layer = layer;
233 surf_tmpl.u.tex.last_layer = layer;
234
235 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
236
237 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
238 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
239 sctx->custom_dsa_flush,
240 1.0f);
241 si_blitter_end(&sctx->b.b);
242
243 pipe_surface_reference(&zsurf, NULL);
244 }
245
246 /* The texture will always be dirty if some layers aren't flushed.
247 * I don't think this case occurs often though. */
248 if (first_layer == 0 && last_layer >= max_layer) {
249 fully_decompressed_mask |= 1u << level;
250 }
251 }
252
253 if (planes & PIPE_MASK_Z)
254 texture->dirty_level_mask &= ~fully_decompressed_mask;
255 if (planes & PIPE_MASK_S)
256 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
257
258 sctx->db_flush_depth_inplace = false;
259 sctx->db_flush_stencil_inplace = false;
260 si_mark_atom_dirty(sctx, &sctx->db_render_state);
261 }
262
263 /* Helper function of si_flush_depth_texture: decompress the given levels
264 * of Z and/or S planes in place.
265 */
266 static void
267 si_blit_decompress_zs_in_place(struct si_context *sctx,
268 struct r600_texture *texture,
269 unsigned levels_z, unsigned levels_s,
270 unsigned first_layer, unsigned last_layer)
271 {
272 unsigned both = levels_z & levels_s;
273
274 /* First, do combined Z & S decompresses for levels that need it. */
275 if (both) {
276 si_blit_decompress_zs_planes_in_place(
277 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
278 both,
279 first_layer, last_layer);
280 levels_z &= ~both;
281 levels_s &= ~both;
282 }
283
284 /* Now do separate Z and S decompresses. */
285 if (levels_z) {
286 si_blit_decompress_zs_planes_in_place(
287 sctx, texture, PIPE_MASK_Z,
288 levels_z,
289 first_layer, last_layer);
290 }
291
292 if (levels_s) {
293 si_blit_decompress_zs_planes_in_place(
294 sctx, texture, PIPE_MASK_S,
295 levels_s,
296 first_layer, last_layer);
297 }
298 }
299
300 static void
301 si_flush_depth_texture(struct si_context *sctx,
302 struct r600_texture *tex,
303 unsigned required_planes,
304 unsigned first_level, unsigned last_level,
305 unsigned first_layer, unsigned last_layer)
306 {
307 unsigned inplace_planes = 0;
308 unsigned copy_planes = 0;
309 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
310 unsigned levels_z = 0;
311 unsigned levels_s = 0;
312
313 if (required_planes & PIPE_MASK_Z) {
314 levels_z = level_mask & tex->dirty_level_mask;
315
316 if (levels_z) {
317 if (r600_can_sample_zs(tex, false))
318 inplace_planes |= PIPE_MASK_Z;
319 else
320 copy_planes |= PIPE_MASK_Z;
321 }
322 }
323 if (required_planes & PIPE_MASK_S) {
324 levels_s = level_mask & tex->stencil_dirty_level_mask;
325
326 if (levels_s) {
327 if (r600_can_sample_zs(tex, true))
328 inplace_planes |= PIPE_MASK_S;
329 else
330 copy_planes |= PIPE_MASK_S;
331 }
332 }
333
334 assert(!tex->tc_compatible_htile || levels_z == 0);
335
336 /* We may have to allocate the flushed texture here when called from
337 * si_decompress_subresource.
338 */
339 if (copy_planes &&
340 (tex->flushed_depth_texture ||
341 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
342 struct r600_texture *dst = tex->flushed_depth_texture;
343 unsigned fully_copied_levels;
344 unsigned levels = 0;
345
346 assert(tex->flushed_depth_texture);
347
348 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
349 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
350
351 if (copy_planes & PIPE_MASK_Z) {
352 levels |= levels_z;
353 levels_z = 0;
354 }
355 if (copy_planes & PIPE_MASK_S) {
356 levels |= levels_s;
357 levels_s = 0;
358 }
359
360 fully_copied_levels = si_blit_dbcb_copy(
361 sctx, tex, dst, copy_planes, levels,
362 first_layer, last_layer,
363 0, u_max_sample(&tex->resource.b.b));
364
365 if (copy_planes & PIPE_MASK_Z)
366 tex->dirty_level_mask &= ~fully_copied_levels;
367 if (copy_planes & PIPE_MASK_S)
368 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
369 }
370
371 if (inplace_planes) {
372 si_blit_decompress_zs_in_place(
373 sctx, tex,
374 levels_z, levels_s,
375 first_layer, last_layer);
376 }
377 }
378
379 static void
380 si_flush_depth_textures(struct si_context *sctx,
381 struct si_textures_info *textures)
382 {
383 unsigned i;
384 unsigned mask = textures->depth_texture_mask;
385
386 while (mask) {
387 struct pipe_sampler_view *view;
388 struct si_sampler_view *sview;
389 struct r600_texture *tex;
390
391 i = u_bit_scan(&mask);
392
393 view = textures->views.views[i];
394 assert(view);
395 sview = (struct si_sampler_view*)view;
396
397 tex = (struct r600_texture *)view->texture;
398 assert(tex->db_compatible);
399
400 si_flush_depth_texture(
401 sctx, tex,
402 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
403 view->u.tex.first_level, view->u.tex.last_level,
404 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
405 }
406 }
407
408 static void si_blit_decompress_color(struct pipe_context *ctx,
409 struct r600_texture *rtex,
410 unsigned first_level, unsigned last_level,
411 unsigned first_layer, unsigned last_layer,
412 bool need_dcc_decompress)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 void* custom_blend;
416 unsigned layer, checked_last_layer, max_layer;
417 unsigned level_mask =
418 u_bit_consecutive(first_level, last_level - first_level + 1);
419
420 if (!need_dcc_decompress)
421 level_mask &= rtex->dirty_level_mask;
422 if (!level_mask)
423 return;
424
425 if (rtex->dcc_offset && need_dcc_decompress) {
426 custom_blend = sctx->custom_blend_dcc_decompress;
427
428 /* disable levels without DCC */
429 for (int i = first_level; i <= last_level; i++) {
430 if (!rtex->dcc_offset ||
431 i >= rtex->surface.num_dcc_levels)
432 level_mask &= ~(1 << i);
433 }
434 } else if (rtex->fmask.size) {
435 custom_blend = sctx->custom_blend_decompress;
436 } else {
437 custom_blend = sctx->custom_blend_fastclear;
438 }
439
440 while (level_mask) {
441 unsigned level = u_bit_scan(&level_mask);
442
443 /* The smaller the mipmap level, the less layers there are
444 * as far as 3D textures are concerned. */
445 max_layer = util_max_layer(&rtex->resource.b.b, level);
446 checked_last_layer = MIN2(last_layer, max_layer);
447
448 for (layer = first_layer; layer <= checked_last_layer; layer++) {
449 struct pipe_surface *cbsurf, surf_tmpl;
450
451 surf_tmpl.format = rtex->resource.b.b.format;
452 surf_tmpl.u.tex.level = level;
453 surf_tmpl.u.tex.first_layer = layer;
454 surf_tmpl.u.tex.last_layer = layer;
455 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
456
457 si_blitter_begin(ctx, SI_DECOMPRESS);
458 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
459 si_blitter_end(ctx);
460
461 pipe_surface_reference(&cbsurf, NULL);
462 }
463
464 /* The texture will always be dirty if some layers aren't flushed.
465 * I don't think this case occurs often though. */
466 if (first_layer == 0 && last_layer >= max_layer) {
467 rtex->dirty_level_mask &= ~(1 << level);
468 }
469 }
470 }
471
472 static void
473 si_decompress_sampler_color_textures(struct si_context *sctx,
474 struct si_textures_info *textures)
475 {
476 unsigned i;
477 unsigned mask = textures->compressed_colortex_mask;
478
479 while (mask) {
480 struct pipe_sampler_view *view;
481 struct r600_texture *tex;
482
483 i = u_bit_scan(&mask);
484
485 view = textures->views.views[i];
486 assert(view);
487
488 tex = (struct r600_texture *)view->texture;
489 /* CMASK or DCC can be discarded and we can still end up here. */
490 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
491 continue;
492
493 si_blit_decompress_color(&sctx->b.b, tex,
494 view->u.tex.first_level, view->u.tex.last_level,
495 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
496 false);
497 }
498 }
499
500 static void
501 si_decompress_image_color_textures(struct si_context *sctx,
502 struct si_images_info *images)
503 {
504 unsigned i;
505 unsigned mask = images->compressed_colortex_mask;
506
507 while (mask) {
508 const struct pipe_image_view *view;
509 struct r600_texture *tex;
510
511 i = u_bit_scan(&mask);
512
513 view = &images->views[i];
514 assert(view->resource->target != PIPE_BUFFER);
515
516 tex = (struct r600_texture *)view->resource;
517 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
518 continue;
519
520 si_blit_decompress_color(&sctx->b.b, tex,
521 view->u.tex.level, view->u.tex.level,
522 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
523 false);
524 }
525 }
526
527 static void si_check_render_feedback_textures(struct si_context *sctx,
528 struct si_textures_info *textures)
529 {
530 uint32_t mask = textures->views.enabled_mask;
531
532 while (mask) {
533 const struct pipe_sampler_view *view;
534 struct r600_texture *tex;
535 bool render_feedback = false;
536
537 unsigned i = u_bit_scan(&mask);
538
539 view = textures->views.views[i];
540 if(view->texture->target == PIPE_BUFFER)
541 continue;
542
543 tex = (struct r600_texture *)view->texture;
544 if (!tex->dcc_offset)
545 continue;
546
547 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
548 struct r600_surface * surf;
549
550 if (!sctx->framebuffer.state.cbufs[j])
551 continue;
552
553 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
554
555 if (tex == (struct r600_texture*)surf->base.texture &&
556 surf->base.u.tex.level >= view->u.tex.first_level &&
557 surf->base.u.tex.level <= view->u.tex.last_level &&
558 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
559 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
560 render_feedback = true;
561 }
562
563 if (render_feedback)
564 r600_texture_disable_dcc(&sctx->b, tex);
565 }
566 }
567
568 static void si_check_render_feedback_images(struct si_context *sctx,
569 struct si_images_info *images)
570 {
571 uint32_t mask = images->enabled_mask;
572
573 while (mask) {
574 const struct pipe_image_view *view;
575 struct r600_texture *tex;
576 bool render_feedback = false;
577
578 unsigned i = u_bit_scan(&mask);
579
580 view = &images->views[i];
581 if (view->resource->target == PIPE_BUFFER)
582 continue;
583
584 tex = (struct r600_texture *)view->resource;
585 if (!tex->dcc_offset)
586 continue;
587
588 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
589 struct r600_surface * surf;
590
591 if (!sctx->framebuffer.state.cbufs[j])
592 continue;
593
594 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
595
596 if (tex == (struct r600_texture*)surf->base.texture &&
597 surf->base.u.tex.level == view->u.tex.level &&
598 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
599 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
600 render_feedback = true;
601 }
602
603 if (render_feedback)
604 r600_texture_disable_dcc(&sctx->b, tex);
605 }
606 }
607
608 static void si_check_render_feedback(struct si_context *sctx)
609 {
610
611 if (!sctx->need_check_render_feedback)
612 return;
613
614 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
615 si_check_render_feedback_images(sctx, &sctx->images[i]);
616 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
617 }
618 sctx->need_check_render_feedback = false;
619 }
620
621 static void si_decompress_textures(struct si_context *sctx, int shader_start,
622 int shader_end)
623 {
624 unsigned compressed_colortex_counter;
625
626 if (sctx->blitter->running)
627 return;
628
629 /* Update the compressed_colortex_mask if necessary. */
630 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
631 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
632 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
633 si_update_compressed_colortex_masks(sctx);
634 }
635
636 /* Flush depth textures which need to be flushed. */
637 for (int i = shader_start; i < shader_end; i++) {
638 if (sctx->samplers[i].depth_texture_mask) {
639 si_flush_depth_textures(sctx, &sctx->samplers[i]);
640 }
641 if (sctx->samplers[i].compressed_colortex_mask) {
642 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
643 }
644 if (sctx->images[i].compressed_colortex_mask) {
645 si_decompress_image_color_textures(sctx, &sctx->images[i]);
646 }
647 }
648
649 si_check_render_feedback(sctx);
650 }
651
652 void si_decompress_graphics_textures(struct si_context *sctx)
653 {
654 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
655 }
656
657 void si_decompress_compute_textures(struct si_context *sctx)
658 {
659 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
660 }
661
662 static void si_clear(struct pipe_context *ctx, unsigned buffers,
663 const union pipe_color_union *color,
664 double depth, unsigned stencil)
665 {
666 struct si_context *sctx = (struct si_context *)ctx;
667 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
668 struct pipe_surface *zsbuf = fb->zsbuf;
669 struct r600_texture *zstex =
670 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
671
672 if (buffers & PIPE_CLEAR_COLOR) {
673 evergreen_do_fast_color_clear(&sctx->b, fb,
674 &sctx->framebuffer.atom, &buffers,
675 &sctx->framebuffer.dirty_cbufs,
676 color);
677 if (!buffers)
678 return; /* all buffers have been fast cleared */
679 }
680
681 if (buffers & PIPE_CLEAR_COLOR) {
682 int i;
683
684 /* These buffers cannot use fast clear, make sure to disable expansion. */
685 for (i = 0; i < fb->nr_cbufs; i++) {
686 struct r600_texture *tex;
687
688 /* If not clearing this buffer, skip. */
689 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
690 continue;
691
692 if (!fb->cbufs[i])
693 continue;
694
695 tex = (struct r600_texture *)fb->cbufs[i]->texture;
696 if (tex->fmask.size == 0)
697 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
698 }
699 }
700
701 if (zstex && zstex->htile_buffer &&
702 zsbuf->u.tex.level == 0 &&
703 zsbuf->u.tex.first_layer == 0 &&
704 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
705 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
706 if (buffers & PIPE_CLEAR_DEPTH &&
707 (!zstex->tc_compatible_htile ||
708 depth == 0 || depth == 1)) {
709 /* Need to disable EXPCLEAR temporarily if clearing
710 * to a new value. */
711 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
712 sctx->db_depth_disable_expclear = true;
713 }
714
715 zstex->depth_clear_value = depth;
716 sctx->framebuffer.dirty_zsbuf = true;
717 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
718 sctx->db_depth_clear = true;
719 si_mark_atom_dirty(sctx, &sctx->db_render_state);
720 }
721
722 /* TC-compatible HTILE only supports stencil clears to 0. */
723 if (buffers & PIPE_CLEAR_STENCIL &&
724 (!zstex->tc_compatible_htile || stencil == 0)) {
725 stencil &= 0xff;
726
727 /* Need to disable EXPCLEAR temporarily if clearing
728 * to a new value. */
729 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
730 sctx->db_stencil_disable_expclear = true;
731 }
732
733 zstex->stencil_clear_value = stencil;
734 sctx->framebuffer.dirty_zsbuf = true;
735 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
736 sctx->db_stencil_clear = true;
737 si_mark_atom_dirty(sctx, &sctx->db_render_state);
738 }
739 }
740
741 si_blitter_begin(ctx, SI_CLEAR);
742 util_blitter_clear(sctx->blitter, fb->width, fb->height,
743 util_framebuffer_get_num_layers(fb),
744 buffers, color, depth, stencil);
745 si_blitter_end(ctx);
746
747 if (sctx->db_depth_clear) {
748 sctx->db_depth_clear = false;
749 sctx->db_depth_disable_expclear = false;
750 zstex->depth_cleared = true;
751 si_mark_atom_dirty(sctx, &sctx->db_render_state);
752 }
753
754 if (sctx->db_stencil_clear) {
755 sctx->db_stencil_clear = false;
756 sctx->db_stencil_disable_expclear = false;
757 zstex->stencil_cleared = true;
758 si_mark_atom_dirty(sctx, &sctx->db_render_state);
759 }
760 }
761
762 static void si_clear_render_target(struct pipe_context *ctx,
763 struct pipe_surface *dst,
764 const union pipe_color_union *color,
765 unsigned dstx, unsigned dsty,
766 unsigned width, unsigned height,
767 bool render_condition_enabled)
768 {
769 struct si_context *sctx = (struct si_context *)ctx;
770
771 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
772 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
773 util_blitter_clear_render_target(sctx->blitter, dst, color,
774 dstx, dsty, width, height);
775 si_blitter_end(ctx);
776 }
777
778 static void si_clear_depth_stencil(struct pipe_context *ctx,
779 struct pipe_surface *dst,
780 unsigned clear_flags,
781 double depth,
782 unsigned stencil,
783 unsigned dstx, unsigned dsty,
784 unsigned width, unsigned height,
785 bool render_condition_enabled)
786 {
787 struct si_context *sctx = (struct si_context *)ctx;
788
789 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
790 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
791 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
792 dstx, dsty, width, height);
793 si_blitter_end(ctx);
794 }
795
796 /* Helper for decompressing a portion of a color or depth resource before
797 * blitting if any decompression is needed.
798 * The driver doesn't decompress resources automatically while u_blitter is
799 * rendering. */
800 static void si_decompress_subresource(struct pipe_context *ctx,
801 struct pipe_resource *tex,
802 unsigned planes, unsigned level,
803 unsigned first_layer, unsigned last_layer)
804 {
805 struct si_context *sctx = (struct si_context *)ctx;
806 struct r600_texture *rtex = (struct r600_texture*)tex;
807
808 if (rtex->db_compatible) {
809 planes &= PIPE_MASK_Z | PIPE_MASK_S;
810
811 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
812 planes &= ~PIPE_MASK_S;
813
814 si_flush_depth_texture(sctx, rtex, planes,
815 level, level,
816 first_layer, last_layer);
817 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
818 si_blit_decompress_color(ctx, rtex, level, level,
819 first_layer, last_layer, false);
820 }
821 }
822
823 struct texture_orig_info {
824 unsigned format;
825 unsigned width0;
826 unsigned height0;
827 unsigned npix_x;
828 unsigned npix_y;
829 unsigned npix0_x;
830 unsigned npix0_y;
831 };
832
833 void si_resource_copy_region(struct pipe_context *ctx,
834 struct pipe_resource *dst,
835 unsigned dst_level,
836 unsigned dstx, unsigned dsty, unsigned dstz,
837 struct pipe_resource *src,
838 unsigned src_level,
839 const struct pipe_box *src_box)
840 {
841 struct si_context *sctx = (struct si_context *)ctx;
842 struct r600_texture *rsrc = (struct r600_texture*)src;
843 struct pipe_surface *dst_view, dst_templ;
844 struct pipe_sampler_view src_templ, *src_view;
845 unsigned dst_width, dst_height, src_width0, src_height0;
846 unsigned src_force_level = 0;
847 struct pipe_box sbox, dstbox;
848
849 /* Handle buffers first. */
850 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
851 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
852 return;
853 }
854
855 assert(u_max_sample(dst) == u_max_sample(src));
856
857 /* The driver doesn't decompress resources automatically while
858 * u_blitter is rendering. */
859 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
860 src_box->z, src_box->z + src_box->depth - 1);
861
862 dst_width = u_minify(dst->width0, dst_level);
863 dst_height = u_minify(dst->height0, dst_level);
864 src_width0 = src->width0;
865 src_height0 = src->height0;
866
867 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
868 util_blitter_default_src_texture(&src_templ, src, src_level);
869
870 if (util_format_is_compressed(src->format) ||
871 util_format_is_compressed(dst->format)) {
872 unsigned blocksize = rsrc->surface.bpe;
873
874 if (blocksize == 8)
875 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
876 else
877 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
878 dst_templ.format = src_templ.format;
879
880 dst_width = util_format_get_nblocksx(dst->format, dst_width);
881 dst_height = util_format_get_nblocksy(dst->format, dst_height);
882 src_width0 = util_format_get_nblocksx(src->format, src_width0);
883 src_height0 = util_format_get_nblocksy(src->format, src_height0);
884
885 dstx = util_format_get_nblocksx(dst->format, dstx);
886 dsty = util_format_get_nblocksy(dst->format, dsty);
887
888 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
889 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
890 sbox.z = src_box->z;
891 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
892 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
893 sbox.depth = src_box->depth;
894 src_box = &sbox;
895
896 src_force_level = src_level;
897 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
898 /* also *8_SNORM has precision issues, use UNORM instead */
899 util_format_is_snorm8(src->format)) {
900 if (util_format_is_subsampled_422(src->format)) {
901 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
902 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
903
904 dst_width = util_format_get_nblocksx(dst->format, dst_width);
905 src_width0 = util_format_get_nblocksx(src->format, src_width0);
906
907 dstx = util_format_get_nblocksx(dst->format, dstx);
908
909 sbox = *src_box;
910 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
911 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
912 src_box = &sbox;
913 } else {
914 unsigned blocksize = rsrc->surface.bpe;
915
916 switch (blocksize) {
917 case 1:
918 dst_templ.format = PIPE_FORMAT_R8_UNORM;
919 src_templ.format = PIPE_FORMAT_R8_UNORM;
920 break;
921 case 2:
922 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
923 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
924 break;
925 case 4:
926 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
927 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
928 break;
929 case 8:
930 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
931 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
932 break;
933 case 16:
934 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
935 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
936 break;
937 default:
938 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
939 util_format_short_name(src->format), blocksize);
940 assert(0);
941 }
942 }
943 }
944
945 /* Initialize the surface. */
946 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
947 dst_width, dst_height);
948
949 /* Initialize the sampler view. */
950 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
951 src_width0, src_height0,
952 src_force_level);
953
954 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
955 abs(src_box->depth), &dstbox);
956
957 /* Copy. */
958 si_blitter_begin(ctx, SI_COPY);
959 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
960 src_view, src_box, src_width0, src_height0,
961 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
962 false);
963 si_blitter_end(ctx);
964
965 pipe_surface_reference(&dst_view, NULL);
966 pipe_sampler_view_reference(&src_view, NULL);
967 }
968
969 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
970 const struct pipe_blit_info *info)
971 {
972 struct si_context *sctx = (struct si_context*)ctx;
973 struct r600_texture *src = (struct r600_texture*)info->src.resource;
974 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
975 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
976 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
977 enum pipe_format format = info->src.format;
978 unsigned sample_mask = ~0;
979 struct pipe_resource *tmp, templ;
980 struct pipe_blit_info blit;
981
982 /* Check basic requirements for hw resolve. */
983 if (!(info->src.resource->nr_samples > 1 &&
984 info->dst.resource->nr_samples <= 1 &&
985 !util_format_is_pure_integer(format) &&
986 !util_format_is_depth_or_stencil(format) &&
987 util_max_layer(info->src.resource, 0) == 0))
988 return false;
989
990 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
991 * the format is R16G16. Use R16A16, which does work.
992 */
993 if (format == PIPE_FORMAT_R16G16_UNORM)
994 format = PIPE_FORMAT_R16A16_UNORM;
995 if (format == PIPE_FORMAT_R16G16_SNORM)
996 format = PIPE_FORMAT_R16A16_SNORM;
997
998 /* Check the remaining requirements for hw resolve. */
999 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1000 !info->scissor_enable &&
1001 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1002 util_is_format_compatible(util_format_description(info->src.format),
1003 util_format_description(info->dst.format)) &&
1004 dst_width == info->src.resource->width0 &&
1005 dst_height == info->src.resource->height0 &&
1006 info->dst.box.x == 0 &&
1007 info->dst.box.y == 0 &&
1008 info->dst.box.width == dst_width &&
1009 info->dst.box.height == dst_height &&
1010 info->dst.box.depth == 1 &&
1011 info->src.box.x == 0 &&
1012 info->src.box.y == 0 &&
1013 info->src.box.width == dst_width &&
1014 info->src.box.height == dst_height &&
1015 info->src.box.depth == 1 &&
1016 !dst->surface.is_linear &&
1017 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1018 /* Check the last constraint. */
1019 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1020 /* The next fast clear will switch to this mode to
1021 * get direct hw resolve next time if the mode is
1022 * different now.
1023 */
1024 src->last_msaa_resolve_target_micro_mode =
1025 dst->surface.micro_tile_mode;
1026 goto resolve_to_temp;
1027 }
1028
1029 /* Resolving into a surface with DCC is unsupported. Since
1030 * it's being overwritten anyway, clear it to uncompressed.
1031 * This is still the fastest codepath even with this clear.
1032 */
1033 if (dst->dcc_offset &&
1034 info->dst.level < dst->surface.num_dcc_levels) {
1035 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1036 0xFFFFFFFF);
1037 dst->dirty_level_mask &= ~(1 << info->dst.level);
1038 }
1039
1040 /* Resolve directly from src to dst. */
1041 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1042 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1043 util_blitter_custom_resolve_color(sctx->blitter,
1044 info->dst.resource, info->dst.level,
1045 info->dst.box.z,
1046 info->src.resource, info->src.box.z,
1047 sample_mask, sctx->custom_blend_resolve,
1048 format);
1049 si_blitter_end(ctx);
1050 return true;
1051 }
1052
1053 resolve_to_temp:
1054 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1055 * a temporary texture and blit.
1056 */
1057 memset(&templ, 0, sizeof(templ));
1058 templ.target = PIPE_TEXTURE_2D;
1059 templ.format = info->src.resource->format;
1060 templ.width0 = info->src.resource->width0;
1061 templ.height0 = info->src.resource->height0;
1062 templ.depth0 = 1;
1063 templ.array_size = 1;
1064 templ.usage = PIPE_USAGE_DEFAULT;
1065 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1066 R600_RESOURCE_FLAG_DISABLE_DCC;
1067
1068 /* The src and dst microtile modes must be the same. */
1069 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1070 templ.bind = PIPE_BIND_SCANOUT;
1071 else
1072 templ.bind = 0;
1073
1074 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1075 if (!tmp)
1076 return false;
1077
1078 assert(src->surface.micro_tile_mode ==
1079 ((struct r600_texture*)tmp)->surface.micro_tile_mode);
1080
1081 /* resolve */
1082 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1083 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1084 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1085 info->src.resource, info->src.box.z,
1086 sample_mask, sctx->custom_blend_resolve,
1087 format);
1088 si_blitter_end(ctx);
1089
1090 /* blit */
1091 blit = *info;
1092 blit.src.resource = tmp;
1093 blit.src.box.z = 0;
1094
1095 si_blitter_begin(ctx, SI_BLIT |
1096 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1097 util_blitter_blit(sctx->blitter, &blit);
1098 si_blitter_end(ctx);
1099
1100 pipe_resource_reference(&tmp, NULL);
1101 return true;
1102 }
1103
1104 static void si_blit(struct pipe_context *ctx,
1105 const struct pipe_blit_info *info)
1106 {
1107 struct si_context *sctx = (struct si_context*)ctx;
1108 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1109
1110 if (do_hardware_msaa_resolve(ctx, info)) {
1111 return;
1112 }
1113
1114 /* Using SDMA for copying to a linear texture in GTT is much faster.
1115 * This improves DRI PRIME performance.
1116 *
1117 * resource_copy_region can't do this yet, because dma_copy calls it
1118 * on failure (recursion).
1119 */
1120 if (rdst->surface.is_linear &&
1121 sctx->b.dma_copy &&
1122 util_can_blit_via_copy_region(info, false)) {
1123 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1124 info->dst.box.x, info->dst.box.y,
1125 info->dst.box.z,
1126 info->src.resource, info->src.level,
1127 &info->src.box);
1128 return;
1129 }
1130
1131 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1132
1133 /* The driver doesn't decompress resources automatically while
1134 * u_blitter is rendering. */
1135 vi_dcc_disable_if_incompatible_format(&sctx->b, info->src.resource,
1136 info->src.level,
1137 info->src.format);
1138 vi_dcc_disable_if_incompatible_format(&sctx->b, info->dst.resource,
1139 info->dst.level,
1140 info->dst.format);
1141 si_decompress_subresource(ctx, info->src.resource, info->mask,
1142 info->src.level,
1143 info->src.box.z,
1144 info->src.box.z + info->src.box.depth - 1);
1145
1146 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1147 util_try_blit_via_copy_region(ctx, info))
1148 return;
1149
1150 si_blitter_begin(ctx, SI_BLIT |
1151 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1152 util_blitter_blit(sctx->blitter, info);
1153 si_blitter_end(ctx);
1154 }
1155
1156 static boolean si_generate_mipmap(struct pipe_context *ctx,
1157 struct pipe_resource *tex,
1158 enum pipe_format format,
1159 unsigned base_level, unsigned last_level,
1160 unsigned first_layer, unsigned last_layer)
1161 {
1162 struct si_context *sctx = (struct si_context*)ctx;
1163 struct r600_texture *rtex = (struct r600_texture *)tex;
1164
1165 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1166 return false;
1167
1168 /* The driver doesn't decompress resources automatically while
1169 * u_blitter is rendering. */
1170 vi_dcc_disable_if_incompatible_format(&sctx->b, tex, base_level,
1171 format);
1172 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1173 base_level, first_layer, last_layer);
1174
1175 /* Clear dirty_level_mask for the levels that will be overwritten. */
1176 assert(base_level < last_level);
1177 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1178 last_level - base_level);
1179
1180 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1181 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1182 base_level, last_level,
1183 first_layer, last_layer);
1184 si_blitter_end(ctx);
1185 return true;
1186 }
1187
1188 static void si_flush_resource(struct pipe_context *ctx,
1189 struct pipe_resource *res)
1190 {
1191 struct r600_texture *rtex = (struct r600_texture*)res;
1192
1193 assert(res->target != PIPE_BUFFER);
1194 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1195
1196 /* st/dri calls flush twice per frame (not a bug), this prevents double
1197 * decompression. */
1198 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1199 return;
1200
1201 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1202 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1203 0, util_max_layer(res, 0),
1204 rtex->dcc_separate_buffer != NULL);
1205 }
1206
1207 /* Always do the analysis even if DCC is disabled at the moment. */
1208 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1209 rtex->separate_dcc_dirty = false;
1210 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1211 }
1212 }
1213
1214 static void si_decompress_dcc(struct pipe_context *ctx,
1215 struct r600_texture *rtex)
1216 {
1217 if (!rtex->dcc_offset)
1218 return;
1219
1220 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1221 0, util_max_layer(&rtex->resource.b.b, 0),
1222 true);
1223 }
1224
1225 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1226 struct pipe_resource *dst,
1227 unsigned offset, unsigned size,
1228 const void *clear_value_ptr,
1229 int clear_value_size)
1230 {
1231 struct si_context *sctx = (struct si_context*)ctx;
1232 uint32_t dword_value;
1233 unsigned i;
1234
1235 assert(offset % clear_value_size == 0);
1236 assert(size % clear_value_size == 0);
1237
1238 if (clear_value_size > 4) {
1239 const uint32_t *u32 = clear_value_ptr;
1240 bool clear_dword_duplicated = true;
1241
1242 /* See if we can lower large fills to dword fills. */
1243 for (i = 1; i < clear_value_size / 4; i++)
1244 if (u32[0] != u32[i]) {
1245 clear_dword_duplicated = false;
1246 break;
1247 }
1248
1249 if (!clear_dword_duplicated) {
1250 /* Use transform feedback for 64-bit, 96-bit, and
1251 * 128-bit fills.
1252 */
1253 union pipe_color_union clear_value;
1254
1255 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1256 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1257 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1258 size, clear_value_size / 4,
1259 &clear_value);
1260 si_blitter_end(ctx);
1261 return;
1262 }
1263 }
1264
1265 /* Expand the clear value to a dword. */
1266 switch (clear_value_size) {
1267 case 1:
1268 dword_value = *(uint8_t*)clear_value_ptr;
1269 dword_value |= (dword_value << 8) |
1270 (dword_value << 16) |
1271 (dword_value << 24);
1272 break;
1273 case 2:
1274 dword_value = *(uint16_t*)clear_value_ptr;
1275 dword_value |= dword_value << 16;
1276 break;
1277 default:
1278 dword_value = *(uint32_t*)clear_value_ptr;
1279 }
1280
1281 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1282 R600_COHERENCY_SHADER);
1283 }
1284
1285 void si_init_blit_functions(struct si_context *sctx)
1286 {
1287 sctx->b.b.clear = si_clear;
1288 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1289 sctx->b.b.clear_render_target = si_clear_render_target;
1290 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1291 sctx->b.b.resource_copy_region = si_resource_copy_region;
1292 sctx->b.b.blit = si_blit;
1293 sctx->b.b.flush_resource = si_flush_resource;
1294 sctx->b.b.generate_mipmap = si_generate_mipmap;
1295 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1296 sctx->b.decompress_dcc = si_decompress_dcc;
1297 }