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radeonsi: isolate real framebuffer changes from the decompression passes (v3)
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
56 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
57 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
58 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
59 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
60 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
61 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
62 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
63 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
64
65 if (op & SI_SAVE_FRAGMENT_STATE) {
66 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
67 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
68 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
69 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
70 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
71 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
72 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
73 }
74
75 if (op & SI_SAVE_FRAMEBUFFER)
76 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
77
78 if (op & SI_SAVE_TEXTURES) {
79 util_blitter_save_fragment_sampler_states(
80 sctx->blitter, 2,
81 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
82
83 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
84 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
85 }
86
87 if (op & SI_DISABLE_RENDER_COND)
88 sctx->b.render_cond_force_off = true;
89 }
90
91 static void si_blitter_end(struct pipe_context *ctx)
92 {
93 struct si_context *sctx = (struct si_context *)ctx;
94
95 sctx->b.render_cond_force_off = false;
96 }
97
98 static unsigned u_max_sample(struct pipe_resource *r)
99 {
100 return r->nr_samples ? r->nr_samples - 1 : 0;
101 }
102
103 static unsigned
104 si_blit_dbcb_copy(struct si_context *sctx,
105 struct r600_texture *src,
106 struct r600_texture *dst,
107 unsigned planes, unsigned level_mask,
108 unsigned first_layer, unsigned last_layer,
109 unsigned first_sample, unsigned last_sample)
110 {
111 struct pipe_surface surf_tmpl = {{0}};
112 unsigned layer, sample, checked_last_layer, max_layer;
113 unsigned fully_copied_levels = 0;
114
115 if (planes & PIPE_MASK_Z)
116 sctx->dbcb_depth_copy_enabled = true;
117 if (planes & PIPE_MASK_S)
118 sctx->dbcb_stencil_copy_enabled = true;
119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
120
121 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
122
123 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
124 sctx->decompression_enabled = true;
125 sctx->framebuffer.do_update_surf_dirtiness = false;
126
127 while (level_mask) {
128 unsigned level = u_bit_scan(&level_mask);
129
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer = util_max_layer(&src->resource.b.b, level);
133 checked_last_layer = MIN2(last_layer, max_layer);
134
135 surf_tmpl.u.tex.level = level;
136
137 for (layer = first_layer; layer <= checked_last_layer; layer++) {
138 struct pipe_surface *zsurf, *cbsurf;
139
140 surf_tmpl.format = src->resource.b.b.format;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = dst->resource.b.b.format;
147 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
148
149 for (sample = first_sample; sample <= last_sample; sample++) {
150 if (sample != sctx->dbcb_copy_sample) {
151 sctx->dbcb_copy_sample = sample;
152 si_mark_atom_dirty(sctx, &sctx->db_render_state);
153 }
154
155 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
156 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
157 sctx->custom_dsa_flush, 1.0f);
158 si_blitter_end(&sctx->b.b);
159 }
160
161 pipe_surface_reference(&zsurf, NULL);
162 pipe_surface_reference(&cbsurf, NULL);
163 }
164
165 if (first_layer == 0 && last_layer >= max_layer &&
166 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
167 fully_copied_levels |= 1u << level;
168 }
169
170 sctx->decompression_enabled = false;
171 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
172 sctx->dbcb_depth_copy_enabled = false;
173 sctx->dbcb_stencil_copy_enabled = false;
174 si_mark_atom_dirty(sctx, &sctx->db_render_state);
175
176 return fully_copied_levels;
177 }
178
179 static void si_blit_decompress_depth(struct pipe_context *ctx,
180 struct r600_texture *texture,
181 struct r600_texture *staging,
182 unsigned first_level, unsigned last_level,
183 unsigned first_layer, unsigned last_layer,
184 unsigned first_sample, unsigned last_sample)
185 {
186 const struct util_format_description *desc;
187 unsigned planes = 0;
188
189 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
190
191 desc = util_format_description(staging->resource.b.b.format);
192
193 if (util_format_has_depth(desc))
194 planes |= PIPE_MASK_Z;
195 if (util_format_has_stencil(desc))
196 planes |= PIPE_MASK_S;
197
198 si_blit_dbcb_copy(
199 (struct si_context *)ctx, texture, staging, planes,
200 u_bit_consecutive(first_level, last_level - first_level + 1),
201 first_layer, last_layer, first_sample, last_sample);
202 }
203
204 /* Helper function for si_blit_decompress_zs_in_place.
205 */
206 static void
207 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
208 struct r600_texture *texture,
209 unsigned planes, unsigned level_mask,
210 unsigned first_layer, unsigned last_layer)
211 {
212 struct pipe_surface *zsurf, surf_tmpl = {{0}};
213 unsigned layer, max_layer, checked_last_layer;
214 unsigned fully_decompressed_mask = 0;
215
216 if (!level_mask)
217 return;
218
219 if (planes & PIPE_MASK_S)
220 sctx->db_flush_stencil_inplace = true;
221 if (planes & PIPE_MASK_Z)
222 sctx->db_flush_depth_inplace = true;
223 si_mark_atom_dirty(sctx, &sctx->db_render_state);
224
225 surf_tmpl.format = texture->resource.b.b.format;
226
227 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
228 sctx->decompression_enabled = true;
229 sctx->framebuffer.do_update_surf_dirtiness = false;
230
231 while (level_mask) {
232 unsigned level = u_bit_scan(&level_mask);
233
234 surf_tmpl.u.tex.level = level;
235
236 /* The smaller the mipmap level, the less layers there are
237 * as far as 3D textures are concerned. */
238 max_layer = util_max_layer(&texture->resource.b.b, level);
239 checked_last_layer = MIN2(last_layer, max_layer);
240
241 for (layer = first_layer; layer <= checked_last_layer; layer++) {
242 surf_tmpl.u.tex.first_layer = layer;
243 surf_tmpl.u.tex.last_layer = layer;
244
245 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
246
247 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
248 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
249 sctx->custom_dsa_flush,
250 1.0f);
251 si_blitter_end(&sctx->b.b);
252
253 pipe_surface_reference(&zsurf, NULL);
254 }
255
256 /* The texture will always be dirty if some layers aren't flushed.
257 * I don't think this case occurs often though. */
258 if (first_layer == 0 && last_layer >= max_layer) {
259 fully_decompressed_mask |= 1u << level;
260 }
261 }
262
263 if (planes & PIPE_MASK_Z)
264 texture->dirty_level_mask &= ~fully_decompressed_mask;
265 if (planes & PIPE_MASK_S)
266 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
267
268 sctx->decompression_enabled = false;
269 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
270 sctx->db_flush_depth_inplace = false;
271 sctx->db_flush_stencil_inplace = false;
272 si_mark_atom_dirty(sctx, &sctx->db_render_state);
273 }
274
275 /* Helper function of si_flush_depth_texture: decompress the given levels
276 * of Z and/or S planes in place.
277 */
278 static void
279 si_blit_decompress_zs_in_place(struct si_context *sctx,
280 struct r600_texture *texture,
281 unsigned levels_z, unsigned levels_s,
282 unsigned first_layer, unsigned last_layer)
283 {
284 unsigned both = levels_z & levels_s;
285
286 /* First, do combined Z & S decompresses for levels that need it. */
287 if (both) {
288 si_blit_decompress_zs_planes_in_place(
289 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
290 both,
291 first_layer, last_layer);
292 levels_z &= ~both;
293 levels_s &= ~both;
294 }
295
296 /* Now do separate Z and S decompresses. */
297 if (levels_z) {
298 si_blit_decompress_zs_planes_in_place(
299 sctx, texture, PIPE_MASK_Z,
300 levels_z,
301 first_layer, last_layer);
302 }
303
304 if (levels_s) {
305 si_blit_decompress_zs_planes_in_place(
306 sctx, texture, PIPE_MASK_S,
307 levels_s,
308 first_layer, last_layer);
309 }
310 }
311
312 static void
313 si_flush_depth_texture(struct si_context *sctx,
314 struct r600_texture *tex,
315 unsigned required_planes,
316 unsigned first_level, unsigned last_level,
317 unsigned first_layer, unsigned last_layer)
318 {
319 unsigned inplace_planes = 0;
320 unsigned copy_planes = 0;
321 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
322 unsigned levels_z = 0;
323 unsigned levels_s = 0;
324
325 if (required_planes & PIPE_MASK_Z) {
326 levels_z = level_mask & tex->dirty_level_mask;
327
328 if (levels_z) {
329 if (r600_can_sample_zs(tex, false))
330 inplace_planes |= PIPE_MASK_Z;
331 else
332 copy_planes |= PIPE_MASK_Z;
333 }
334 }
335 if (required_planes & PIPE_MASK_S) {
336 levels_s = level_mask & tex->stencil_dirty_level_mask;
337
338 if (levels_s) {
339 if (r600_can_sample_zs(tex, true))
340 inplace_planes |= PIPE_MASK_S;
341 else
342 copy_planes |= PIPE_MASK_S;
343 }
344 }
345
346 assert(!tex->tc_compatible_htile || levels_z == 0);
347 assert(!tex->tc_compatible_htile || levels_s == 0 ||
348 !r600_can_sample_zs(tex, true));
349
350 /* We may have to allocate the flushed texture here when called from
351 * si_decompress_subresource.
352 */
353 if (copy_planes &&
354 (tex->flushed_depth_texture ||
355 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
356 struct r600_texture *dst = tex->flushed_depth_texture;
357 unsigned fully_copied_levels;
358 unsigned levels = 0;
359
360 assert(tex->flushed_depth_texture);
361
362 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
363 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
364
365 if (copy_planes & PIPE_MASK_Z) {
366 levels |= levels_z;
367 levels_z = 0;
368 }
369 if (copy_planes & PIPE_MASK_S) {
370 levels |= levels_s;
371 levels_s = 0;
372 }
373
374 fully_copied_levels = si_blit_dbcb_copy(
375 sctx, tex, dst, copy_planes, levels,
376 first_layer, last_layer,
377 0, u_max_sample(&tex->resource.b.b));
378
379 if (copy_planes & PIPE_MASK_Z)
380 tex->dirty_level_mask &= ~fully_copied_levels;
381 if (copy_planes & PIPE_MASK_S)
382 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
383 }
384
385 if (inplace_planes) {
386 si_blit_decompress_zs_in_place(
387 sctx, tex,
388 levels_z, levels_s,
389 first_layer, last_layer);
390 }
391 }
392
393 static void
394 si_flush_depth_textures(struct si_context *sctx,
395 struct si_textures_info *textures)
396 {
397 unsigned i;
398 unsigned mask = textures->depth_texture_mask;
399
400 while (mask) {
401 struct pipe_sampler_view *view;
402 struct si_sampler_view *sview;
403 struct r600_texture *tex;
404
405 i = u_bit_scan(&mask);
406
407 view = textures->views.views[i];
408 assert(view);
409 sview = (struct si_sampler_view*)view;
410
411 tex = (struct r600_texture *)view->texture;
412 assert(tex->db_compatible);
413
414 si_flush_depth_texture(
415 sctx, tex,
416 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
417 view->u.tex.first_level, view->u.tex.last_level,
418 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
419 }
420 }
421
422 static void si_blit_decompress_color(struct pipe_context *ctx,
423 struct r600_texture *rtex,
424 unsigned first_level, unsigned last_level,
425 unsigned first_layer, unsigned last_layer,
426 bool need_dcc_decompress)
427 {
428 struct si_context *sctx = (struct si_context *)ctx;
429 void* custom_blend;
430 unsigned layer, checked_last_layer, max_layer;
431 unsigned level_mask =
432 u_bit_consecutive(first_level, last_level - first_level + 1);
433
434 if (!need_dcc_decompress)
435 level_mask &= rtex->dirty_level_mask;
436 if (!level_mask)
437 return;
438
439 if (rtex->dcc_offset && need_dcc_decompress) {
440 custom_blend = sctx->custom_blend_dcc_decompress;
441
442 /* disable levels without DCC */
443 for (int i = first_level; i <= last_level; i++) {
444 if (!vi_dcc_enabled(rtex, i))
445 level_mask &= ~(1 << i);
446 }
447 } else if (rtex->fmask.size) {
448 custom_blend = sctx->custom_blend_fmask_decompress;
449 } else {
450 custom_blend = sctx->custom_blend_eliminate_fastclear;
451 }
452
453 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
454 sctx->decompression_enabled = true;
455 sctx->framebuffer.do_update_surf_dirtiness = false;
456
457 while (level_mask) {
458 unsigned level = u_bit_scan(&level_mask);
459
460 /* The smaller the mipmap level, the less layers there are
461 * as far as 3D textures are concerned. */
462 max_layer = util_max_layer(&rtex->resource.b.b, level);
463 checked_last_layer = MIN2(last_layer, max_layer);
464
465 for (layer = first_layer; layer <= checked_last_layer; layer++) {
466 struct pipe_surface *cbsurf, surf_tmpl;
467
468 surf_tmpl.format = rtex->resource.b.b.format;
469 surf_tmpl.u.tex.level = level;
470 surf_tmpl.u.tex.first_layer = layer;
471 surf_tmpl.u.tex.last_layer = layer;
472 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
473
474 si_blitter_begin(ctx, SI_DECOMPRESS);
475 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
476 si_blitter_end(ctx);
477
478 pipe_surface_reference(&cbsurf, NULL);
479 }
480
481 /* The texture will always be dirty if some layers aren't flushed.
482 * I don't think this case occurs often though. */
483 if (first_layer == 0 && last_layer >= max_layer) {
484 rtex->dirty_level_mask &= ~(1 << level);
485 }
486 }
487
488 sctx->decompression_enabled = false;
489 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
490 }
491
492 static void
493 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
494 unsigned first_level, unsigned last_level)
495 {
496 /* CMASK or DCC can be discarded and we can still end up here. */
497 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
498 return;
499
500 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
501 util_max_layer(&tex->resource.b.b, first_level),
502 false);
503 }
504
505 static void
506 si_decompress_sampler_color_textures(struct si_context *sctx,
507 struct si_textures_info *textures)
508 {
509 unsigned i;
510 unsigned mask = textures->compressed_colortex_mask;
511
512 while (mask) {
513 struct pipe_sampler_view *view;
514 struct r600_texture *tex;
515
516 i = u_bit_scan(&mask);
517
518 view = textures->views.views[i];
519 assert(view);
520
521 tex = (struct r600_texture *)view->texture;
522
523 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
524 view->u.tex.last_level);
525 }
526 }
527
528 static void
529 si_decompress_image_color_textures(struct si_context *sctx,
530 struct si_images_info *images)
531 {
532 unsigned i;
533 unsigned mask = images->compressed_colortex_mask;
534
535 while (mask) {
536 const struct pipe_image_view *view;
537 struct r600_texture *tex;
538
539 i = u_bit_scan(&mask);
540
541 view = &images->views[i];
542 assert(view->resource->target != PIPE_BUFFER);
543
544 tex = (struct r600_texture *)view->resource;
545
546 si_decompress_color_texture(sctx, tex, view->u.tex.level,
547 view->u.tex.level);
548 }
549 }
550
551 static void si_check_render_feedback_texture(struct si_context *sctx,
552 struct r600_texture *tex,
553 unsigned first_level,
554 unsigned last_level,
555 unsigned first_layer,
556 unsigned last_layer)
557 {
558 bool render_feedback = false;
559
560 if (!tex->dcc_offset)
561 return;
562
563 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
564 struct r600_surface * surf;
565
566 if (!sctx->framebuffer.state.cbufs[j])
567 continue;
568
569 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
570
571 if (tex == (struct r600_texture *)surf->base.texture &&
572 surf->base.u.tex.level >= first_level &&
573 surf->base.u.tex.level <= last_level &&
574 surf->base.u.tex.first_layer <= last_layer &&
575 surf->base.u.tex.last_layer >= first_layer) {
576 render_feedback = true;
577 break;
578 }
579 }
580
581 if (render_feedback)
582 r600_texture_disable_dcc(&sctx->b, tex);
583 }
584
585 static void si_check_render_feedback_textures(struct si_context *sctx,
586 struct si_textures_info *textures)
587 {
588 uint32_t mask = textures->views.enabled_mask;
589
590 while (mask) {
591 const struct pipe_sampler_view *view;
592 struct r600_texture *tex;
593
594 unsigned i = u_bit_scan(&mask);
595
596 view = textures->views.views[i];
597 if(view->texture->target == PIPE_BUFFER)
598 continue;
599
600 tex = (struct r600_texture *)view->texture;
601
602 si_check_render_feedback_texture(sctx, tex,
603 view->u.tex.first_level,
604 view->u.tex.last_level,
605 view->u.tex.first_layer,
606 view->u.tex.last_layer);
607 }
608 }
609
610 static void si_check_render_feedback_images(struct si_context *sctx,
611 struct si_images_info *images)
612 {
613 uint32_t mask = images->enabled_mask;
614
615 while (mask) {
616 const struct pipe_image_view *view;
617 struct r600_texture *tex;
618
619 unsigned i = u_bit_scan(&mask);
620
621 view = &images->views[i];
622 if (view->resource->target == PIPE_BUFFER)
623 continue;
624
625 tex = (struct r600_texture *)view->resource;
626
627 si_check_render_feedback_texture(sctx, tex,
628 view->u.tex.level,
629 view->u.tex.level,
630 view->u.tex.first_layer,
631 view->u.tex.last_layer);
632 }
633 }
634
635 static void si_check_render_feedback(struct si_context *sctx)
636 {
637
638 if (!sctx->need_check_render_feedback)
639 return;
640
641 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
642 si_check_render_feedback_images(sctx, &sctx->images[i]);
643 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
644 }
645 sctx->need_check_render_feedback = false;
646 }
647
648 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
649 {
650 unsigned compressed_colortex_counter, mask;
651
652 if (sctx->blitter->running)
653 return;
654
655 /* Update the compressed_colortex_mask if necessary. */
656 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
657 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
658 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
659 si_update_compressed_colortex_masks(sctx);
660 }
661
662 /* Decompress color & depth textures if needed. */
663 mask = sctx->compressed_tex_shader_mask & shader_mask;
664 while (mask) {
665 unsigned i = u_bit_scan(&mask);
666
667 if (sctx->samplers[i].depth_texture_mask) {
668 si_flush_depth_textures(sctx, &sctx->samplers[i]);
669 }
670 if (sctx->samplers[i].compressed_colortex_mask) {
671 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
672 }
673 if (sctx->images[i].compressed_colortex_mask) {
674 si_decompress_image_color_textures(sctx, &sctx->images[i]);
675 }
676 }
677
678 si_check_render_feedback(sctx);
679 }
680
681 void si_decompress_graphics_textures(struct si_context *sctx)
682 {
683 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
684 }
685
686 void si_decompress_compute_textures(struct si_context *sctx)
687 {
688 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
689 }
690
691 static void si_clear(struct pipe_context *ctx, unsigned buffers,
692 const union pipe_color_union *color,
693 double depth, unsigned stencil)
694 {
695 struct si_context *sctx = (struct si_context *)ctx;
696 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
697 struct pipe_surface *zsbuf = fb->zsbuf;
698 struct r600_texture *zstex =
699 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
700
701 if (buffers & PIPE_CLEAR_COLOR) {
702 evergreen_do_fast_color_clear(&sctx->b, fb,
703 &sctx->framebuffer.atom, &buffers,
704 &sctx->framebuffer.dirty_cbufs,
705 color);
706 if (!buffers)
707 return; /* all buffers have been fast cleared */
708 }
709
710 if (buffers & PIPE_CLEAR_COLOR) {
711 int i;
712
713 /* These buffers cannot use fast clear, make sure to disable expansion. */
714 for (i = 0; i < fb->nr_cbufs; i++) {
715 struct r600_texture *tex;
716
717 /* If not clearing this buffer, skip. */
718 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
719 continue;
720
721 if (!fb->cbufs[i])
722 continue;
723
724 tex = (struct r600_texture *)fb->cbufs[i]->texture;
725 if (tex->fmask.size == 0)
726 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
727 }
728 }
729
730 if (zstex && zstex->htile_buffer &&
731 zsbuf->u.tex.level == 0 &&
732 zsbuf->u.tex.first_layer == 0 &&
733 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
734 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
735 if (buffers & PIPE_CLEAR_DEPTH &&
736 (!zstex->tc_compatible_htile ||
737 depth == 0 || depth == 1)) {
738 /* Need to disable EXPCLEAR temporarily if clearing
739 * to a new value. */
740 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
741 sctx->db_depth_disable_expclear = true;
742 }
743
744 zstex->depth_clear_value = depth;
745 sctx->framebuffer.dirty_zsbuf = true;
746 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
747 sctx->db_depth_clear = true;
748 si_mark_atom_dirty(sctx, &sctx->db_render_state);
749 }
750
751 /* TC-compatible HTILE only supports stencil clears to 0. */
752 if (buffers & PIPE_CLEAR_STENCIL &&
753 (!zstex->tc_compatible_htile || stencil == 0)) {
754 stencil &= 0xff;
755
756 /* Need to disable EXPCLEAR temporarily if clearing
757 * to a new value. */
758 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
759 sctx->db_stencil_disable_expclear = true;
760 }
761
762 zstex->stencil_clear_value = stencil;
763 sctx->framebuffer.dirty_zsbuf = true;
764 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
765 sctx->db_stencil_clear = true;
766 si_mark_atom_dirty(sctx, &sctx->db_render_state);
767 }
768 }
769
770 si_blitter_begin(ctx, SI_CLEAR);
771 util_blitter_clear(sctx->blitter, fb->width, fb->height,
772 util_framebuffer_get_num_layers(fb),
773 buffers, color, depth, stencil);
774 si_blitter_end(ctx);
775
776 if (sctx->db_depth_clear) {
777 sctx->db_depth_clear = false;
778 sctx->db_depth_disable_expclear = false;
779 zstex->depth_cleared = true;
780 si_mark_atom_dirty(sctx, &sctx->db_render_state);
781 }
782
783 if (sctx->db_stencil_clear) {
784 sctx->db_stencil_clear = false;
785 sctx->db_stencil_disable_expclear = false;
786 zstex->stencil_cleared = true;
787 si_mark_atom_dirty(sctx, &sctx->db_render_state);
788 }
789 }
790
791 static void si_clear_render_target(struct pipe_context *ctx,
792 struct pipe_surface *dst,
793 const union pipe_color_union *color,
794 unsigned dstx, unsigned dsty,
795 unsigned width, unsigned height,
796 bool render_condition_enabled)
797 {
798 struct si_context *sctx = (struct si_context *)ctx;
799
800 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
801 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
802 util_blitter_clear_render_target(sctx->blitter, dst, color,
803 dstx, dsty, width, height);
804 si_blitter_end(ctx);
805 }
806
807 static void si_clear_depth_stencil(struct pipe_context *ctx,
808 struct pipe_surface *dst,
809 unsigned clear_flags,
810 double depth,
811 unsigned stencil,
812 unsigned dstx, unsigned dsty,
813 unsigned width, unsigned height,
814 bool render_condition_enabled)
815 {
816 struct si_context *sctx = (struct si_context *)ctx;
817
818 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
819 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
820 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
821 dstx, dsty, width, height);
822 si_blitter_end(ctx);
823 }
824
825 /* Helper for decompressing a portion of a color or depth resource before
826 * blitting if any decompression is needed.
827 * The driver doesn't decompress resources automatically while u_blitter is
828 * rendering. */
829 static void si_decompress_subresource(struct pipe_context *ctx,
830 struct pipe_resource *tex,
831 unsigned planes, unsigned level,
832 unsigned first_layer, unsigned last_layer)
833 {
834 struct si_context *sctx = (struct si_context *)ctx;
835 struct r600_texture *rtex = (struct r600_texture*)tex;
836
837 if (rtex->db_compatible) {
838 planes &= PIPE_MASK_Z | PIPE_MASK_S;
839
840 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
841 planes &= ~PIPE_MASK_S;
842
843 si_flush_depth_texture(sctx, rtex, planes,
844 level, level,
845 first_layer, last_layer);
846 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
847 si_blit_decompress_color(ctx, rtex, level, level,
848 first_layer, last_layer, false);
849 }
850 }
851
852 struct texture_orig_info {
853 unsigned format;
854 unsigned width0;
855 unsigned height0;
856 unsigned npix_x;
857 unsigned npix_y;
858 unsigned npix0_x;
859 unsigned npix0_y;
860 };
861
862 void si_resource_copy_region(struct pipe_context *ctx,
863 struct pipe_resource *dst,
864 unsigned dst_level,
865 unsigned dstx, unsigned dsty, unsigned dstz,
866 struct pipe_resource *src,
867 unsigned src_level,
868 const struct pipe_box *src_box)
869 {
870 struct si_context *sctx = (struct si_context *)ctx;
871 struct r600_texture *rsrc = (struct r600_texture*)src;
872 struct pipe_surface *dst_view, dst_templ;
873 struct pipe_sampler_view src_templ, *src_view;
874 unsigned dst_width, dst_height, src_width0, src_height0;
875 unsigned dst_width0, dst_height0, src_force_level = 0;
876 struct pipe_box sbox, dstbox;
877
878 /* Handle buffers first. */
879 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
880 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
881 return;
882 }
883
884 assert(u_max_sample(dst) == u_max_sample(src));
885
886 /* The driver doesn't decompress resources automatically while
887 * u_blitter is rendering. */
888 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
889 src_box->z, src_box->z + src_box->depth - 1);
890
891 dst_width = u_minify(dst->width0, dst_level);
892 dst_height = u_minify(dst->height0, dst_level);
893 dst_width0 = dst->width0;
894 dst_height0 = dst->height0;
895 src_width0 = src->width0;
896 src_height0 = src->height0;
897
898 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
899 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
900
901 if (util_format_is_compressed(src->format) ||
902 util_format_is_compressed(dst->format)) {
903 unsigned blocksize = rsrc->surface.bpe;
904
905 if (blocksize == 8)
906 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
907 else
908 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
909 dst_templ.format = src_templ.format;
910
911 dst_width = util_format_get_nblocksx(dst->format, dst_width);
912 dst_height = util_format_get_nblocksy(dst->format, dst_height);
913 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
914 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
915 src_width0 = util_format_get_nblocksx(src->format, src_width0);
916 src_height0 = util_format_get_nblocksy(src->format, src_height0);
917
918 dstx = util_format_get_nblocksx(dst->format, dstx);
919 dsty = util_format_get_nblocksy(dst->format, dsty);
920
921 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
922 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
923 sbox.z = src_box->z;
924 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
925 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
926 sbox.depth = src_box->depth;
927 src_box = &sbox;
928
929 src_force_level = src_level;
930 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
931 if (util_format_is_subsampled_422(src->format)) {
932 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
933 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
934
935 dst_width = util_format_get_nblocksx(dst->format, dst_width);
936 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
937 src_width0 = util_format_get_nblocksx(src->format, src_width0);
938
939 dstx = util_format_get_nblocksx(dst->format, dstx);
940
941 sbox = *src_box;
942 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
943 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
944 src_box = &sbox;
945 } else {
946 unsigned blocksize = rsrc->surface.bpe;
947
948 switch (blocksize) {
949 case 1:
950 dst_templ.format = PIPE_FORMAT_R8_UNORM;
951 src_templ.format = PIPE_FORMAT_R8_UNORM;
952 break;
953 case 2:
954 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
955 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
956 break;
957 case 4:
958 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
959 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
960 break;
961 case 8:
962 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
963 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
964 break;
965 case 16:
966 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
967 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
968 break;
969 default:
970 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
971 util_format_short_name(src->format), blocksize);
972 assert(0);
973 }
974 }
975 }
976
977 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
978 dst_templ.format);
979 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
980 src_templ.format);
981
982 /* Initialize the surface. */
983 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
984 dst_width0, dst_height0,
985 dst_width, dst_height);
986
987 /* Initialize the sampler view. */
988 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
989 src_width0, src_height0,
990 src_force_level);
991
992 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
993 abs(src_box->depth), &dstbox);
994
995 /* Copy. */
996 si_blitter_begin(ctx, SI_COPY);
997 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
998 src_view, src_box, src_width0, src_height0,
999 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1000 false);
1001 si_blitter_end(ctx);
1002
1003 pipe_surface_reference(&dst_view, NULL);
1004 pipe_sampler_view_reference(&src_view, NULL);
1005 }
1006
1007 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1008 const struct pipe_blit_info *info)
1009 {
1010 struct si_context *sctx = (struct si_context*)ctx;
1011 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1012 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1013 MAYBE_UNUSED struct r600_texture *rtmp;
1014 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1015 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1016 enum pipe_format format = info->src.format;
1017 unsigned sample_mask = ~0;
1018 struct pipe_resource *tmp, templ;
1019 struct pipe_blit_info blit;
1020
1021 /* Check basic requirements for hw resolve. */
1022 if (!(info->src.resource->nr_samples > 1 &&
1023 info->dst.resource->nr_samples <= 1 &&
1024 !util_format_is_pure_integer(format) &&
1025 !util_format_is_depth_or_stencil(format) &&
1026 util_max_layer(info->src.resource, 0) == 0))
1027 return false;
1028
1029 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1030 * the format is R16G16. Use R16A16, which does work.
1031 */
1032 if (format == PIPE_FORMAT_R16G16_UNORM)
1033 format = PIPE_FORMAT_R16A16_UNORM;
1034 if (format == PIPE_FORMAT_R16G16_SNORM)
1035 format = PIPE_FORMAT_R16A16_SNORM;
1036
1037 /* Check the remaining requirements for hw resolve. */
1038 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1039 !info->scissor_enable &&
1040 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1041 util_is_format_compatible(util_format_description(info->src.format),
1042 util_format_description(info->dst.format)) &&
1043 dst_width == info->src.resource->width0 &&
1044 dst_height == info->src.resource->height0 &&
1045 info->dst.box.x == 0 &&
1046 info->dst.box.y == 0 &&
1047 info->dst.box.width == dst_width &&
1048 info->dst.box.height == dst_height &&
1049 info->dst.box.depth == 1 &&
1050 info->src.box.x == 0 &&
1051 info->src.box.y == 0 &&
1052 info->src.box.width == dst_width &&
1053 info->src.box.height == dst_height &&
1054 info->src.box.depth == 1 &&
1055 !dst->surface.is_linear &&
1056 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1057 /* Check the last constraint. */
1058 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1059 /* The next fast clear will switch to this mode to
1060 * get direct hw resolve next time if the mode is
1061 * different now.
1062 */
1063 src->last_msaa_resolve_target_micro_mode =
1064 dst->surface.micro_tile_mode;
1065 goto resolve_to_temp;
1066 }
1067
1068 /* Resolving into a surface with DCC is unsupported. Since
1069 * it's being overwritten anyway, clear it to uncompressed.
1070 * This is still the fastest codepath even with this clear.
1071 */
1072 if (vi_dcc_enabled(dst, info->dst.level)) {
1073 /* TODO: Implement per-level DCC clears for GFX9. */
1074 if (sctx->b.chip_class >= GFX9 &&
1075 info->dst.resource->last_level != 0)
1076 goto resolve_to_temp;
1077
1078 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1079 0xFFFFFFFF);
1080 dst->dirty_level_mask &= ~(1 << info->dst.level);
1081 }
1082
1083 /* Resolve directly from src to dst. */
1084 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1085 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1086 util_blitter_custom_resolve_color(sctx->blitter,
1087 info->dst.resource, info->dst.level,
1088 info->dst.box.z,
1089 info->src.resource, info->src.box.z,
1090 sample_mask, sctx->custom_blend_resolve,
1091 format);
1092 si_blitter_end(ctx);
1093 return true;
1094 }
1095
1096 resolve_to_temp:
1097 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1098 * a temporary texture and blit.
1099 */
1100 memset(&templ, 0, sizeof(templ));
1101 templ.target = PIPE_TEXTURE_2D;
1102 templ.format = info->src.resource->format;
1103 templ.width0 = info->src.resource->width0;
1104 templ.height0 = info->src.resource->height0;
1105 templ.depth0 = 1;
1106 templ.array_size = 1;
1107 templ.usage = PIPE_USAGE_DEFAULT;
1108 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1109 R600_RESOURCE_FLAG_DISABLE_DCC;
1110
1111 /* The src and dst microtile modes must be the same. */
1112 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1113 templ.bind = PIPE_BIND_SCANOUT;
1114 else
1115 templ.bind = 0;
1116
1117 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1118 if (!tmp)
1119 return false;
1120 rtmp = (struct r600_texture*)tmp;
1121
1122 assert(!rtmp->surface.is_linear);
1123 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1124
1125 /* resolve */
1126 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1127 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1128 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1129 info->src.resource, info->src.box.z,
1130 sample_mask, sctx->custom_blend_resolve,
1131 format);
1132 si_blitter_end(ctx);
1133
1134 /* blit */
1135 blit = *info;
1136 blit.src.resource = tmp;
1137 blit.src.box.z = 0;
1138
1139 si_blitter_begin(ctx, SI_BLIT |
1140 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1141 util_blitter_blit(sctx->blitter, &blit);
1142 si_blitter_end(ctx);
1143
1144 pipe_resource_reference(&tmp, NULL);
1145 return true;
1146 }
1147
1148 static void si_blit(struct pipe_context *ctx,
1149 const struct pipe_blit_info *info)
1150 {
1151 struct si_context *sctx = (struct si_context*)ctx;
1152 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1153
1154 if (do_hardware_msaa_resolve(ctx, info)) {
1155 return;
1156 }
1157
1158 /* Using SDMA for copying to a linear texture in GTT is much faster.
1159 * This improves DRI PRIME performance.
1160 *
1161 * resource_copy_region can't do this yet, because dma_copy calls it
1162 * on failure (recursion).
1163 */
1164 if (rdst->surface.is_linear &&
1165 sctx->b.dma_copy &&
1166 util_can_blit_via_copy_region(info, false)) {
1167 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1168 info->dst.box.x, info->dst.box.y,
1169 info->dst.box.z,
1170 info->src.resource, info->src.level,
1171 &info->src.box);
1172 return;
1173 }
1174
1175 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1176
1177 /* The driver doesn't decompress resources automatically while
1178 * u_blitter is rendering. */
1179 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1180 info->src.level,
1181 info->src.format);
1182 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1183 info->dst.level,
1184 info->dst.format);
1185 si_decompress_subresource(ctx, info->src.resource, info->mask,
1186 info->src.level,
1187 info->src.box.z,
1188 info->src.box.z + info->src.box.depth - 1);
1189
1190 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1191 util_try_blit_via_copy_region(ctx, info))
1192 return;
1193
1194 si_blitter_begin(ctx, SI_BLIT |
1195 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1196 util_blitter_blit(sctx->blitter, info);
1197 si_blitter_end(ctx);
1198 }
1199
1200 static boolean si_generate_mipmap(struct pipe_context *ctx,
1201 struct pipe_resource *tex,
1202 enum pipe_format format,
1203 unsigned base_level, unsigned last_level,
1204 unsigned first_layer, unsigned last_layer)
1205 {
1206 struct si_context *sctx = (struct si_context*)ctx;
1207 struct r600_texture *rtex = (struct r600_texture *)tex;
1208
1209 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1210 return false;
1211
1212 /* The driver doesn't decompress resources automatically while
1213 * u_blitter is rendering. */
1214 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1215 format);
1216 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1217 base_level, first_layer, last_layer);
1218
1219 /* Clear dirty_level_mask for the levels that will be overwritten. */
1220 assert(base_level < last_level);
1221 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1222 last_level - base_level);
1223
1224 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1225 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1226 base_level, last_level,
1227 first_layer, last_layer);
1228 si_blitter_end(ctx);
1229 return true;
1230 }
1231
1232 static void si_flush_resource(struct pipe_context *ctx,
1233 struct pipe_resource *res)
1234 {
1235 struct r600_texture *rtex = (struct r600_texture*)res;
1236
1237 assert(res->target != PIPE_BUFFER);
1238 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1239
1240 /* st/dri calls flush twice per frame (not a bug), this prevents double
1241 * decompression. */
1242 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1243 return;
1244
1245 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1246 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1247 0, util_max_layer(res, 0),
1248 rtex->dcc_separate_buffer != NULL);
1249 }
1250
1251 /* Always do the analysis even if DCC is disabled at the moment. */
1252 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1253 rtex->separate_dcc_dirty = false;
1254 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1255 }
1256 }
1257
1258 static void si_decompress_dcc(struct pipe_context *ctx,
1259 struct r600_texture *rtex)
1260 {
1261 if (!rtex->dcc_offset)
1262 return;
1263
1264 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1265 0, util_max_layer(&rtex->resource.b.b, 0),
1266 true);
1267 }
1268
1269 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1270 struct pipe_resource *dst,
1271 unsigned offset, unsigned size,
1272 const void *clear_value_ptr,
1273 int clear_value_size)
1274 {
1275 struct si_context *sctx = (struct si_context*)ctx;
1276 uint32_t dword_value;
1277 unsigned i;
1278
1279 assert(offset % clear_value_size == 0);
1280 assert(size % clear_value_size == 0);
1281
1282 if (clear_value_size > 4) {
1283 const uint32_t *u32 = clear_value_ptr;
1284 bool clear_dword_duplicated = true;
1285
1286 /* See if we can lower large fills to dword fills. */
1287 for (i = 1; i < clear_value_size / 4; i++)
1288 if (u32[0] != u32[i]) {
1289 clear_dword_duplicated = false;
1290 break;
1291 }
1292
1293 if (!clear_dword_duplicated) {
1294 /* Use transform feedback for 64-bit, 96-bit, and
1295 * 128-bit fills.
1296 */
1297 union pipe_color_union clear_value;
1298
1299 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1300 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1301 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1302 size, clear_value_size / 4,
1303 &clear_value);
1304 si_blitter_end(ctx);
1305 return;
1306 }
1307 }
1308
1309 /* Expand the clear value to a dword. */
1310 switch (clear_value_size) {
1311 case 1:
1312 dword_value = *(uint8_t*)clear_value_ptr;
1313 dword_value |= (dword_value << 8) |
1314 (dword_value << 16) |
1315 (dword_value << 24);
1316 break;
1317 case 2:
1318 dword_value = *(uint16_t*)clear_value_ptr;
1319 dword_value |= dword_value << 16;
1320 break;
1321 default:
1322 dword_value = *(uint32_t*)clear_value_ptr;
1323 }
1324
1325 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1326 R600_COHERENCY_SHADER);
1327 }
1328
1329 void si_init_blit_functions(struct si_context *sctx)
1330 {
1331 sctx->b.b.clear = si_clear;
1332 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1333 sctx->b.b.clear_render_target = si_clear_render_target;
1334 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1335 sctx->b.b.resource_copy_region = si_resource_copy_region;
1336 sctx->b.b.blit = si_blit;
1337 sctx->b.b.flush_resource = si_flush_resource;
1338 sctx->b.b.generate_mipmap = si_generate_mipmap;
1339 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1340 sctx->b.decompress_dcc = si_decompress_dcc;
1341 }