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[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
62 util_blitter_save_window_rectangles(sctx->blitter,
63 sctx->window_rectangles_include,
64 sctx->num_window_rectangles,
65 sctx->window_rectangles);
66 }
67
68 if (op & SI_SAVE_FRAMEBUFFER)
69 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
70
71 if (op & SI_SAVE_TEXTURES) {
72 util_blitter_save_fragment_sampler_states(
73 sctx->blitter, 2,
74 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
75
76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
77 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
78 }
79
80 if (op & SI_DISABLE_RENDER_COND)
81 sctx->render_cond_force_off = true;
82
83 if (sctx->screen->dpbb_allowed) {
84 sctx->dpbb_force_off = true;
85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
86 }
87 }
88
89 void si_blitter_end(struct si_context *sctx)
90 {
91 if (sctx->screen->dpbb_allowed) {
92 sctx->dpbb_force_off = false;
93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
94 }
95
96 sctx->render_cond_force_off = false;
97
98 /* Restore shader pointers because the VS blit shader changed all
99 * non-global VS user SGPRs. */
100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
101 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
102 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
103 }
104
105 static unsigned u_max_sample(struct pipe_resource *r)
106 {
107 return r->nr_samples ? r->nr_samples - 1 : 0;
108 }
109
110 static unsigned
111 si_blit_dbcb_copy(struct si_context *sctx,
112 struct si_texture *src,
113 struct si_texture *dst,
114 unsigned planes, unsigned level_mask,
115 unsigned first_layer, unsigned last_layer,
116 unsigned first_sample, unsigned last_sample)
117 {
118 struct pipe_surface surf_tmpl = {{0}};
119 unsigned layer, sample, checked_last_layer, max_layer;
120 unsigned fully_copied_levels = 0;
121
122 if (planes & PIPE_MASK_Z)
123 sctx->dbcb_depth_copy_enabled = true;
124 if (planes & PIPE_MASK_S)
125 sctx->dbcb_stencil_copy_enabled = true;
126 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
127
128 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
129
130 sctx->decompression_enabled = true;
131
132 while (level_mask) {
133 unsigned level = u_bit_scan(&level_mask);
134
135 /* The smaller the mipmap level, the less layers there are
136 * as far as 3D textures are concerned. */
137 max_layer = util_max_layer(&src->buffer.b.b, level);
138 checked_last_layer = MIN2(last_layer, max_layer);
139
140 surf_tmpl.u.tex.level = level;
141
142 for (layer = first_layer; layer <= checked_last_layer; layer++) {
143 struct pipe_surface *zsurf, *cbsurf;
144
145 surf_tmpl.format = src->buffer.b.b.format;
146 surf_tmpl.u.tex.first_layer = layer;
147 surf_tmpl.u.tex.last_layer = layer;
148
149 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
150
151 surf_tmpl.format = dst->buffer.b.b.format;
152 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
153
154 for (sample = first_sample; sample <= last_sample; sample++) {
155 if (sample != sctx->dbcb_copy_sample) {
156 sctx->dbcb_copy_sample = sample;
157 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
158 }
159
160 si_blitter_begin(sctx, SI_DECOMPRESS);
161 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
162 sctx->custom_dsa_flush, 1.0f);
163 si_blitter_end(sctx);
164 }
165
166 pipe_surface_reference(&zsurf, NULL);
167 pipe_surface_reference(&cbsurf, NULL);
168 }
169
170 if (first_layer == 0 && last_layer >= max_layer &&
171 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
172 fully_copied_levels |= 1u << level;
173 }
174
175 sctx->decompression_enabled = false;
176 sctx->dbcb_depth_copy_enabled = false;
177 sctx->dbcb_stencil_copy_enabled = false;
178 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
179
180 return fully_copied_levels;
181 }
182
183 /* Helper function for si_blit_decompress_zs_in_place.
184 */
185 static void
186 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
187 struct si_texture *texture,
188 unsigned planes, unsigned level_mask,
189 unsigned first_layer, unsigned last_layer)
190 {
191 struct pipe_surface *zsurf, surf_tmpl = {{0}};
192 unsigned layer, max_layer, checked_last_layer;
193 unsigned fully_decompressed_mask = 0;
194
195 if (!level_mask)
196 return;
197
198 if (planes & PIPE_MASK_S)
199 sctx->db_flush_stencil_inplace = true;
200 if (planes & PIPE_MASK_Z)
201 sctx->db_flush_depth_inplace = true;
202 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
203
204 surf_tmpl.format = texture->buffer.b.b.format;
205
206 sctx->decompression_enabled = true;
207
208 while (level_mask) {
209 unsigned level = u_bit_scan(&level_mask);
210
211 surf_tmpl.u.tex.level = level;
212
213 /* The smaller the mipmap level, the less layers there are
214 * as far as 3D textures are concerned. */
215 max_layer = util_max_layer(&texture->buffer.b.b, level);
216 checked_last_layer = MIN2(last_layer, max_layer);
217
218 for (layer = first_layer; layer <= checked_last_layer; layer++) {
219 surf_tmpl.u.tex.first_layer = layer;
220 surf_tmpl.u.tex.last_layer = layer;
221
222 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
223
224 si_blitter_begin(sctx, SI_DECOMPRESS);
225 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
226 sctx->custom_dsa_flush,
227 1.0f);
228 si_blitter_end(sctx);
229
230 pipe_surface_reference(&zsurf, NULL);
231 }
232
233 /* The texture will always be dirty if some layers aren't flushed.
234 * I don't think this case occurs often though. */
235 if (first_layer == 0 && last_layer >= max_layer) {
236 fully_decompressed_mask |= 1u << level;
237 }
238 }
239
240 if (planes & PIPE_MASK_Z)
241 texture->dirty_level_mask &= ~fully_decompressed_mask;
242 if (planes & PIPE_MASK_S)
243 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
244
245 sctx->decompression_enabled = false;
246 sctx->db_flush_depth_inplace = false;
247 sctx->db_flush_stencil_inplace = false;
248 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
249 }
250
251 /* Helper function of si_flush_depth_texture: decompress the given levels
252 * of Z and/or S planes in place.
253 */
254 static void
255 si_blit_decompress_zs_in_place(struct si_context *sctx,
256 struct si_texture *texture,
257 unsigned levels_z, unsigned levels_s,
258 unsigned first_layer, unsigned last_layer)
259 {
260 unsigned both = levels_z & levels_s;
261
262 /* First, do combined Z & S decompresses for levels that need it. */
263 if (both) {
264 si_blit_decompress_zs_planes_in_place(
265 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
266 both,
267 first_layer, last_layer);
268 levels_z &= ~both;
269 levels_s &= ~both;
270 }
271
272 /* Now do separate Z and S decompresses. */
273 if (levels_z) {
274 si_blit_decompress_zs_planes_in_place(
275 sctx, texture, PIPE_MASK_Z,
276 levels_z,
277 first_layer, last_layer);
278 }
279
280 if (levels_s) {
281 si_blit_decompress_zs_planes_in_place(
282 sctx, texture, PIPE_MASK_S,
283 levels_s,
284 first_layer, last_layer);
285 }
286 }
287
288 static void
289 si_decompress_depth(struct si_context *sctx,
290 struct si_texture *tex,
291 unsigned required_planes,
292 unsigned first_level, unsigned last_level,
293 unsigned first_layer, unsigned last_layer)
294 {
295 unsigned inplace_planes = 0;
296 unsigned copy_planes = 0;
297 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
298 unsigned levels_z = 0;
299 unsigned levels_s = 0;
300
301 if (required_planes & PIPE_MASK_Z) {
302 levels_z = level_mask & tex->dirty_level_mask;
303
304 if (levels_z) {
305 if (si_can_sample_zs(tex, false))
306 inplace_planes |= PIPE_MASK_Z;
307 else
308 copy_planes |= PIPE_MASK_Z;
309 }
310 }
311 if (required_planes & PIPE_MASK_S) {
312 levels_s = level_mask & tex->stencil_dirty_level_mask;
313
314 if (levels_s) {
315 if (si_can_sample_zs(tex, true))
316 inplace_planes |= PIPE_MASK_S;
317 else
318 copy_planes |= PIPE_MASK_S;
319 }
320 }
321
322 if (unlikely(sctx->log))
323 u_log_printf(sctx->log,
324 "\n------------------------------------------------\n"
325 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
326 first_level, last_level, levels_z, levels_s);
327
328 /* We may have to allocate the flushed texture here when called from
329 * si_decompress_subresource.
330 */
331 if (copy_planes &&
332 (tex->flushed_depth_texture ||
333 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
334 struct si_texture *dst = tex->flushed_depth_texture;
335 unsigned fully_copied_levels;
336 unsigned levels = 0;
337
338 assert(tex->flushed_depth_texture);
339
340 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
341 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
342
343 if (copy_planes & PIPE_MASK_Z) {
344 levels |= levels_z;
345 levels_z = 0;
346 }
347 if (copy_planes & PIPE_MASK_S) {
348 levels |= levels_s;
349 levels_s = 0;
350 }
351
352 fully_copied_levels = si_blit_dbcb_copy(
353 sctx, tex, dst, copy_planes, levels,
354 first_layer, last_layer,
355 0, u_max_sample(&tex->buffer.b.b));
356
357 if (copy_planes & PIPE_MASK_Z)
358 tex->dirty_level_mask &= ~fully_copied_levels;
359 if (copy_planes & PIPE_MASK_S)
360 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
361 }
362
363 if (inplace_planes) {
364 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes);
365 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level,
366 inplace_planes);
367
368 /* Don't decompress if there is no HTILE or when HTILE is
369 * TC-compatible. */
370 if (has_htile && !tc_compat_htile) {
371 si_blit_decompress_zs_in_place(
372 sctx, tex,
373 levels_z, levels_s,
374 first_layer, last_layer);
375 } else {
376 /* This is only a cache flush.
377 *
378 * Only clear the mask that we are flushing, because
379 * si_make_DB_shader_coherent() treats different levels
380 * and depth and stencil differently.
381 */
382 if (inplace_planes & PIPE_MASK_Z)
383 tex->dirty_level_mask &= ~levels_z;
384 if (inplace_planes & PIPE_MASK_S)
385 tex->stencil_dirty_level_mask &= ~levels_s;
386 }
387
388 /* Only in-place decompression needs to flush DB caches, or
389 * when we don't decompress but TC-compatible planes are dirty.
390 */
391 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
392 inplace_planes & PIPE_MASK_S,
393 tc_compat_htile);
394 }
395 /* set_framebuffer_state takes care of coherency for single-sample.
396 * The DB->CB copy uses CB for the final writes.
397 */
398 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
399 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
400 false, true /* no DCC */);
401 }
402
403 static void
404 si_decompress_sampler_depth_textures(struct si_context *sctx,
405 struct si_samplers *textures)
406 {
407 unsigned i;
408 unsigned mask = textures->needs_depth_decompress_mask;
409
410 while (mask) {
411 struct pipe_sampler_view *view;
412 struct si_sampler_view *sview;
413 struct si_texture *tex;
414
415 i = u_bit_scan(&mask);
416
417 view = textures->views[i];
418 assert(view);
419 sview = (struct si_sampler_view*)view;
420
421 tex = (struct si_texture *)view->texture;
422 assert(tex->db_compatible);
423
424 si_decompress_depth(sctx, tex,
425 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
426 view->u.tex.first_level, view->u.tex.last_level,
427 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
428 }
429 }
430
431 static void si_blit_decompress_color(struct si_context *sctx,
432 struct si_texture *tex,
433 unsigned first_level, unsigned last_level,
434 unsigned first_layer, unsigned last_layer,
435 bool need_dcc_decompress)
436 {
437 void* custom_blend;
438 unsigned layer, checked_last_layer, max_layer;
439 unsigned level_mask =
440 u_bit_consecutive(first_level, last_level - first_level + 1);
441
442 if (!need_dcc_decompress)
443 level_mask &= tex->dirty_level_mask;
444 if (!level_mask)
445 return;
446
447 if (unlikely(sctx->log))
448 u_log_printf(sctx->log,
449 "\n------------------------------------------------\n"
450 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
451 first_level, last_level, level_mask);
452
453 if (need_dcc_decompress) {
454 custom_blend = sctx->custom_blend_dcc_decompress;
455
456 assert(tex->dcc_offset);
457
458 /* disable levels without DCC */
459 for (int i = first_level; i <= last_level; i++) {
460 if (!vi_dcc_enabled(tex, i))
461 level_mask &= ~(1 << i);
462 }
463 } else if (tex->surface.fmask_size) {
464 custom_blend = sctx->custom_blend_fmask_decompress;
465 } else {
466 custom_blend = sctx->custom_blend_eliminate_fastclear;
467 }
468
469 sctx->decompression_enabled = true;
470
471 while (level_mask) {
472 unsigned level = u_bit_scan(&level_mask);
473
474 /* The smaller the mipmap level, the less layers there are
475 * as far as 3D textures are concerned. */
476 max_layer = util_max_layer(&tex->buffer.b.b, level);
477 checked_last_layer = MIN2(last_layer, max_layer);
478
479 for (layer = first_layer; layer <= checked_last_layer; layer++) {
480 struct pipe_surface *cbsurf, surf_tmpl;
481
482 surf_tmpl.format = tex->buffer.b.b.format;
483 surf_tmpl.u.tex.level = level;
484 surf_tmpl.u.tex.first_layer = layer;
485 surf_tmpl.u.tex.last_layer = layer;
486 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
487
488 /* Required before and after FMASK and DCC_DECOMPRESS. */
489 if (custom_blend == sctx->custom_blend_fmask_decompress ||
490 custom_blend == sctx->custom_blend_dcc_decompress)
491 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
492
493 si_blitter_begin(sctx, SI_DECOMPRESS);
494 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
495 si_blitter_end(sctx);
496
497 if (custom_blend == sctx->custom_blend_fmask_decompress ||
498 custom_blend == sctx->custom_blend_dcc_decompress)
499 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
500
501 pipe_surface_reference(&cbsurf, NULL);
502 }
503
504 /* The texture will always be dirty if some layers aren't flushed.
505 * I don't think this case occurs often though. */
506 if (first_layer == 0 && last_layer >= max_layer) {
507 tex->dirty_level_mask &= ~(1 << level);
508 }
509 }
510
511 sctx->decompression_enabled = false;
512 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
513 vi_dcc_enabled(tex, first_level),
514 tex->surface.u.gfx9.dcc.pipe_aligned);
515 }
516
517 static void
518 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
519 unsigned first_level, unsigned last_level)
520 {
521 /* CMASK or DCC can be discarded and we can still end up here. */
522 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->dcc_offset)
523 return;
524
525 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
526 util_max_layer(&tex->buffer.b.b, first_level),
527 false);
528 }
529
530 static void
531 si_decompress_sampler_color_textures(struct si_context *sctx,
532 struct si_samplers *textures)
533 {
534 unsigned i;
535 unsigned mask = textures->needs_color_decompress_mask;
536
537 while (mask) {
538 struct pipe_sampler_view *view;
539 struct si_texture *tex;
540
541 i = u_bit_scan(&mask);
542
543 view = textures->views[i];
544 assert(view);
545
546 tex = (struct si_texture *)view->texture;
547
548 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
549 view->u.tex.last_level);
550 }
551 }
552
553 static void
554 si_decompress_image_color_textures(struct si_context *sctx,
555 struct si_images *images)
556 {
557 unsigned i;
558 unsigned mask = images->needs_color_decompress_mask;
559
560 while (mask) {
561 const struct pipe_image_view *view;
562 struct si_texture *tex;
563
564 i = u_bit_scan(&mask);
565
566 view = &images->views[i];
567 assert(view->resource->target != PIPE_BUFFER);
568
569 tex = (struct si_texture *)view->resource;
570
571 si_decompress_color_texture(sctx, tex, view->u.tex.level,
572 view->u.tex.level);
573 }
574 }
575
576 static void si_check_render_feedback_texture(struct si_context *sctx,
577 struct si_texture *tex,
578 unsigned first_level,
579 unsigned last_level,
580 unsigned first_layer,
581 unsigned last_layer)
582 {
583 bool render_feedback = false;
584
585 if (!tex->dcc_offset)
586 return;
587
588 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
589 struct si_surface * surf;
590
591 if (!sctx->framebuffer.state.cbufs[j])
592 continue;
593
594 surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
595
596 if (tex == (struct si_texture *)surf->base.texture &&
597 surf->base.u.tex.level >= first_level &&
598 surf->base.u.tex.level <= last_level &&
599 surf->base.u.tex.first_layer <= last_layer &&
600 surf->base.u.tex.last_layer >= first_layer) {
601 render_feedback = true;
602 break;
603 }
604 }
605
606 if (render_feedback)
607 si_texture_disable_dcc(sctx, tex);
608 }
609
610 static void si_check_render_feedback_textures(struct si_context *sctx,
611 struct si_samplers *textures)
612 {
613 uint32_t mask = textures->enabled_mask;
614
615 while (mask) {
616 const struct pipe_sampler_view *view;
617 struct si_texture *tex;
618
619 unsigned i = u_bit_scan(&mask);
620
621 view = textures->views[i];
622 if(view->texture->target == PIPE_BUFFER)
623 continue;
624
625 tex = (struct si_texture *)view->texture;
626
627 si_check_render_feedback_texture(sctx, tex,
628 view->u.tex.first_level,
629 view->u.tex.last_level,
630 view->u.tex.first_layer,
631 view->u.tex.last_layer);
632 }
633 }
634
635 static void si_check_render_feedback_images(struct si_context *sctx,
636 struct si_images *images)
637 {
638 uint32_t mask = images->enabled_mask;
639
640 while (mask) {
641 const struct pipe_image_view *view;
642 struct si_texture *tex;
643
644 unsigned i = u_bit_scan(&mask);
645
646 view = &images->views[i];
647 if (view->resource->target == PIPE_BUFFER)
648 continue;
649
650 tex = (struct si_texture *)view->resource;
651
652 si_check_render_feedback_texture(sctx, tex,
653 view->u.tex.level,
654 view->u.tex.level,
655 view->u.tex.first_layer,
656 view->u.tex.last_layer);
657 }
658 }
659
660 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
661 {
662 util_dynarray_foreach(&sctx->resident_tex_handles,
663 struct si_texture_handle *, tex_handle) {
664 struct pipe_sampler_view *view;
665 struct si_texture *tex;
666
667 view = (*tex_handle)->view;
668 if (view->texture->target == PIPE_BUFFER)
669 continue;
670
671 tex = (struct si_texture *)view->texture;
672
673 si_check_render_feedback_texture(sctx, tex,
674 view->u.tex.first_level,
675 view->u.tex.last_level,
676 view->u.tex.first_layer,
677 view->u.tex.last_layer);
678 }
679 }
680
681 static void si_check_render_feedback_resident_images(struct si_context *sctx)
682 {
683 util_dynarray_foreach(&sctx->resident_img_handles,
684 struct si_image_handle *, img_handle) {
685 struct pipe_image_view *view;
686 struct si_texture *tex;
687
688 view = &(*img_handle)->view;
689 if (view->resource->target == PIPE_BUFFER)
690 continue;
691
692 tex = (struct si_texture *)view->resource;
693
694 si_check_render_feedback_texture(sctx, tex,
695 view->u.tex.level,
696 view->u.tex.level,
697 view->u.tex.first_layer,
698 view->u.tex.last_layer);
699 }
700 }
701
702 static void si_check_render_feedback(struct si_context *sctx)
703 {
704 if (!sctx->need_check_render_feedback)
705 return;
706
707 /* There is no render feedback if color writes are disabled.
708 * (e.g. a pixel shader with image stores)
709 */
710 if (!si_get_total_colormask(sctx))
711 return;
712
713 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
714 si_check_render_feedback_images(sctx, &sctx->images[i]);
715 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
716 }
717
718 si_check_render_feedback_resident_images(sctx);
719 si_check_render_feedback_resident_textures(sctx);
720
721 sctx->need_check_render_feedback = false;
722 }
723
724 static void si_decompress_resident_textures(struct si_context *sctx)
725 {
726 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
727 struct si_texture_handle *, tex_handle) {
728 struct pipe_sampler_view *view = (*tex_handle)->view;
729 struct si_texture *tex = (struct si_texture *)view->texture;
730
731 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
732 view->u.tex.last_level);
733 }
734
735 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
736 struct si_texture_handle *, tex_handle) {
737 struct pipe_sampler_view *view = (*tex_handle)->view;
738 struct si_sampler_view *sview = (struct si_sampler_view *)view;
739 struct si_texture *tex = (struct si_texture *)view->texture;
740
741 si_decompress_depth(sctx, tex,
742 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
743 view->u.tex.first_level, view->u.tex.last_level,
744 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
745 }
746 }
747
748 static void si_decompress_resident_images(struct si_context *sctx)
749 {
750 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
751 struct si_image_handle *, img_handle) {
752 struct pipe_image_view *view = &(*img_handle)->view;
753 struct si_texture *tex = (struct si_texture *)view->resource;
754
755 si_decompress_color_texture(sctx, tex, view->u.tex.level,
756 view->u.tex.level);
757 }
758 }
759
760 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
761 {
762 unsigned compressed_colortex_counter, mask;
763
764 if (sctx->blitter->running)
765 return;
766
767 /* Update the compressed_colortex_mask if necessary. */
768 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
769 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
770 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
771 si_update_needs_color_decompress_masks(sctx);
772 }
773
774 /* Decompress color & depth textures if needed. */
775 mask = sctx->shader_needs_decompress_mask & shader_mask;
776 while (mask) {
777 unsigned i = u_bit_scan(&mask);
778
779 if (sctx->samplers[i].needs_depth_decompress_mask) {
780 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
781 }
782 if (sctx->samplers[i].needs_color_decompress_mask) {
783 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
784 }
785 if (sctx->images[i].needs_color_decompress_mask) {
786 si_decompress_image_color_textures(sctx, &sctx->images[i]);
787 }
788 }
789
790 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
791 if (sctx->uses_bindless_samplers)
792 si_decompress_resident_textures(sctx);
793 if (sctx->uses_bindless_images)
794 si_decompress_resident_images(sctx);
795
796 if (sctx->ps_uses_fbfetch) {
797 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
798 si_decompress_color_texture(sctx,
799 (struct si_texture*)cb0->texture,
800 cb0->u.tex.first_layer,
801 cb0->u.tex.last_layer);
802 }
803
804 si_check_render_feedback(sctx);
805 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
806 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers)
807 si_decompress_resident_textures(sctx);
808 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images)
809 si_decompress_resident_images(sctx);
810 }
811 }
812
813 /* Helper for decompressing a portion of a color or depth resource before
814 * blitting if any decompression is needed.
815 * The driver doesn't decompress resources automatically while u_blitter is
816 * rendering. */
817 static void si_decompress_subresource(struct pipe_context *ctx,
818 struct pipe_resource *tex,
819 unsigned planes, unsigned level,
820 unsigned first_layer, unsigned last_layer)
821 {
822 struct si_context *sctx = (struct si_context *)ctx;
823 struct si_texture *stex = (struct si_texture*)tex;
824
825 if (stex->db_compatible) {
826 planes &= PIPE_MASK_Z | PIPE_MASK_S;
827
828 if (!stex->surface.has_stencil)
829 planes &= ~PIPE_MASK_S;
830
831 /* If we've rendered into the framebuffer and it's a blitting
832 * source, make sure the decompression pass is invoked
833 * by dirtying the framebuffer.
834 */
835 if (sctx->framebuffer.state.zsbuf &&
836 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
837 sctx->framebuffer.state.zsbuf->texture == tex)
838 si_update_fb_dirtiness_after_rendering(sctx);
839
840 si_decompress_depth(sctx, stex, planes,
841 level, level,
842 first_layer, last_layer);
843 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->dcc_offset) {
844 /* If we've rendered into the framebuffer and it's a blitting
845 * source, make sure the decompression pass is invoked
846 * by dirtying the framebuffer.
847 */
848 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
849 if (sctx->framebuffer.state.cbufs[i] &&
850 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
851 sctx->framebuffer.state.cbufs[i]->texture == tex) {
852 si_update_fb_dirtiness_after_rendering(sctx);
853 break;
854 }
855 }
856
857 si_blit_decompress_color(sctx, stex, level, level,
858 first_layer, last_layer, false);
859 }
860 }
861
862 struct texture_orig_info {
863 unsigned format;
864 unsigned width0;
865 unsigned height0;
866 unsigned npix_x;
867 unsigned npix_y;
868 unsigned npix0_x;
869 unsigned npix0_y;
870 };
871
872 void si_resource_copy_region(struct pipe_context *ctx,
873 struct pipe_resource *dst,
874 unsigned dst_level,
875 unsigned dstx, unsigned dsty, unsigned dstz,
876 struct pipe_resource *src,
877 unsigned src_level,
878 const struct pipe_box *src_box)
879 {
880 struct si_context *sctx = (struct si_context *)ctx;
881 struct si_texture *ssrc = (struct si_texture*)src;
882 struct si_texture *sdst = (struct si_texture*)dst;
883 struct pipe_surface *dst_view, dst_templ;
884 struct pipe_sampler_view src_templ, *src_view;
885 unsigned dst_width, dst_height, src_width0, src_height0;
886 unsigned dst_width0, dst_height0, src_force_level = 0;
887 struct pipe_box sbox, dstbox;
888
889 /* Handle buffers first. */
890 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
891 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
892 return;
893 }
894
895 if (!util_format_is_compressed(src->format) &&
896 !util_format_is_compressed(dst->format) &&
897 !util_format_is_depth_or_stencil(src->format) &&
898 src->nr_samples <= 1 &&
899 !sdst->dcc_offset &&
900 !(dst->target != src->target &&
901 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
902 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
903 return;
904 }
905
906 assert(u_max_sample(dst) == u_max_sample(src));
907
908 /* The driver doesn't decompress resources automatically while
909 * u_blitter is rendering. */
910 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
911 src_box->z, src_box->z + src_box->depth - 1);
912
913 dst_width = u_minify(dst->width0, dst_level);
914 dst_height = u_minify(dst->height0, dst_level);
915 dst_width0 = dst->width0;
916 dst_height0 = dst->height0;
917 src_width0 = src->width0;
918 src_height0 = src->height0;
919
920 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
921 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
922
923 if (util_format_is_compressed(src->format) ||
924 util_format_is_compressed(dst->format)) {
925 unsigned blocksize = ssrc->surface.bpe;
926
927 if (blocksize == 8)
928 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
929 else
930 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
931 dst_templ.format = src_templ.format;
932
933 dst_width = util_format_get_nblocksx(dst->format, dst_width);
934 dst_height = util_format_get_nblocksy(dst->format, dst_height);
935 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
936 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
937 src_width0 = util_format_get_nblocksx(src->format, src_width0);
938 src_height0 = util_format_get_nblocksy(src->format, src_height0);
939
940 dstx = util_format_get_nblocksx(dst->format, dstx);
941 dsty = util_format_get_nblocksy(dst->format, dsty);
942
943 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
944 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
945 sbox.z = src_box->z;
946 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
947 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
948 sbox.depth = src_box->depth;
949 src_box = &sbox;
950
951 src_force_level = src_level;
952 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
953 if (util_format_is_subsampled_422(src->format)) {
954 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
955 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
956
957 dst_width = util_format_get_nblocksx(dst->format, dst_width);
958 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
959 src_width0 = util_format_get_nblocksx(src->format, src_width0);
960
961 dstx = util_format_get_nblocksx(dst->format, dstx);
962
963 sbox = *src_box;
964 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
965 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
966 src_box = &sbox;
967 } else {
968 unsigned blocksize = ssrc->surface.bpe;
969
970 switch (blocksize) {
971 case 1:
972 dst_templ.format = PIPE_FORMAT_R8_UNORM;
973 src_templ.format = PIPE_FORMAT_R8_UNORM;
974 break;
975 case 2:
976 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
977 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
978 break;
979 case 4:
980 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
981 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
982 break;
983 case 8:
984 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
985 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
986 break;
987 case 16:
988 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
989 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
990 break;
991 default:
992 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
993 util_format_short_name(src->format), blocksize);
994 assert(0);
995 }
996 }
997 }
998
999 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1000 * equivalent instead, which doesn't force DCC decompression.
1001 * Note that some chips avoid this issue by using SDMA.
1002 */
1003 if (util_format_is_snorm8(dst_templ.format)) {
1004 dst_templ.format = src_templ.format =
1005 util_format_snorm8_to_sint8(dst_templ.format);
1006 }
1007
1008 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1009 dst_templ.format);
1010 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1011 src_templ.format);
1012
1013 /* Initialize the surface. */
1014 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1015 dst_width0, dst_height0,
1016 dst_width, dst_height);
1017
1018 /* Initialize the sampler view. */
1019 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1020 src_width0, src_height0,
1021 src_force_level);
1022
1023 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1024 abs(src_box->depth), &dstbox);
1025
1026 /* Copy. */
1027 si_blitter_begin(sctx, SI_COPY);
1028 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1029 src_view, src_box, src_width0, src_height0,
1030 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1031 false);
1032 si_blitter_end(sctx);
1033
1034 pipe_surface_reference(&dst_view, NULL);
1035 pipe_sampler_view_reference(&src_view, NULL);
1036 }
1037
1038 static void si_do_CB_resolve(struct si_context *sctx,
1039 const struct pipe_blit_info *info,
1040 struct pipe_resource *dst,
1041 unsigned dst_level, unsigned dst_z,
1042 enum pipe_format format)
1043 {
1044 /* Required before and after CB_RESOLVE. */
1045 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1046
1047 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1048 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1049 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1050 info->src.resource, info->src.box.z,
1051 ~0, sctx->custom_blend_resolve,
1052 format);
1053 si_blitter_end(sctx);
1054
1055 /* Flush caches for possible texturing. */
1056 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
1057 }
1058
1059 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1060 const struct pipe_blit_info *info)
1061 {
1062 struct si_context *sctx = (struct si_context*)ctx;
1063 struct si_texture *src = (struct si_texture*)info->src.resource;
1064 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1065 ASSERTED struct si_texture *stmp;
1066 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1067 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1068 enum pipe_format format = info->src.format;
1069 struct pipe_resource *tmp, templ;
1070 struct pipe_blit_info blit;
1071
1072 /* Check basic requirements for hw resolve. */
1073 if (!(info->src.resource->nr_samples > 1 &&
1074 info->dst.resource->nr_samples <= 1 &&
1075 !util_format_is_pure_integer(format) &&
1076 !util_format_is_depth_or_stencil(format) &&
1077 util_max_layer(info->src.resource, 0) == 0))
1078 return false;
1079
1080 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1081 * the format is R16G16. Use R16A16, which does work.
1082 */
1083 if (format == PIPE_FORMAT_R16G16_UNORM)
1084 format = PIPE_FORMAT_R16A16_UNORM;
1085 if (format == PIPE_FORMAT_R16G16_SNORM)
1086 format = PIPE_FORMAT_R16A16_SNORM;
1087
1088 /* Check the remaining requirements for hw resolve. */
1089 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1090 !info->scissor_enable &&
1091 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1092 util_is_format_compatible(util_format_description(info->src.format),
1093 util_format_description(info->dst.format)) &&
1094 dst_width == info->src.resource->width0 &&
1095 dst_height == info->src.resource->height0 &&
1096 info->dst.box.x == 0 &&
1097 info->dst.box.y == 0 &&
1098 info->dst.box.width == dst_width &&
1099 info->dst.box.height == dst_height &&
1100 info->dst.box.depth == 1 &&
1101 info->src.box.x == 0 &&
1102 info->src.box.y == 0 &&
1103 info->src.box.width == dst_width &&
1104 info->src.box.height == dst_height &&
1105 info->src.box.depth == 1 &&
1106 !dst->surface.is_linear &&
1107 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1108 /* Check the last constraint. */
1109 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1110 /* The next fast clear will switch to this mode to
1111 * get direct hw resolve next time if the mode is
1112 * different now.
1113 *
1114 * TODO-GFX10: This does not work in GFX10 because MSAA
1115 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1116 * In some cases we could change the swizzle of the
1117 * destination texture instead, but the more general
1118 * solution is to implement compute shader resolve.
1119 */
1120 src->last_msaa_resolve_target_micro_mode =
1121 dst->surface.micro_tile_mode;
1122 goto resolve_to_temp;
1123 }
1124
1125 /* Resolving into a surface with DCC is unsupported. Since
1126 * it's being overwritten anyway, clear it to uncompressed.
1127 * This is still the fastest codepath even with this clear.
1128 */
1129 if (vi_dcc_enabled(dst, info->dst.level)) {
1130 if (!vi_dcc_clear_level(sctx, dst, info->dst.level,
1131 DCC_UNCOMPRESSED))
1132 goto resolve_to_temp;
1133
1134 dst->dirty_level_mask &= ~(1 << info->dst.level);
1135 }
1136
1137 /* Resolve directly from src to dst. */
1138 si_do_CB_resolve(sctx, info, info->dst.resource,
1139 info->dst.level, info->dst.box.z, format);
1140 return true;
1141 }
1142
1143 resolve_to_temp:
1144 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1145 * a temporary texture and blit.
1146 */
1147 memset(&templ, 0, sizeof(templ));
1148 templ.target = PIPE_TEXTURE_2D;
1149 templ.format = info->src.resource->format;
1150 templ.width0 = info->src.resource->width0;
1151 templ.height0 = info->src.resource->height0;
1152 templ.depth0 = 1;
1153 templ.array_size = 1;
1154 templ.usage = PIPE_USAGE_DEFAULT;
1155 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
1156 SI_RESOURCE_FLAG_DISABLE_DCC;
1157
1158 /* The src and dst microtile modes must be the same. */
1159 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1160 templ.bind = PIPE_BIND_SCANOUT;
1161 else
1162 templ.bind = 0;
1163
1164 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1165 if (!tmp)
1166 return false;
1167 stmp = (struct si_texture*)tmp;
1168
1169 assert(!stmp->surface.is_linear);
1170 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1171
1172 /* resolve */
1173 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1174
1175 /* blit */
1176 blit = *info;
1177 blit.src.resource = tmp;
1178 blit.src.box.z = 0;
1179
1180 si_blitter_begin(sctx, SI_BLIT |
1181 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1182 util_blitter_blit(sctx->blitter, &blit);
1183 si_blitter_end(sctx);
1184
1185 pipe_resource_reference(&tmp, NULL);
1186 return true;
1187 }
1188
1189 static void si_blit(struct pipe_context *ctx,
1190 const struct pipe_blit_info *info)
1191 {
1192 struct si_context *sctx = (struct si_context*)ctx;
1193 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1194
1195 if (do_hardware_msaa_resolve(ctx, info)) {
1196 return;
1197 }
1198
1199 /* Using SDMA for copying to a linear texture in GTT is much faster.
1200 * This improves DRI PRIME performance.
1201 *
1202 * resource_copy_region can't do this yet, because dma_copy calls it
1203 * on failure (recursion).
1204 */
1205 if (dst->surface.is_linear &&
1206 sctx->dma_copy &&
1207 util_can_blit_via_copy_region(info, false)) {
1208 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1209 info->dst.box.x, info->dst.box.y,
1210 info->dst.box.z,
1211 info->src.resource, info->src.level,
1212 &info->src.box);
1213 return;
1214 }
1215
1216 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1217
1218 /* The driver doesn't decompress resources automatically while
1219 * u_blitter is rendering. */
1220 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1221 info->src.level,
1222 info->src.format);
1223 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1224 info->dst.level,
1225 info->dst.format);
1226 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS,
1227 info->src.level,
1228 info->src.box.z,
1229 info->src.box.z + info->src.box.depth - 1);
1230
1231 if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
1232 util_try_blit_via_copy_region(ctx, info))
1233 return;
1234
1235 si_blitter_begin(sctx, SI_BLIT |
1236 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1237 util_blitter_blit(sctx->blitter, info);
1238 si_blitter_end(sctx);
1239 }
1240
1241 static bool si_generate_mipmap(struct pipe_context *ctx,
1242 struct pipe_resource *tex,
1243 enum pipe_format format,
1244 unsigned base_level, unsigned last_level,
1245 unsigned first_layer, unsigned last_layer)
1246 {
1247 struct si_context *sctx = (struct si_context*)ctx;
1248 struct si_texture *stex = (struct si_texture *)tex;
1249
1250 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1251 return false;
1252
1253 /* The driver doesn't decompress resources automatically while
1254 * u_blitter is rendering. */
1255 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1256 format);
1257 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1258 base_level, first_layer, last_layer);
1259
1260 /* Clear dirty_level_mask for the levels that will be overwritten. */
1261 assert(base_level < last_level);
1262 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1263 last_level - base_level);
1264
1265 sctx->generate_mipmap_for_depth = stex->is_depth;
1266
1267 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1268 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1269 base_level, last_level,
1270 first_layer, last_layer);
1271 si_blitter_end(sctx);
1272
1273 sctx->generate_mipmap_for_depth = false;
1274 return true;
1275 }
1276
1277 static void si_flush_resource(struct pipe_context *ctx,
1278 struct pipe_resource *res)
1279 {
1280 struct si_context *sctx = (struct si_context*)ctx;
1281 struct si_texture *tex = (struct si_texture*)res;
1282
1283 assert(res->target != PIPE_BUFFER);
1284 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1285
1286 /* st/dri calls flush twice per frame (not a bug), this prevents double
1287 * decompression. */
1288 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1289 return;
1290
1291 if (!tex->is_depth && (tex->cmask_buffer || tex->dcc_offset)) {
1292 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1293 0, util_max_layer(res, 0),
1294 tex->dcc_separate_buffer != NULL);
1295
1296 if (tex->display_dcc_offset)
1297 si_retile_dcc(sctx, tex);
1298 }
1299
1300 /* Always do the analysis even if DCC is disabled at the moment. */
1301 if (tex->dcc_gather_statistics) {
1302 bool separate_dcc_dirty = tex->separate_dcc_dirty;
1303
1304 /* If the color buffer hasn't been unbound and fast clear hasn't
1305 * been used, separate_dcc_dirty is false, but there may have been
1306 * new rendering. Check if the color buffer is bound and assume
1307 * it's dirty.
1308 *
1309 * Note that DRI2 never unbinds window colorbuffers, which means
1310 * the DCC pipeline statistics query would never be re-set and would
1311 * keep adding new results until all free memory is exhausted if we
1312 * didn't do this.
1313 */
1314 if (!separate_dcc_dirty) {
1315 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1316 if (sctx->framebuffer.state.cbufs[i] &&
1317 sctx->framebuffer.state.cbufs[i]->texture == res) {
1318 separate_dcc_dirty = true;
1319 break;
1320 }
1321 }
1322 }
1323
1324 if (separate_dcc_dirty) {
1325 tex->separate_dcc_dirty = false;
1326 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1327 }
1328 }
1329 }
1330
1331 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1332 {
1333 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1334 * be compressed either. The caller should simply discard it.
1335 */
1336 if (!tex->dcc_offset || !sctx->has_graphics)
1337 return;
1338
1339 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1340 0, util_max_layer(&tex->buffer.b.b, 0),
1341 true);
1342 }
1343
1344 void si_init_blit_functions(struct si_context *sctx)
1345 {
1346 sctx->b.resource_copy_region = si_resource_copy_region;
1347
1348 if (sctx->has_graphics) {
1349 sctx->b.blit = si_blit;
1350 sctx->b.flush_resource = si_flush_resource;
1351 sctx->b.generate_mipmap = si_generate_mipmap;
1352 }
1353 }