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radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival Evolved
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum si_blitter_op /* bitmask */
31 {
32 SI_SAVE_TEXTURES = 1,
33 SI_SAVE_FRAMEBUFFER = 2,
34 SI_SAVE_FRAGMENT_STATE = 4,
35 SI_DISABLE_RENDER_COND = 8,
36
37 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
38
39 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
40
41 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
42 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
43
44 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
45 SI_SAVE_FRAGMENT_STATE,
46
47 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
48 SI_DISABLE_RENDER_COND,
49
50 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
51 };
52
53 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
54 {
55 struct si_context *sctx = (struct si_context *)ctx;
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98 }
99
100 static unsigned u_max_sample(struct pipe_resource *r)
101 {
102 return r->nr_samples ? r->nr_samples - 1 : 0;
103 }
104
105 static unsigned
106 si_blit_dbcb_copy(struct si_context *sctx,
107 struct r600_texture *src,
108 struct r600_texture *dst,
109 unsigned planes, unsigned level_mask,
110 unsigned first_layer, unsigned last_layer,
111 unsigned first_sample, unsigned last_sample)
112 {
113 struct pipe_surface surf_tmpl = {{0}};
114 unsigned layer, sample, checked_last_layer, max_layer;
115 unsigned fully_copied_levels = 0;
116
117 if (planes & PIPE_MASK_Z)
118 sctx->dbcb_depth_copy_enabled = true;
119 if (planes & PIPE_MASK_S)
120 sctx->dbcb_stencil_copy_enabled = true;
121 si_mark_atom_dirty(sctx, &sctx->db_render_state);
122
123 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
124
125 sctx->decompression_enabled = true;
126
127 while (level_mask) {
128 unsigned level = u_bit_scan(&level_mask);
129
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer = util_max_layer(&src->resource.b.b, level);
133 checked_last_layer = MIN2(last_layer, max_layer);
134
135 surf_tmpl.u.tex.level = level;
136
137 for (layer = first_layer; layer <= checked_last_layer; layer++) {
138 struct pipe_surface *zsurf, *cbsurf;
139
140 surf_tmpl.format = src->resource.b.b.format;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = dst->resource.b.b.format;
147 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
148
149 for (sample = first_sample; sample <= last_sample; sample++) {
150 if (sample != sctx->dbcb_copy_sample) {
151 sctx->dbcb_copy_sample = sample;
152 si_mark_atom_dirty(sctx, &sctx->db_render_state);
153 }
154
155 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
156 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
157 sctx->custom_dsa_flush, 1.0f);
158 si_blitter_end(&sctx->b.b);
159 }
160
161 pipe_surface_reference(&zsurf, NULL);
162 pipe_surface_reference(&cbsurf, NULL);
163 }
164
165 if (first_layer == 0 && last_layer >= max_layer &&
166 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
167 fully_copied_levels |= 1u << level;
168 }
169
170 sctx->decompression_enabled = false;
171 sctx->dbcb_depth_copy_enabled = false;
172 sctx->dbcb_stencil_copy_enabled = false;
173 si_mark_atom_dirty(sctx, &sctx->db_render_state);
174
175 return fully_copied_levels;
176 }
177
178 static void si_blit_decompress_depth(struct pipe_context *ctx,
179 struct r600_texture *texture,
180 struct r600_texture *staging,
181 unsigned first_level, unsigned last_level,
182 unsigned first_layer, unsigned last_layer,
183 unsigned first_sample, unsigned last_sample)
184 {
185 const struct util_format_description *desc;
186 unsigned planes = 0;
187
188 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
189
190 desc = util_format_description(staging->resource.b.b.format);
191
192 if (util_format_has_depth(desc))
193 planes |= PIPE_MASK_Z;
194 if (util_format_has_stencil(desc))
195 planes |= PIPE_MASK_S;
196
197 si_blit_dbcb_copy(
198 (struct si_context *)ctx, texture, staging, planes,
199 u_bit_consecutive(first_level, last_level - first_level + 1),
200 first_layer, last_layer, first_sample, last_sample);
201 }
202
203 /* Helper function for si_blit_decompress_zs_in_place.
204 */
205 static void
206 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
207 struct r600_texture *texture,
208 unsigned planes, unsigned level_mask,
209 unsigned first_layer, unsigned last_layer)
210 {
211 struct pipe_surface *zsurf, surf_tmpl = {{0}};
212 unsigned layer, max_layer, checked_last_layer;
213 unsigned fully_decompressed_mask = 0;
214
215 if (!level_mask)
216 return;
217
218 if (planes & PIPE_MASK_S)
219 sctx->db_flush_stencil_inplace = true;
220 if (planes & PIPE_MASK_Z)
221 sctx->db_flush_depth_inplace = true;
222 si_mark_atom_dirty(sctx, &sctx->db_render_state);
223
224 surf_tmpl.format = texture->resource.b.b.format;
225
226 sctx->decompression_enabled = true;
227
228 while (level_mask) {
229 unsigned level = u_bit_scan(&level_mask);
230
231 surf_tmpl.u.tex.level = level;
232
233 /* The smaller the mipmap level, the less layers there are
234 * as far as 3D textures are concerned. */
235 max_layer = util_max_layer(&texture->resource.b.b, level);
236 checked_last_layer = MIN2(last_layer, max_layer);
237
238 for (layer = first_layer; layer <= checked_last_layer; layer++) {
239 surf_tmpl.u.tex.first_layer = layer;
240 surf_tmpl.u.tex.last_layer = layer;
241
242 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
243
244 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
245 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
246 sctx->custom_dsa_flush,
247 1.0f);
248 si_blitter_end(&sctx->b.b);
249
250 pipe_surface_reference(&zsurf, NULL);
251 }
252
253 /* The texture will always be dirty if some layers aren't flushed.
254 * I don't think this case occurs often though. */
255 if (first_layer == 0 && last_layer >= max_layer) {
256 fully_decompressed_mask |= 1u << level;
257 }
258 }
259
260 if (planes & PIPE_MASK_Z)
261 texture->dirty_level_mask &= ~fully_decompressed_mask;
262 if (planes & PIPE_MASK_S)
263 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
264
265 sctx->decompression_enabled = false;
266 sctx->db_flush_depth_inplace = false;
267 sctx->db_flush_stencil_inplace = false;
268 si_mark_atom_dirty(sctx, &sctx->db_render_state);
269 }
270
271 /* Helper function of si_flush_depth_texture: decompress the given levels
272 * of Z and/or S planes in place.
273 */
274 static void
275 si_blit_decompress_zs_in_place(struct si_context *sctx,
276 struct r600_texture *texture,
277 unsigned levels_z, unsigned levels_s,
278 unsigned first_layer, unsigned last_layer)
279 {
280 unsigned both = levels_z & levels_s;
281
282 /* First, do combined Z & S decompresses for levels that need it. */
283 if (both) {
284 si_blit_decompress_zs_planes_in_place(
285 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
286 both,
287 first_layer, last_layer);
288 levels_z &= ~both;
289 levels_s &= ~both;
290 }
291
292 /* Now do separate Z and S decompresses. */
293 if (levels_z) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_Z,
296 levels_z,
297 first_layer, last_layer);
298 }
299
300 if (levels_s) {
301 si_blit_decompress_zs_planes_in_place(
302 sctx, texture, PIPE_MASK_S,
303 levels_s,
304 first_layer, last_layer);
305 }
306 }
307
308 static void
309 si_decompress_depth(struct si_context *sctx,
310 struct r600_texture *tex,
311 unsigned required_planes,
312 unsigned first_level, unsigned last_level,
313 unsigned first_layer, unsigned last_layer)
314 {
315 unsigned inplace_planes = 0;
316 unsigned copy_planes = 0;
317 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
318 unsigned levels_z = 0;
319 unsigned levels_s = 0;
320
321 if (required_planes & PIPE_MASK_Z) {
322 levels_z = level_mask & tex->dirty_level_mask;
323
324 if (levels_z) {
325 if (r600_can_sample_zs(tex, false))
326 inplace_planes |= PIPE_MASK_Z;
327 else
328 copy_planes |= PIPE_MASK_Z;
329 }
330 }
331 if (required_planes & PIPE_MASK_S) {
332 levels_s = level_mask & tex->stencil_dirty_level_mask;
333
334 if (levels_s) {
335 if (r600_can_sample_zs(tex, true))
336 inplace_planes |= PIPE_MASK_S;
337 else
338 copy_planes |= PIPE_MASK_S;
339 }
340 }
341
342 if (unlikely(sctx->b.log))
343 u_log_printf(sctx->b.log,
344 "\n------------------------------------------------\n"
345 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
346 first_level, last_level, levels_z, levels_s);
347
348 /* We may have to allocate the flushed texture here when called from
349 * si_decompress_subresource.
350 */
351 if (copy_planes &&
352 (tex->flushed_depth_texture ||
353 si_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
354 struct r600_texture *dst = tex->flushed_depth_texture;
355 unsigned fully_copied_levels;
356 unsigned levels = 0;
357
358 assert(tex->flushed_depth_texture);
359
360 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
361 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
362
363 if (copy_planes & PIPE_MASK_Z) {
364 levels |= levels_z;
365 levels_z = 0;
366 }
367 if (copy_planes & PIPE_MASK_S) {
368 levels |= levels_s;
369 levels_s = 0;
370 }
371
372 fully_copied_levels = si_blit_dbcb_copy(
373 sctx, tex, dst, copy_planes, levels,
374 first_layer, last_layer,
375 0, u_max_sample(&tex->resource.b.b));
376
377 if (copy_planes & PIPE_MASK_Z)
378 tex->dirty_level_mask &= ~fully_copied_levels;
379 if (copy_planes & PIPE_MASK_S)
380 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
381 }
382
383 if (inplace_planes) {
384 bool has_htile = r600_htile_enabled(tex, first_level);
385 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
386
387 /* Don't decompress if there is no HTILE or when HTILE is
388 * TC-compatible. */
389 if (has_htile && !tc_compat_htile) {
390 si_blit_decompress_zs_in_place(
391 sctx, tex,
392 levels_z, levels_s,
393 first_layer, last_layer);
394 } else {
395 /* This is only a cache flush.
396 *
397 * Only clear the mask that we are flushing, because
398 * si_make_DB_shader_coherent() treats different levels
399 * and depth and stencil differently.
400 */
401 if (inplace_planes & PIPE_MASK_Z)
402 tex->dirty_level_mask &= ~levels_z;
403 if (inplace_planes & PIPE_MASK_S)
404 tex->stencil_dirty_level_mask &= ~levels_s;
405 }
406
407 /* Only in-place decompression needs to flush DB caches, or
408 * when we don't decompress but TC-compatible planes are dirty.
409 */
410 si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
411 inplace_planes & PIPE_MASK_S,
412 tc_compat_htile);
413 }
414 /* set_framebuffer_state takes care of coherency for single-sample.
415 * The DB->CB copy uses CB for the final writes.
416 */
417 if (copy_planes && tex->resource.b.b.nr_samples > 1)
418 si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
419 false);
420 }
421
422 static void
423 si_decompress_sampler_depth_textures(struct si_context *sctx,
424 struct si_samplers *textures)
425 {
426 unsigned i;
427 unsigned mask = textures->needs_depth_decompress_mask;
428
429 while (mask) {
430 struct pipe_sampler_view *view;
431 struct si_sampler_view *sview;
432 struct r600_texture *tex;
433
434 i = u_bit_scan(&mask);
435
436 view = textures->views[i];
437 assert(view);
438 sview = (struct si_sampler_view*)view;
439
440 tex = (struct r600_texture *)view->texture;
441 assert(tex->db_compatible);
442
443 si_decompress_depth(sctx, tex,
444 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
445 view->u.tex.first_level, view->u.tex.last_level,
446 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
447 }
448 }
449
450 static void si_blit_decompress_color(struct pipe_context *ctx,
451 struct r600_texture *rtex,
452 unsigned first_level, unsigned last_level,
453 unsigned first_layer, unsigned last_layer,
454 bool need_dcc_decompress)
455 {
456 struct si_context *sctx = (struct si_context *)ctx;
457 void* custom_blend;
458 unsigned layer, checked_last_layer, max_layer;
459 unsigned level_mask =
460 u_bit_consecutive(first_level, last_level - first_level + 1);
461
462 if (!need_dcc_decompress)
463 level_mask &= rtex->dirty_level_mask;
464 if (!level_mask)
465 return;
466
467 if (unlikely(sctx->b.log))
468 u_log_printf(sctx->b.log,
469 "\n------------------------------------------------\n"
470 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
471 first_level, last_level, level_mask);
472
473 if (need_dcc_decompress) {
474 custom_blend = sctx->custom_blend_dcc_decompress;
475
476 assert(rtex->dcc_offset);
477
478 /* disable levels without DCC */
479 for (int i = first_level; i <= last_level; i++) {
480 if (!vi_dcc_enabled(rtex, i))
481 level_mask &= ~(1 << i);
482 }
483 } else if (rtex->fmask.size) {
484 custom_blend = sctx->custom_blend_fmask_decompress;
485 } else {
486 custom_blend = sctx->custom_blend_eliminate_fastclear;
487 }
488
489 sctx->decompression_enabled = true;
490
491 while (level_mask) {
492 unsigned level = u_bit_scan(&level_mask);
493
494 /* The smaller the mipmap level, the less layers there are
495 * as far as 3D textures are concerned. */
496 max_layer = util_max_layer(&rtex->resource.b.b, level);
497 checked_last_layer = MIN2(last_layer, max_layer);
498
499 for (layer = first_layer; layer <= checked_last_layer; layer++) {
500 struct pipe_surface *cbsurf, surf_tmpl;
501
502 surf_tmpl.format = rtex->resource.b.b.format;
503 surf_tmpl.u.tex.level = level;
504 surf_tmpl.u.tex.first_layer = layer;
505 surf_tmpl.u.tex.last_layer = layer;
506 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
507
508 /* Required before and after FMASK and DCC_DECOMPRESS. */
509 if (custom_blend == sctx->custom_blend_fmask_decompress ||
510 custom_blend == sctx->custom_blend_dcc_decompress)
511 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
512
513 si_blitter_begin(ctx, SI_DECOMPRESS);
514 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
515 si_blitter_end(ctx);
516
517 if (custom_blend == sctx->custom_blend_fmask_decompress ||
518 custom_blend == sctx->custom_blend_dcc_decompress)
519 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
520
521 pipe_surface_reference(&cbsurf, NULL);
522 }
523
524 /* The texture will always be dirty if some layers aren't flushed.
525 * I don't think this case occurs often though. */
526 if (first_layer == 0 && last_layer >= max_layer) {
527 rtex->dirty_level_mask &= ~(1 << level);
528 }
529 }
530
531 sctx->decompression_enabled = false;
532 si_make_CB_shader_coherent(sctx, rtex->resource.b.b.nr_samples,
533 vi_dcc_enabled(rtex, first_level));
534 }
535
536 static void
537 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
538 unsigned first_level, unsigned last_level)
539 {
540 /* CMASK or DCC can be discarded and we can still end up here. */
541 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
542 return;
543
544 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
545 util_max_layer(&tex->resource.b.b, first_level),
546 false);
547 }
548
549 static void
550 si_decompress_sampler_color_textures(struct si_context *sctx,
551 struct si_samplers *textures)
552 {
553 unsigned i;
554 unsigned mask = textures->needs_color_decompress_mask;
555
556 while (mask) {
557 struct pipe_sampler_view *view;
558 struct r600_texture *tex;
559
560 i = u_bit_scan(&mask);
561
562 view = textures->views[i];
563 assert(view);
564
565 tex = (struct r600_texture *)view->texture;
566
567 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
568 view->u.tex.last_level);
569 }
570 }
571
572 static void
573 si_decompress_image_color_textures(struct si_context *sctx,
574 struct si_images *images)
575 {
576 unsigned i;
577 unsigned mask = images->needs_color_decompress_mask;
578
579 while (mask) {
580 const struct pipe_image_view *view;
581 struct r600_texture *tex;
582
583 i = u_bit_scan(&mask);
584
585 view = &images->views[i];
586 assert(view->resource->target != PIPE_BUFFER);
587
588 tex = (struct r600_texture *)view->resource;
589
590 si_decompress_color_texture(sctx, tex, view->u.tex.level,
591 view->u.tex.level);
592 }
593 }
594
595 static void si_check_render_feedback_texture(struct si_context *sctx,
596 struct r600_texture *tex,
597 unsigned first_level,
598 unsigned last_level,
599 unsigned first_layer,
600 unsigned last_layer)
601 {
602 bool render_feedback = false;
603
604 if (!tex->dcc_offset)
605 return;
606
607 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
608 struct r600_surface * surf;
609
610 if (!sctx->framebuffer.state.cbufs[j])
611 continue;
612
613 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
614
615 if (tex == (struct r600_texture *)surf->base.texture &&
616 surf->base.u.tex.level >= first_level &&
617 surf->base.u.tex.level <= last_level &&
618 surf->base.u.tex.first_layer <= last_layer &&
619 surf->base.u.tex.last_layer >= first_layer) {
620 render_feedback = true;
621 break;
622 }
623 }
624
625 if (render_feedback)
626 si_texture_disable_dcc(&sctx->b, tex);
627 }
628
629 static void si_check_render_feedback_textures(struct si_context *sctx,
630 struct si_samplers *textures)
631 {
632 uint32_t mask = textures->enabled_mask;
633
634 while (mask) {
635 const struct pipe_sampler_view *view;
636 struct r600_texture *tex;
637
638 unsigned i = u_bit_scan(&mask);
639
640 view = textures->views[i];
641 if(view->texture->target == PIPE_BUFFER)
642 continue;
643
644 tex = (struct r600_texture *)view->texture;
645
646 si_check_render_feedback_texture(sctx, tex,
647 view->u.tex.first_level,
648 view->u.tex.last_level,
649 view->u.tex.first_layer,
650 view->u.tex.last_layer);
651 }
652 }
653
654 static void si_check_render_feedback_images(struct si_context *sctx,
655 struct si_images *images)
656 {
657 uint32_t mask = images->enabled_mask;
658
659 while (mask) {
660 const struct pipe_image_view *view;
661 struct r600_texture *tex;
662
663 unsigned i = u_bit_scan(&mask);
664
665 view = &images->views[i];
666 if (view->resource->target == PIPE_BUFFER)
667 continue;
668
669 tex = (struct r600_texture *)view->resource;
670
671 si_check_render_feedback_texture(sctx, tex,
672 view->u.tex.level,
673 view->u.tex.level,
674 view->u.tex.first_layer,
675 view->u.tex.last_layer);
676 }
677 }
678
679 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
680 {
681 util_dynarray_foreach(&sctx->resident_tex_handles,
682 struct si_texture_handle *, tex_handle) {
683 struct pipe_sampler_view *view;
684 struct r600_texture *tex;
685
686 view = (*tex_handle)->view;
687 if (view->texture->target == PIPE_BUFFER)
688 continue;
689
690 tex = (struct r600_texture *)view->texture;
691
692 si_check_render_feedback_texture(sctx, tex,
693 view->u.tex.first_level,
694 view->u.tex.last_level,
695 view->u.tex.first_layer,
696 view->u.tex.last_layer);
697 }
698 }
699
700 static void si_check_render_feedback_resident_images(struct si_context *sctx)
701 {
702 util_dynarray_foreach(&sctx->resident_img_handles,
703 struct si_image_handle *, img_handle) {
704 struct pipe_image_view *view;
705 struct r600_texture *tex;
706
707 view = &(*img_handle)->view;
708 if (view->resource->target == PIPE_BUFFER)
709 continue;
710
711 tex = (struct r600_texture *)view->resource;
712
713 si_check_render_feedback_texture(sctx, tex,
714 view->u.tex.level,
715 view->u.tex.level,
716 view->u.tex.first_layer,
717 view->u.tex.last_layer);
718 }
719 }
720
721 static void si_check_render_feedback(struct si_context *sctx)
722 {
723
724 if (!sctx->need_check_render_feedback)
725 return;
726
727 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
728 si_check_render_feedback_images(sctx, &sctx->images[i]);
729 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
730 }
731
732 si_check_render_feedback_resident_images(sctx);
733 si_check_render_feedback_resident_textures(sctx);
734
735 sctx->need_check_render_feedback = false;
736 }
737
738 static void si_decompress_resident_textures(struct si_context *sctx)
739 {
740 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
741 struct si_texture_handle *, tex_handle) {
742 struct pipe_sampler_view *view = (*tex_handle)->view;
743 struct r600_texture *tex = (struct r600_texture *)view->texture;
744
745 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
746 view->u.tex.last_level);
747 }
748
749 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
750 struct si_texture_handle *, tex_handle) {
751 struct pipe_sampler_view *view = (*tex_handle)->view;
752 struct si_sampler_view *sview = (struct si_sampler_view *)view;
753 struct r600_texture *tex = (struct r600_texture *)view->texture;
754
755 si_decompress_depth(sctx, tex,
756 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
757 view->u.tex.first_level, view->u.tex.last_level,
758 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
759 }
760 }
761
762 static void si_decompress_resident_images(struct si_context *sctx)
763 {
764 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
765 struct si_image_handle *, img_handle) {
766 struct pipe_image_view *view = &(*img_handle)->view;
767 struct r600_texture *tex = (struct r600_texture *)view->resource;
768
769 si_decompress_color_texture(sctx, tex, view->u.tex.level,
770 view->u.tex.level);
771 }
772 }
773
774 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
775 {
776 unsigned compressed_colortex_counter, mask;
777
778 if (sctx->blitter->running)
779 return;
780
781 /* Update the compressed_colortex_mask if necessary. */
782 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
783 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
784 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
785 si_update_needs_color_decompress_masks(sctx);
786 }
787
788 /* Decompress color & depth textures if needed. */
789 mask = sctx->shader_needs_decompress_mask & shader_mask;
790 while (mask) {
791 unsigned i = u_bit_scan(&mask);
792
793 if (sctx->samplers[i].needs_depth_decompress_mask) {
794 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
795 }
796 if (sctx->samplers[i].needs_color_decompress_mask) {
797 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
798 }
799 if (sctx->images[i].needs_color_decompress_mask) {
800 si_decompress_image_color_textures(sctx, &sctx->images[i]);
801 }
802 }
803
804 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
805 if (sctx->uses_bindless_samplers)
806 si_decompress_resident_textures(sctx);
807 if (sctx->uses_bindless_images)
808 si_decompress_resident_images(sctx);
809 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
810 if (sctx->cs_shader_state.program->uses_bindless_samplers)
811 si_decompress_resident_textures(sctx);
812 if (sctx->cs_shader_state.program->uses_bindless_images)
813 si_decompress_resident_images(sctx);
814 }
815
816 si_check_render_feedback(sctx);
817 }
818
819 void si_decompress_graphics_textures(struct si_context *sctx)
820 {
821 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
822 }
823
824 void si_decompress_compute_textures(struct si_context *sctx)
825 {
826 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
827 }
828
829 static void si_clear(struct pipe_context *ctx, unsigned buffers,
830 const union pipe_color_union *color,
831 double depth, unsigned stencil)
832 {
833 struct si_context *sctx = (struct si_context *)ctx;
834 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
835 struct pipe_surface *zsbuf = fb->zsbuf;
836 struct r600_texture *zstex =
837 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
838
839 if (buffers & PIPE_CLEAR_COLOR) {
840 si_do_fast_color_clear(&sctx->b, fb,
841 &sctx->framebuffer.atom, &buffers,
842 &sctx->framebuffer.dirty_cbufs,
843 color);
844 if (!buffers)
845 return; /* all buffers have been fast cleared */
846 }
847
848 if (buffers & PIPE_CLEAR_COLOR) {
849 int i;
850
851 /* These buffers cannot use fast clear, make sure to disable expansion. */
852 for (i = 0; i < fb->nr_cbufs; i++) {
853 struct r600_texture *tex;
854
855 /* If not clearing this buffer, skip. */
856 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
857 continue;
858
859 if (!fb->cbufs[i])
860 continue;
861
862 tex = (struct r600_texture *)fb->cbufs[i]->texture;
863 if (tex->fmask.size == 0)
864 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
865 }
866 }
867
868 if (zstex &&
869 r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
870 zsbuf->u.tex.first_layer == 0 &&
871 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
872 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
873 if (buffers & PIPE_CLEAR_DEPTH &&
874 (!zstex->tc_compatible_htile ||
875 depth == 0 || depth == 1)) {
876 /* Need to disable EXPCLEAR temporarily if clearing
877 * to a new value. */
878 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
879 sctx->db_depth_disable_expclear = true;
880 }
881
882 zstex->depth_clear_value = depth;
883 sctx->framebuffer.dirty_zsbuf = true;
884 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
885 sctx->db_depth_clear = true;
886 si_mark_atom_dirty(sctx, &sctx->db_render_state);
887 }
888
889 /* TC-compatible HTILE only supports stencil clears to 0. */
890 if (buffers & PIPE_CLEAR_STENCIL &&
891 (!zstex->tc_compatible_htile || stencil == 0)) {
892 stencil &= 0xff;
893
894 /* Need to disable EXPCLEAR temporarily if clearing
895 * to a new value. */
896 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
897 sctx->db_stencil_disable_expclear = true;
898 }
899
900 zstex->stencil_clear_value = stencil;
901 sctx->framebuffer.dirty_zsbuf = true;
902 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
903 sctx->db_stencil_clear = true;
904 si_mark_atom_dirty(sctx, &sctx->db_render_state);
905 }
906
907 /* TODO: Find out what's wrong here. Fast depth clear leads to
908 * corruption in ARK: Survival Evolved, but that may just be
909 * a coincidence and the root cause is elsewhere.
910 *
911 * The corruption can be fixed by putting the DB metadata flush
912 * before or after the depth clear. (suprisingly)
913 *
914 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
915 *
916 * This hack decreases back-to-back ClearDepth performance.
917 */
918 if (sctx->screen->clear_db_meta_before_clear)
919 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META |
920 SI_CONTEXT_PS_PARTIAL_FLUSH;
921 }
922
923 si_blitter_begin(ctx, SI_CLEAR);
924 util_blitter_clear(sctx->blitter, fb->width, fb->height,
925 util_framebuffer_get_num_layers(fb),
926 buffers, color, depth, stencil);
927 si_blitter_end(ctx);
928
929 if (sctx->db_depth_clear) {
930 sctx->db_depth_clear = false;
931 sctx->db_depth_disable_expclear = false;
932 zstex->depth_cleared = true;
933 si_mark_atom_dirty(sctx, &sctx->db_render_state);
934 }
935
936 if (sctx->db_stencil_clear) {
937 sctx->db_stencil_clear = false;
938 sctx->db_stencil_disable_expclear = false;
939 zstex->stencil_cleared = true;
940 si_mark_atom_dirty(sctx, &sctx->db_render_state);
941 }
942 }
943
944 static void si_clear_render_target(struct pipe_context *ctx,
945 struct pipe_surface *dst,
946 const union pipe_color_union *color,
947 unsigned dstx, unsigned dsty,
948 unsigned width, unsigned height,
949 bool render_condition_enabled)
950 {
951 struct si_context *sctx = (struct si_context *)ctx;
952
953 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
954 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
955 util_blitter_clear_render_target(sctx->blitter, dst, color,
956 dstx, dsty, width, height);
957 si_blitter_end(ctx);
958 }
959
960 static void si_clear_depth_stencil(struct pipe_context *ctx,
961 struct pipe_surface *dst,
962 unsigned clear_flags,
963 double depth,
964 unsigned stencil,
965 unsigned dstx, unsigned dsty,
966 unsigned width, unsigned height,
967 bool render_condition_enabled)
968 {
969 struct si_context *sctx = (struct si_context *)ctx;
970
971 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
972 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
973 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
974 dstx, dsty, width, height);
975 si_blitter_end(ctx);
976 }
977
978 /* Helper for decompressing a portion of a color or depth resource before
979 * blitting if any decompression is needed.
980 * The driver doesn't decompress resources automatically while u_blitter is
981 * rendering. */
982 static void si_decompress_subresource(struct pipe_context *ctx,
983 struct pipe_resource *tex,
984 unsigned planes, unsigned level,
985 unsigned first_layer, unsigned last_layer)
986 {
987 struct si_context *sctx = (struct si_context *)ctx;
988 struct r600_texture *rtex = (struct r600_texture*)tex;
989
990 if (rtex->db_compatible) {
991 planes &= PIPE_MASK_Z | PIPE_MASK_S;
992
993 if (!rtex->surface.has_stencil)
994 planes &= ~PIPE_MASK_S;
995
996 /* If we've rendered into the framebuffer and it's a blitting
997 * source, make sure the decompression pass is invoked
998 * by dirtying the framebuffer.
999 */
1000 if (sctx->framebuffer.state.zsbuf &&
1001 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
1002 sctx->framebuffer.state.zsbuf->texture == tex)
1003 si_update_fb_dirtiness_after_rendering(sctx);
1004
1005 si_decompress_depth(sctx, rtex, planes,
1006 level, level,
1007 first_layer, last_layer);
1008 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
1009 /* If we've rendered into the framebuffer and it's a blitting
1010 * source, make sure the decompression pass is invoked
1011 * by dirtying the framebuffer.
1012 */
1013 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1014 if (sctx->framebuffer.state.cbufs[i] &&
1015 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
1016 sctx->framebuffer.state.cbufs[i]->texture == tex) {
1017 si_update_fb_dirtiness_after_rendering(sctx);
1018 break;
1019 }
1020 }
1021
1022 si_blit_decompress_color(ctx, rtex, level, level,
1023 first_layer, last_layer, false);
1024 }
1025 }
1026
1027 struct texture_orig_info {
1028 unsigned format;
1029 unsigned width0;
1030 unsigned height0;
1031 unsigned npix_x;
1032 unsigned npix_y;
1033 unsigned npix0_x;
1034 unsigned npix0_y;
1035 };
1036
1037 void si_resource_copy_region(struct pipe_context *ctx,
1038 struct pipe_resource *dst,
1039 unsigned dst_level,
1040 unsigned dstx, unsigned dsty, unsigned dstz,
1041 struct pipe_resource *src,
1042 unsigned src_level,
1043 const struct pipe_box *src_box)
1044 {
1045 struct si_context *sctx = (struct si_context *)ctx;
1046 struct r600_texture *rsrc = (struct r600_texture*)src;
1047 struct pipe_surface *dst_view, dst_templ;
1048 struct pipe_sampler_view src_templ, *src_view;
1049 unsigned dst_width, dst_height, src_width0, src_height0;
1050 unsigned dst_width0, dst_height0, src_force_level = 0;
1051 struct pipe_box sbox, dstbox;
1052
1053 /* Handle buffers first. */
1054 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1055 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1056 return;
1057 }
1058
1059 assert(u_max_sample(dst) == u_max_sample(src));
1060
1061 /* The driver doesn't decompress resources automatically while
1062 * u_blitter is rendering. */
1063 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1064 src_box->z, src_box->z + src_box->depth - 1);
1065
1066 dst_width = u_minify(dst->width0, dst_level);
1067 dst_height = u_minify(dst->height0, dst_level);
1068 dst_width0 = dst->width0;
1069 dst_height0 = dst->height0;
1070 src_width0 = src->width0;
1071 src_height0 = src->height0;
1072
1073 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1074 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1075
1076 if (util_format_is_compressed(src->format) ||
1077 util_format_is_compressed(dst->format)) {
1078 unsigned blocksize = rsrc->surface.bpe;
1079
1080 if (blocksize == 8)
1081 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1082 else
1083 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1084 dst_templ.format = src_templ.format;
1085
1086 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1087 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1088 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1089 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1090 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1091 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1092
1093 dstx = util_format_get_nblocksx(dst->format, dstx);
1094 dsty = util_format_get_nblocksy(dst->format, dsty);
1095
1096 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1097 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1098 sbox.z = src_box->z;
1099 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1100 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1101 sbox.depth = src_box->depth;
1102 src_box = &sbox;
1103
1104 src_force_level = src_level;
1105 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1106 if (util_format_is_subsampled_422(src->format)) {
1107 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1108 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1109
1110 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1111 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1112 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1113
1114 dstx = util_format_get_nblocksx(dst->format, dstx);
1115
1116 sbox = *src_box;
1117 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1118 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1119 src_box = &sbox;
1120 } else {
1121 unsigned blocksize = rsrc->surface.bpe;
1122
1123 switch (blocksize) {
1124 case 1:
1125 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1126 src_templ.format = PIPE_FORMAT_R8_UNORM;
1127 break;
1128 case 2:
1129 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1130 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1131 break;
1132 case 4:
1133 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1134 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1135 break;
1136 case 8:
1137 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1138 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1139 break;
1140 case 16:
1141 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1142 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1143 break;
1144 default:
1145 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1146 util_format_short_name(src->format), blocksize);
1147 assert(0);
1148 }
1149 }
1150 }
1151
1152 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1153 * equivalent instead, which doesn't force DCC decompression.
1154 * Note that some chips avoid this issue by using SDMA.
1155 */
1156 if (util_format_is_snorm8(dst_templ.format)) {
1157 switch (dst_templ.format) {
1158 case PIPE_FORMAT_R8_SNORM:
1159 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1160 break;
1161 case PIPE_FORMAT_R8G8_SNORM:
1162 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1163 break;
1164 case PIPE_FORMAT_R8G8B8X8_SNORM:
1165 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1166 break;
1167 case PIPE_FORMAT_R8G8B8A8_SNORM:
1168 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1169 case PIPE_FORMAT_A8B8G8R8_SNORM:
1170 case PIPE_FORMAT_X8B8G8R8_SNORM:
1171 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1172 break;
1173 case PIPE_FORMAT_A8_SNORM:
1174 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1175 break;
1176 case PIPE_FORMAT_L8_SNORM:
1177 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1178 break;
1179 case PIPE_FORMAT_L8A8_SNORM:
1180 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1181 break;
1182 case PIPE_FORMAT_I8_SNORM:
1183 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1184 break;
1185 default:; /* fall through */
1186 }
1187 }
1188
1189 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1190 dst_templ.format);
1191 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1192 src_templ.format);
1193
1194 /* Initialize the surface. */
1195 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1196 dst_width0, dst_height0,
1197 dst_width, dst_height);
1198
1199 /* Initialize the sampler view. */
1200 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1201 src_width0, src_height0,
1202 src_force_level);
1203
1204 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1205 abs(src_box->depth), &dstbox);
1206
1207 /* Copy. */
1208 si_blitter_begin(ctx, SI_COPY);
1209 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1210 src_view, src_box, src_width0, src_height0,
1211 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1212 false);
1213 si_blitter_end(ctx);
1214
1215 pipe_surface_reference(&dst_view, NULL);
1216 pipe_sampler_view_reference(&src_view, NULL);
1217 }
1218
1219 static void si_do_CB_resolve(struct si_context *sctx,
1220 const struct pipe_blit_info *info,
1221 struct pipe_resource *dst,
1222 unsigned dst_level, unsigned dst_z,
1223 enum pipe_format format)
1224 {
1225 /* Required before and after CB_RESOLVE. */
1226 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1227
1228 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1229 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1230 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1231 info->src.resource, info->src.box.z,
1232 ~0, sctx->custom_blend_resolve,
1233 format);
1234 si_blitter_end(&sctx->b.b);
1235
1236 /* Flush caches for possible texturing. */
1237 si_make_CB_shader_coherent(sctx, 1, false);
1238 }
1239
1240 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1241 const struct pipe_blit_info *info)
1242 {
1243 struct si_context *sctx = (struct si_context*)ctx;
1244 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1245 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1246 MAYBE_UNUSED struct r600_texture *rtmp;
1247 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1248 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1249 enum pipe_format format = info->src.format;
1250 struct pipe_resource *tmp, templ;
1251 struct pipe_blit_info blit;
1252
1253 /* Check basic requirements for hw resolve. */
1254 if (!(info->src.resource->nr_samples > 1 &&
1255 info->dst.resource->nr_samples <= 1 &&
1256 !util_format_is_pure_integer(format) &&
1257 !util_format_is_depth_or_stencil(format) &&
1258 util_max_layer(info->src.resource, 0) == 0))
1259 return false;
1260
1261 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1262 * the format is R16G16. Use R16A16, which does work.
1263 */
1264 if (format == PIPE_FORMAT_R16G16_UNORM)
1265 format = PIPE_FORMAT_R16A16_UNORM;
1266 if (format == PIPE_FORMAT_R16G16_SNORM)
1267 format = PIPE_FORMAT_R16A16_SNORM;
1268
1269 /* Check the remaining requirements for hw resolve. */
1270 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1271 !info->scissor_enable &&
1272 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1273 util_is_format_compatible(util_format_description(info->src.format),
1274 util_format_description(info->dst.format)) &&
1275 dst_width == info->src.resource->width0 &&
1276 dst_height == info->src.resource->height0 &&
1277 info->dst.box.x == 0 &&
1278 info->dst.box.y == 0 &&
1279 info->dst.box.width == dst_width &&
1280 info->dst.box.height == dst_height &&
1281 info->dst.box.depth == 1 &&
1282 info->src.box.x == 0 &&
1283 info->src.box.y == 0 &&
1284 info->src.box.width == dst_width &&
1285 info->src.box.height == dst_height &&
1286 info->src.box.depth == 1 &&
1287 !dst->surface.is_linear &&
1288 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1289 /* Check the last constraint. */
1290 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1291 /* The next fast clear will switch to this mode to
1292 * get direct hw resolve next time if the mode is
1293 * different now.
1294 */
1295 src->last_msaa_resolve_target_micro_mode =
1296 dst->surface.micro_tile_mode;
1297 goto resolve_to_temp;
1298 }
1299
1300 /* Resolving into a surface with DCC is unsupported. Since
1301 * it's being overwritten anyway, clear it to uncompressed.
1302 * This is still the fastest codepath even with this clear.
1303 */
1304 if (vi_dcc_enabled(dst, info->dst.level)) {
1305 /* TODO: Implement per-level DCC clears for GFX9. */
1306 if (sctx->b.chip_class >= GFX9 &&
1307 info->dst.resource->last_level != 0)
1308 goto resolve_to_temp;
1309
1310 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1311 0xFFFFFFFF);
1312 dst->dirty_level_mask &= ~(1 << info->dst.level);
1313 }
1314
1315 /* Resolve directly from src to dst. */
1316 si_do_CB_resolve(sctx, info, info->dst.resource,
1317 info->dst.level, info->dst.box.z, format);
1318 return true;
1319 }
1320
1321 resolve_to_temp:
1322 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1323 * a temporary texture and blit.
1324 */
1325 memset(&templ, 0, sizeof(templ));
1326 templ.target = PIPE_TEXTURE_2D;
1327 templ.format = info->src.resource->format;
1328 templ.width0 = info->src.resource->width0;
1329 templ.height0 = info->src.resource->height0;
1330 templ.depth0 = 1;
1331 templ.array_size = 1;
1332 templ.usage = PIPE_USAGE_DEFAULT;
1333 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1334 R600_RESOURCE_FLAG_DISABLE_DCC;
1335
1336 /* The src and dst microtile modes must be the same. */
1337 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1338 templ.bind = PIPE_BIND_SCANOUT;
1339 else
1340 templ.bind = 0;
1341
1342 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1343 if (!tmp)
1344 return false;
1345 rtmp = (struct r600_texture*)tmp;
1346
1347 assert(!rtmp->surface.is_linear);
1348 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1349
1350 /* resolve */
1351 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1352
1353 /* blit */
1354 blit = *info;
1355 blit.src.resource = tmp;
1356 blit.src.box.z = 0;
1357
1358 si_blitter_begin(ctx, SI_BLIT |
1359 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1360 util_blitter_blit(sctx->blitter, &blit);
1361 si_blitter_end(ctx);
1362
1363 pipe_resource_reference(&tmp, NULL);
1364 return true;
1365 }
1366
1367 static void si_blit(struct pipe_context *ctx,
1368 const struct pipe_blit_info *info)
1369 {
1370 struct si_context *sctx = (struct si_context*)ctx;
1371 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1372
1373 if (do_hardware_msaa_resolve(ctx, info)) {
1374 return;
1375 }
1376
1377 /* Using SDMA for copying to a linear texture in GTT is much faster.
1378 * This improves DRI PRIME performance.
1379 *
1380 * resource_copy_region can't do this yet, because dma_copy calls it
1381 * on failure (recursion).
1382 */
1383 if (rdst->surface.is_linear &&
1384 sctx->b.dma_copy &&
1385 util_can_blit_via_copy_region(info, false)) {
1386 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1387 info->dst.box.x, info->dst.box.y,
1388 info->dst.box.z,
1389 info->src.resource, info->src.level,
1390 &info->src.box);
1391 return;
1392 }
1393
1394 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1395
1396 /* The driver doesn't decompress resources automatically while
1397 * u_blitter is rendering. */
1398 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1399 info->src.level,
1400 info->src.format);
1401 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1402 info->dst.level,
1403 info->dst.format);
1404 si_decompress_subresource(ctx, info->src.resource, info->mask,
1405 info->src.level,
1406 info->src.box.z,
1407 info->src.box.z + info->src.box.depth - 1);
1408
1409 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1410 util_try_blit_via_copy_region(ctx, info))
1411 return;
1412
1413 si_blitter_begin(ctx, SI_BLIT |
1414 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1415 util_blitter_blit(sctx->blitter, info);
1416 si_blitter_end(ctx);
1417 }
1418
1419 static boolean si_generate_mipmap(struct pipe_context *ctx,
1420 struct pipe_resource *tex,
1421 enum pipe_format format,
1422 unsigned base_level, unsigned last_level,
1423 unsigned first_layer, unsigned last_layer)
1424 {
1425 struct si_context *sctx = (struct si_context*)ctx;
1426 struct r600_texture *rtex = (struct r600_texture *)tex;
1427
1428 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1429 return false;
1430
1431 /* The driver doesn't decompress resources automatically while
1432 * u_blitter is rendering. */
1433 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1434 format);
1435 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1436 base_level, first_layer, last_layer);
1437
1438 /* Clear dirty_level_mask for the levels that will be overwritten. */
1439 assert(base_level < last_level);
1440 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1441 last_level - base_level);
1442
1443 sctx->generate_mipmap_for_depth = rtex->is_depth;
1444
1445 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1446 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1447 base_level, last_level,
1448 first_layer, last_layer);
1449 si_blitter_end(ctx);
1450
1451 sctx->generate_mipmap_for_depth = false;
1452 return true;
1453 }
1454
1455 static void si_flush_resource(struct pipe_context *ctx,
1456 struct pipe_resource *res)
1457 {
1458 struct r600_texture *rtex = (struct r600_texture*)res;
1459
1460 assert(res->target != PIPE_BUFFER);
1461 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1462
1463 /* st/dri calls flush twice per frame (not a bug), this prevents double
1464 * decompression. */
1465 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1466 return;
1467
1468 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1469 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1470 0, util_max_layer(res, 0),
1471 rtex->dcc_separate_buffer != NULL);
1472 }
1473
1474 /* Always do the analysis even if DCC is disabled at the moment. */
1475 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1476 rtex->separate_dcc_dirty = false;
1477 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1478 }
1479 }
1480
1481 static void si_decompress_dcc(struct pipe_context *ctx,
1482 struct r600_texture *rtex)
1483 {
1484 if (!rtex->dcc_offset)
1485 return;
1486
1487 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1488 0, util_max_layer(&rtex->resource.b.b, 0),
1489 true);
1490 }
1491
1492 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1493 struct pipe_resource *dst,
1494 unsigned offset, unsigned size,
1495 const void *clear_value_ptr,
1496 int clear_value_size)
1497 {
1498 struct si_context *sctx = (struct si_context*)ctx;
1499 uint32_t dword_value;
1500 unsigned i;
1501
1502 assert(offset % clear_value_size == 0);
1503 assert(size % clear_value_size == 0);
1504
1505 if (clear_value_size > 4) {
1506 const uint32_t *u32 = clear_value_ptr;
1507 bool clear_dword_duplicated = true;
1508
1509 /* See if we can lower large fills to dword fills. */
1510 for (i = 1; i < clear_value_size / 4; i++)
1511 if (u32[0] != u32[i]) {
1512 clear_dword_duplicated = false;
1513 break;
1514 }
1515
1516 if (!clear_dword_duplicated) {
1517 /* Use transform feedback for 64-bit, 96-bit, and
1518 * 128-bit fills.
1519 */
1520 union pipe_color_union clear_value;
1521
1522 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1523 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1524 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1525 size, clear_value_size / 4,
1526 &clear_value);
1527 si_blitter_end(ctx);
1528 return;
1529 }
1530 }
1531
1532 /* Expand the clear value to a dword. */
1533 switch (clear_value_size) {
1534 case 1:
1535 dword_value = *(uint8_t*)clear_value_ptr;
1536 dword_value |= (dword_value << 8) |
1537 (dword_value << 16) |
1538 (dword_value << 24);
1539 break;
1540 case 2:
1541 dword_value = *(uint16_t*)clear_value_ptr;
1542 dword_value |= dword_value << 16;
1543 break;
1544 default:
1545 dword_value = *(uint32_t*)clear_value_ptr;
1546 }
1547
1548 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1549 R600_COHERENCY_SHADER);
1550 }
1551
1552 void si_init_blit_functions(struct si_context *sctx)
1553 {
1554 sctx->b.b.clear = si_clear;
1555 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1556 sctx->b.b.clear_render_target = si_clear_render_target;
1557 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1558 sctx->b.b.resource_copy_region = si_resource_copy_region;
1559 sctx->b.b.blit = si_blit;
1560 sctx->b.b.flush_resource = si_flush_resource;
1561 sctx->b.b.generate_mipmap = si_generate_mipmap;
1562 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1563 sctx->b.decompress_dcc = si_decompress_dcc;
1564 }