2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_compute.h"
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
35 SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
| SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
37 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
| SI_SAVE_FRAGMENT_STATE
,
39 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
41 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
44 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
)
46 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
47 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
48 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
49 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
50 util_blitter_save_so_targets(sctx
->blitter
, sctx
->streamout
.num_targets
,
51 (struct pipe_stream_output_target
**)sctx
->streamout
.targets
);
52 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
54 if (op
& SI_SAVE_FRAGMENT_STATE
) {
55 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
56 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
57 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
58 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
59 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
);
60 util_blitter_save_scissor(sctx
->blitter
, &sctx
->scissors
[0]);
61 util_blitter_save_window_rectangles(sctx
->blitter
, sctx
->window_rectangles_include
,
62 sctx
->num_window_rectangles
, sctx
->window_rectangles
);
65 if (op
& SI_SAVE_FRAMEBUFFER
)
66 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
68 if (op
& SI_SAVE_TEXTURES
) {
69 util_blitter_save_fragment_sampler_states(
70 sctx
->blitter
, 2, (void **)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].sampler_states
);
72 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
73 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
);
76 if (op
& SI_DISABLE_RENDER_COND
)
77 sctx
->render_cond_force_off
= true;
79 if (sctx
->screen
->dpbb_allowed
) {
80 sctx
->dpbb_force_off
= true;
81 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
85 void si_blitter_end(struct si_context
*sctx
)
87 if (sctx
->screen
->dpbb_allowed
) {
88 sctx
->dpbb_force_off
= false;
89 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
92 sctx
->render_cond_force_off
= false;
94 /* Restore shader pointers because the VS blit shader changed all
95 * non-global VS user SGPRs. */
96 sctx
->shader_pointers_dirty
|= SI_DESCS_SHADER_MASK(VERTEX
);
97 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
98 sctx
->vertex_buffer_user_sgprs_dirty
= sctx
->num_vertex_elements
> 0;
99 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
102 static unsigned u_max_sample(struct pipe_resource
*r
)
104 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
107 static unsigned si_blit_dbcb_copy(struct si_context
*sctx
, struct si_texture
*src
,
108 struct si_texture
*dst
, unsigned planes
, unsigned level_mask
,
109 unsigned first_layer
, unsigned last_layer
, unsigned first_sample
,
110 unsigned last_sample
)
112 struct pipe_surface surf_tmpl
= {{0}};
113 unsigned layer
, sample
, checked_last_layer
, max_layer
;
114 unsigned fully_copied_levels
= 0;
116 if (planes
& PIPE_MASK_Z
)
117 sctx
->dbcb_depth_copy_enabled
= true;
118 if (planes
& PIPE_MASK_S
)
119 sctx
->dbcb_stencil_copy_enabled
= true;
120 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
122 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
124 sctx
->decompression_enabled
= true;
127 unsigned level
= u_bit_scan(&level_mask
);
129 /* The smaller the mipmap level, the less layers there are
130 * as far as 3D textures are concerned. */
131 max_layer
= util_max_layer(&src
->buffer
.b
.b
, level
);
132 checked_last_layer
= MIN2(last_layer
, max_layer
);
134 surf_tmpl
.u
.tex
.level
= level
;
136 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
137 struct pipe_surface
*zsurf
, *cbsurf
;
139 surf_tmpl
.format
= src
->buffer
.b
.b
.format
;
140 surf_tmpl
.u
.tex
.first_layer
= layer
;
141 surf_tmpl
.u
.tex
.last_layer
= layer
;
143 zsurf
= sctx
->b
.create_surface(&sctx
->b
, &src
->buffer
.b
.b
, &surf_tmpl
);
145 surf_tmpl
.format
= dst
->buffer
.b
.b
.format
;
146 cbsurf
= sctx
->b
.create_surface(&sctx
->b
, &dst
->buffer
.b
.b
, &surf_tmpl
);
148 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
149 if (sample
!= sctx
->dbcb_copy_sample
) {
150 sctx
->dbcb_copy_sample
= sample
;
151 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
154 si_blitter_begin(sctx
, SI_DECOMPRESS
);
155 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
156 sctx
->custom_dsa_flush
, 1.0f
);
157 si_blitter_end(sctx
);
160 pipe_surface_reference(&zsurf
, NULL
);
161 pipe_surface_reference(&cbsurf
, NULL
);
164 if (first_layer
== 0 && last_layer
>= max_layer
&& first_sample
== 0 &&
165 last_sample
>= u_max_sample(&src
->buffer
.b
.b
))
166 fully_copied_levels
|= 1u << level
;
169 sctx
->decompression_enabled
= false;
170 sctx
->dbcb_depth_copy_enabled
= false;
171 sctx
->dbcb_stencil_copy_enabled
= false;
172 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
174 return fully_copied_levels
;
177 /* Helper function for si_blit_decompress_zs_in_place.
179 static void si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
180 struct si_texture
*texture
, unsigned planes
,
181 unsigned level_mask
, unsigned first_layer
,
184 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
185 unsigned layer
, max_layer
, checked_last_layer
;
186 unsigned fully_decompressed_mask
= 0;
191 if (planes
& PIPE_MASK_S
)
192 sctx
->db_flush_stencil_inplace
= true;
193 if (planes
& PIPE_MASK_Z
)
194 sctx
->db_flush_depth_inplace
= true;
195 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
197 surf_tmpl
.format
= texture
->buffer
.b
.b
.format
;
199 sctx
->decompression_enabled
= true;
202 unsigned level
= u_bit_scan(&level_mask
);
204 surf_tmpl
.u
.tex
.level
= level
;
206 /* The smaller the mipmap level, the less layers there are
207 * as far as 3D textures are concerned. */
208 max_layer
= util_max_layer(&texture
->buffer
.b
.b
, level
);
209 checked_last_layer
= MIN2(last_layer
, max_layer
);
211 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
212 surf_tmpl
.u
.tex
.first_layer
= layer
;
213 surf_tmpl
.u
.tex
.last_layer
= layer
;
215 zsurf
= sctx
->b
.create_surface(&sctx
->b
, &texture
->buffer
.b
.b
, &surf_tmpl
);
217 si_blitter_begin(sctx
, SI_DECOMPRESS
);
218 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0, sctx
->custom_dsa_flush
,
220 si_blitter_end(sctx
);
222 pipe_surface_reference(&zsurf
, NULL
);
225 /* The texture will always be dirty if some layers aren't flushed.
226 * I don't think this case occurs often though. */
227 if (first_layer
== 0 && last_layer
>= max_layer
) {
228 fully_decompressed_mask
|= 1u << level
;
232 if (planes
& PIPE_MASK_Z
)
233 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
234 if (planes
& PIPE_MASK_S
)
235 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
237 sctx
->decompression_enabled
= false;
238 sctx
->db_flush_depth_inplace
= false;
239 sctx
->db_flush_stencil_inplace
= false;
240 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
243 /* Helper function of si_flush_depth_texture: decompress the given levels
244 * of Z and/or S planes in place.
246 static void si_blit_decompress_zs_in_place(struct si_context
*sctx
, struct si_texture
*texture
,
247 unsigned levels_z
, unsigned levels_s
,
248 unsigned first_layer
, unsigned last_layer
)
250 unsigned both
= levels_z
& levels_s
;
252 /* First, do combined Z & S decompresses for levels that need it. */
254 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
, both
,
255 first_layer
, last_layer
);
260 /* Now do separate Z and S decompresses. */
262 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_Z
, levels_z
, first_layer
,
267 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_S
, levels_s
, first_layer
,
272 static void si_decompress_depth(struct si_context
*sctx
, struct si_texture
*tex
,
273 unsigned required_planes
, unsigned first_level
, unsigned last_level
,
274 unsigned first_layer
, unsigned last_layer
)
276 unsigned inplace_planes
= 0;
277 unsigned copy_planes
= 0;
278 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
279 unsigned levels_z
= 0;
280 unsigned levels_s
= 0;
282 if (required_planes
& PIPE_MASK_Z
) {
283 levels_z
= level_mask
& tex
->dirty_level_mask
;
286 if (si_can_sample_zs(tex
, false))
287 inplace_planes
|= PIPE_MASK_Z
;
289 copy_planes
|= PIPE_MASK_Z
;
292 if (required_planes
& PIPE_MASK_S
) {
293 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
296 if (si_can_sample_zs(tex
, true))
297 inplace_planes
|= PIPE_MASK_S
;
299 copy_planes
|= PIPE_MASK_S
;
303 if (unlikely(sctx
->log
))
304 u_log_printf(sctx
->log
,
305 "\n------------------------------------------------\n"
306 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
307 first_level
, last_level
, levels_z
, levels_s
);
309 /* We may have to allocate the flushed texture here when called from
310 * si_decompress_subresource.
313 (tex
->flushed_depth_texture
|| si_init_flushed_depth_texture(&sctx
->b
, &tex
->buffer
.b
.b
))) {
314 struct si_texture
*dst
= tex
->flushed_depth_texture
;
315 unsigned fully_copied_levels
;
318 assert(tex
->flushed_depth_texture
);
320 if (util_format_is_depth_and_stencil(dst
->buffer
.b
.b
.format
))
321 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
323 if (copy_planes
& PIPE_MASK_Z
) {
327 if (copy_planes
& PIPE_MASK_S
) {
332 fully_copied_levels
= si_blit_dbcb_copy(sctx
, tex
, dst
, copy_planes
, levels
, first_layer
,
333 last_layer
, 0, u_max_sample(&tex
->buffer
.b
.b
));
335 if (copy_planes
& PIPE_MASK_Z
)
336 tex
->dirty_level_mask
&= ~fully_copied_levels
;
337 if (copy_planes
& PIPE_MASK_S
)
338 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
341 if (inplace_planes
) {
342 bool has_htile
= si_htile_enabled(tex
, first_level
, inplace_planes
);
343 bool tc_compat_htile
= vi_tc_compat_htile_enabled(tex
, first_level
, inplace_planes
);
345 /* Don't decompress if there is no HTILE or when HTILE is
347 if (has_htile
&& !tc_compat_htile
) {
348 si_blit_decompress_zs_in_place(sctx
, tex
, levels_z
, levels_s
, first_layer
, last_layer
);
350 /* This is only a cache flush.
352 * Only clear the mask that we are flushing, because
353 * si_make_DB_shader_coherent() treats different levels
354 * and depth and stencil differently.
356 if (inplace_planes
& PIPE_MASK_Z
)
357 tex
->dirty_level_mask
&= ~levels_z
;
358 if (inplace_planes
& PIPE_MASK_S
)
359 tex
->stencil_dirty_level_mask
&= ~levels_s
;
362 /* Only in-place decompression needs to flush DB caches, or
363 * when we don't decompress but TC-compatible planes are dirty.
365 si_make_DB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, inplace_planes
& PIPE_MASK_S
,
368 /* set_framebuffer_state takes care of coherency for single-sample.
369 * The DB->CB copy uses CB for the final writes.
371 if (copy_planes
&& tex
->buffer
.b
.b
.nr_samples
> 1)
372 si_make_CB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, false, true /* no DCC */);
375 static void si_decompress_sampler_depth_textures(struct si_context
*sctx
,
376 struct si_samplers
*textures
)
379 unsigned mask
= textures
->needs_depth_decompress_mask
;
382 struct pipe_sampler_view
*view
;
383 struct si_sampler_view
*sview
;
384 struct si_texture
*tex
;
386 i
= u_bit_scan(&mask
);
388 view
= textures
->views
[i
];
390 sview
= (struct si_sampler_view
*)view
;
392 tex
= (struct si_texture
*)view
->texture
;
393 assert(tex
->db_compatible
);
395 si_decompress_depth(sctx
, tex
, sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
396 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
, 0,
397 util_max_layer(&tex
->buffer
.b
.b
, view
->u
.tex
.first_level
));
401 static void si_blit_decompress_color(struct si_context
*sctx
, struct si_texture
*tex
,
402 unsigned first_level
, unsigned last_level
,
403 unsigned first_layer
, unsigned last_layer
,
404 bool need_dcc_decompress
, bool need_fmask_expand
)
407 unsigned layer
, checked_last_layer
, max_layer
;
408 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
410 if (!need_dcc_decompress
)
411 level_mask
&= tex
->dirty_level_mask
;
415 if (unlikely(sctx
->log
))
416 u_log_printf(sctx
->log
,
417 "\n------------------------------------------------\n"
418 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
419 first_level
, last_level
, level_mask
);
421 if (need_dcc_decompress
) {
422 assert(sctx
->chip_class
== GFX8
);
423 custom_blend
= sctx
->custom_blend_dcc_decompress
;
425 assert(tex
->surface
.dcc_offset
);
427 /* disable levels without DCC */
428 for (int i
= first_level
; i
<= last_level
; i
++) {
429 if (!vi_dcc_enabled(tex
, i
))
430 level_mask
&= ~(1 << i
);
432 } else if (tex
->surface
.fmask_size
) {
433 custom_blend
= sctx
->custom_blend_fmask_decompress
;
435 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
438 sctx
->decompression_enabled
= true;
441 unsigned level
= u_bit_scan(&level_mask
);
443 /* The smaller the mipmap level, the less layers there are
444 * as far as 3D textures are concerned. */
445 max_layer
= util_max_layer(&tex
->buffer
.b
.b
, level
);
446 checked_last_layer
= MIN2(last_layer
, max_layer
);
448 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
449 struct pipe_surface
*cbsurf
, surf_tmpl
;
451 surf_tmpl
.format
= tex
->buffer
.b
.b
.format
;
452 surf_tmpl
.u
.tex
.level
= level
;
453 surf_tmpl
.u
.tex
.first_layer
= layer
;
454 surf_tmpl
.u
.tex
.last_layer
= layer
;
455 cbsurf
= sctx
->b
.create_surface(&sctx
->b
, &tex
->buffer
.b
.b
, &surf_tmpl
);
457 /* Required before and after FMASK and DCC_DECOMPRESS. */
458 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
459 custom_blend
== sctx
->custom_blend_dcc_decompress
)
460 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
462 si_blitter_begin(sctx
, SI_DECOMPRESS
);
463 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
464 si_blitter_end(sctx
);
466 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
467 custom_blend
== sctx
->custom_blend_dcc_decompress
)
468 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
470 pipe_surface_reference(&cbsurf
, NULL
);
473 /* The texture will always be dirty if some layers aren't flushed.
474 * I don't think this case occurs often though. */
475 if (first_layer
== 0 && last_layer
>= max_layer
) {
476 tex
->dirty_level_mask
&= ~(1 << level
);
480 sctx
->decompression_enabled
= false;
481 si_make_CB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, vi_dcc_enabled(tex
, first_level
),
482 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
485 if (need_fmask_expand
&& tex
->surface
.fmask_offset
&& !tex
->fmask_is_identity
) {
486 si_compute_expand_fmask(&sctx
->b
, &tex
->buffer
.b
.b
);
487 tex
->fmask_is_identity
= true;
491 static void si_decompress_color_texture(struct si_context
*sctx
, struct si_texture
*tex
,
492 unsigned first_level
, unsigned last_level
,
493 bool need_fmask_expand
)
495 /* CMASK or DCC can be discarded and we can still end up here. */
496 if (!tex
->cmask_buffer
&& !tex
->surface
.fmask_size
&& !tex
->surface
.dcc_offset
)
499 si_blit_decompress_color(sctx
, tex
, first_level
, last_level
, 0,
500 util_max_layer(&tex
->buffer
.b
.b
, first_level
), false,
504 static void si_decompress_sampler_color_textures(struct si_context
*sctx
,
505 struct si_samplers
*textures
)
508 unsigned mask
= textures
->needs_color_decompress_mask
;
511 struct pipe_sampler_view
*view
;
512 struct si_texture
*tex
;
514 i
= u_bit_scan(&mask
);
516 view
= textures
->views
[i
];
519 tex
= (struct si_texture
*)view
->texture
;
521 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
526 static void si_decompress_image_color_textures(struct si_context
*sctx
, struct si_images
*images
)
529 unsigned mask
= images
->needs_color_decompress_mask
;
532 const struct pipe_image_view
*view
;
533 struct si_texture
*tex
;
535 i
= u_bit_scan(&mask
);
537 view
= &images
->views
[i
];
538 assert(view
->resource
->target
!= PIPE_BUFFER
);
540 tex
= (struct si_texture
*)view
->resource
;
542 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
543 view
->access
& PIPE_IMAGE_ACCESS_WRITE
);
547 static void si_check_render_feedback_texture(struct si_context
*sctx
, struct si_texture
*tex
,
548 unsigned first_level
, unsigned last_level
,
549 unsigned first_layer
, unsigned last_layer
)
551 bool render_feedback
= false;
553 if (!tex
->surface
.dcc_offset
)
556 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
557 struct si_surface
*surf
;
559 if (!sctx
->framebuffer
.state
.cbufs
[j
])
562 surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
564 if (tex
== (struct si_texture
*)surf
->base
.texture
&& surf
->base
.u
.tex
.level
>= first_level
&&
565 surf
->base
.u
.tex
.level
<= last_level
&& surf
->base
.u
.tex
.first_layer
<= last_layer
&&
566 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
567 render_feedback
= true;
573 si_texture_disable_dcc(sctx
, tex
);
576 static void si_check_render_feedback_textures(struct si_context
*sctx
, struct si_samplers
*textures
)
578 uint32_t mask
= textures
->enabled_mask
;
581 const struct pipe_sampler_view
*view
;
582 struct si_texture
*tex
;
584 unsigned i
= u_bit_scan(&mask
);
586 view
= textures
->views
[i
];
587 if (view
->texture
->target
== PIPE_BUFFER
)
590 tex
= (struct si_texture
*)view
->texture
;
592 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
593 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
597 static void si_check_render_feedback_images(struct si_context
*sctx
, struct si_images
*images
)
599 uint32_t mask
= images
->enabled_mask
;
602 const struct pipe_image_view
*view
;
603 struct si_texture
*tex
;
605 unsigned i
= u_bit_scan(&mask
);
607 view
= &images
->views
[i
];
608 if (view
->resource
->target
== PIPE_BUFFER
)
611 tex
= (struct si_texture
*)view
->resource
;
613 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
614 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
618 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
620 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
621 struct pipe_sampler_view
*view
;
622 struct si_texture
*tex
;
624 view
= (*tex_handle
)->view
;
625 if (view
->texture
->target
== PIPE_BUFFER
)
628 tex
= (struct si_texture
*)view
->texture
;
630 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
631 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
635 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
637 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
638 struct pipe_image_view
*view
;
639 struct si_texture
*tex
;
641 view
= &(*img_handle
)->view
;
642 if (view
->resource
->target
== PIPE_BUFFER
)
645 tex
= (struct si_texture
*)view
->resource
;
647 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
648 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
652 static void si_check_render_feedback(struct si_context
*sctx
)
654 if (!sctx
->need_check_render_feedback
)
657 /* There is no render feedback if color writes are disabled.
658 * (e.g. a pixel shader with image stores)
660 if (!si_get_total_colormask(sctx
))
663 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
664 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
665 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
668 si_check_render_feedback_resident_images(sctx
);
669 si_check_render_feedback_resident_textures(sctx
);
671 sctx
->need_check_render_feedback
= false;
674 static void si_decompress_resident_textures(struct si_context
*sctx
)
676 util_dynarray_foreach (&sctx
->resident_tex_needs_color_decompress
, struct si_texture_handle
*,
678 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
679 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
681 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
685 util_dynarray_foreach (&sctx
->resident_tex_needs_depth_decompress
, struct si_texture_handle
*,
687 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
688 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
689 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
691 si_decompress_depth(sctx
, tex
, sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
692 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
, 0,
693 util_max_layer(&tex
->buffer
.b
.b
, view
->u
.tex
.first_level
));
697 static void si_decompress_resident_images(struct si_context
*sctx
)
699 util_dynarray_foreach (&sctx
->resident_img_needs_color_decompress
, struct si_image_handle
*,
701 struct pipe_image_view
*view
= &(*img_handle
)->view
;
702 struct si_texture
*tex
= (struct si_texture
*)view
->resource
;
704 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
705 view
->access
& PIPE_IMAGE_ACCESS_WRITE
);
709 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
711 unsigned compressed_colortex_counter
, mask
;
713 if (sctx
->blitter
->running
)
716 /* Update the compressed_colortex_mask if necessary. */
717 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->compressed_colortex_counter
);
718 if (compressed_colortex_counter
!= sctx
->last_compressed_colortex_counter
) {
719 sctx
->last_compressed_colortex_counter
= compressed_colortex_counter
;
720 si_update_needs_color_decompress_masks(sctx
);
723 /* Decompress color & depth textures if needed. */
724 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
726 unsigned i
= u_bit_scan(&mask
);
728 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
729 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
731 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
732 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
734 if (sctx
->images
[i
].needs_color_decompress_mask
) {
735 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
739 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
740 if (sctx
->uses_bindless_samplers
)
741 si_decompress_resident_textures(sctx
);
742 if (sctx
->uses_bindless_images
)
743 si_decompress_resident_images(sctx
);
745 if (sctx
->ps_uses_fbfetch
) {
746 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
747 si_decompress_color_texture(sctx
, (struct si_texture
*)cb0
->texture
,
748 cb0
->u
.tex
.first_layer
, cb0
->u
.tex
.last_layer
, false);
751 si_check_render_feedback(sctx
);
752 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
753 if (sctx
->cs_shader_state
.program
->sel
.info
.uses_bindless_samplers
)
754 si_decompress_resident_textures(sctx
);
755 if (sctx
->cs_shader_state
.program
->sel
.info
.uses_bindless_images
)
756 si_decompress_resident_images(sctx
);
760 /* Helper for decompressing a portion of a color or depth resource before
761 * blitting if any decompression is needed.
762 * The driver doesn't decompress resources automatically while u_blitter is
764 void si_decompress_subresource(struct pipe_context
*ctx
, struct pipe_resource
*tex
, unsigned planes
,
765 unsigned level
, unsigned first_layer
, unsigned last_layer
)
767 struct si_context
*sctx
= (struct si_context
*)ctx
;
768 struct si_texture
*stex
= (struct si_texture
*)tex
;
770 if (stex
->db_compatible
) {
771 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
773 if (!stex
->surface
.has_stencil
)
774 planes
&= ~PIPE_MASK_S
;
776 /* If we've rendered into the framebuffer and it's a blitting
777 * source, make sure the decompression pass is invoked
778 * by dirtying the framebuffer.
780 if (sctx
->framebuffer
.state
.zsbuf
&& sctx
->framebuffer
.state
.zsbuf
->u
.tex
.level
== level
&&
781 sctx
->framebuffer
.state
.zsbuf
->texture
== tex
)
782 si_update_fb_dirtiness_after_rendering(sctx
);
784 si_decompress_depth(sctx
, stex
, planes
, level
, level
, first_layer
, last_layer
);
785 } else if (stex
->surface
.fmask_size
|| stex
->cmask_buffer
|| stex
->surface
.dcc_offset
) {
786 /* If we've rendered into the framebuffer and it's a blitting
787 * source, make sure the decompression pass is invoked
788 * by dirtying the framebuffer.
790 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
791 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
792 sctx
->framebuffer
.state
.cbufs
[i
]->u
.tex
.level
== level
&&
793 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== tex
) {
794 si_update_fb_dirtiness_after_rendering(sctx
);
799 si_blit_decompress_color(sctx
, stex
, level
, level
, first_layer
, last_layer
, false, false);
803 struct texture_orig_info
{
813 void si_resource_copy_region(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
814 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
815 struct pipe_resource
*src
, unsigned src_level
,
816 const struct pipe_box
*src_box
)
818 struct si_context
*sctx
= (struct si_context
*)ctx
;
819 struct si_texture
*ssrc
= (struct si_texture
*)src
;
820 struct si_texture
*sdst
= (struct si_texture
*)dst
;
821 struct pipe_surface
*dst_view
, dst_templ
;
822 struct pipe_sampler_view src_templ
, *src_view
;
823 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
824 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
825 struct pipe_box sbox
, dstbox
;
827 /* Handle buffers first. */
828 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
829 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
833 if (!util_format_is_compressed(src
->format
) && !util_format_is_compressed(dst
->format
) &&
834 !util_format_is_depth_or_stencil(src
->format
) && src
->nr_samples
<= 1 &&
835 !sdst
->surface
.dcc_offset
&&
836 !(dst
->target
!= src
->target
&&
837 (src
->target
== PIPE_TEXTURE_1D_ARRAY
|| dst
->target
== PIPE_TEXTURE_1D_ARRAY
))) {
838 si_compute_copy_image(sctx
, dst
, dst_level
, src
, src_level
, dstx
, dsty
, dstz
,
843 assert(u_max_sample(dst
) == u_max_sample(src
));
845 /* The driver doesn't decompress resources automatically while
846 * u_blitter is rendering. */
847 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
, src_box
->z
,
848 src_box
->z
+ src_box
->depth
- 1);
850 dst_width
= u_minify(dst
->width0
, dst_level
);
851 dst_height
= u_minify(dst
->height0
, dst_level
);
852 dst_width0
= dst
->width0
;
853 dst_height0
= dst
->height0
;
854 src_width0
= src
->width0
;
855 src_height0
= src
->height0
;
857 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
858 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
860 if (util_format_is_compressed(src
->format
) || util_format_is_compressed(dst
->format
)) {
861 unsigned blocksize
= ssrc
->surface
.bpe
;
864 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
866 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
867 dst_templ
.format
= src_templ
.format
;
869 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
870 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
871 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
872 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
873 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
874 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
876 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
877 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
879 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
880 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
882 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
883 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
884 sbox
.depth
= src_box
->depth
;
887 src_force_level
= src_level
;
888 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
889 if (util_format_is_subsampled_422(src
->format
)) {
890 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
891 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
893 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
894 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
895 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
897 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
900 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
901 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
904 unsigned blocksize
= ssrc
->surface
.bpe
;
908 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
909 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
912 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
913 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
916 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
917 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
920 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
921 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
924 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
925 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
928 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
929 util_format_short_name(src
->format
), blocksize
);
935 /* SNORM8 blitting has precision issues on some chips. Use the SINT
936 * equivalent instead, which doesn't force DCC decompression.
937 * Note that some chips avoid this issue by using SDMA.
939 if (util_format_is_snorm8(dst_templ
.format
)) {
940 dst_templ
.format
= src_templ
.format
= util_format_snorm8_to_sint8(dst_templ
.format
);
943 vi_disable_dcc_if_incompatible_format(sctx
, dst
, dst_level
, dst_templ
.format
);
944 vi_disable_dcc_if_incompatible_format(sctx
, src
, src_level
, src_templ
.format
);
946 /* Initialize the surface. */
947 dst_view
= si_create_surface_custom(ctx
, dst
, &dst_templ
, dst_width0
, dst_height0
, dst_width
,
950 /* Initialize the sampler view. */
952 si_create_sampler_view_custom(ctx
, src
, &src_templ
, src_width0
, src_height0
, src_force_level
);
954 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
), abs(src_box
->depth
),
958 si_blitter_begin(sctx
, SI_COPY
);
959 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
, src_view
, src_box
, src_width0
,
960 src_height0
, PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
, false);
961 si_blitter_end(sctx
);
963 pipe_surface_reference(&dst_view
, NULL
);
964 pipe_sampler_view_reference(&src_view
, NULL
);
967 static void si_do_CB_resolve(struct si_context
*sctx
, const struct pipe_blit_info
*info
,
968 struct pipe_resource
*dst
, unsigned dst_level
, unsigned dst_z
,
969 enum pipe_format format
)
971 /* Required before and after CB_RESOLVE. */
972 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
975 sctx
, SI_COLOR_RESOLVE
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
976 util_blitter_custom_resolve_color(sctx
->blitter
, dst
, dst_level
, dst_z
, info
->src
.resource
,
977 info
->src
.box
.z
, ~0, sctx
->custom_blend_resolve
, format
);
978 si_blitter_end(sctx
);
980 /* Flush caches for possible texturing. */
981 si_make_CB_shader_coherent(sctx
, 1, false, true /* no DCC */);
984 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
, const struct pipe_blit_info
*info
)
986 struct si_context
*sctx
= (struct si_context
*)ctx
;
987 struct si_texture
*src
= (struct si_texture
*)info
->src
.resource
;
988 struct si_texture
*dst
= (struct si_texture
*)info
->dst
.resource
;
989 ASSERTED
struct si_texture
*stmp
;
990 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
991 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
992 enum pipe_format format
= info
->src
.format
;
993 struct pipe_resource
*tmp
, templ
;
994 struct pipe_blit_info blit
;
996 /* Check basic requirements for hw resolve. */
997 if (!(info
->src
.resource
->nr_samples
> 1 && info
->dst
.resource
->nr_samples
<= 1 &&
998 !util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
) &&
999 util_max_layer(info
->src
.resource
, 0) == 0))
1002 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1003 * the format is R16G16. Use R16A16, which does work.
1005 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1006 format
= PIPE_FORMAT_R16A16_UNORM
;
1007 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1008 format
= PIPE_FORMAT_R16A16_SNORM
;
1010 /* Check the remaining requirements for hw resolve. */
1011 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 && !info
->scissor_enable
&&
1012 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1013 util_is_format_compatible(util_format_description(info
->src
.format
),
1014 util_format_description(info
->dst
.format
)) &&
1015 dst_width
== info
->src
.resource
->width0
&& dst_height
== info
->src
.resource
->height0
&&
1016 info
->dst
.box
.x
== 0 && info
->dst
.box
.y
== 0 && info
->dst
.box
.width
== dst_width
&&
1017 info
->dst
.box
.height
== dst_height
&& info
->dst
.box
.depth
== 1 && info
->src
.box
.x
== 0 &&
1018 info
->src
.box
.y
== 0 && info
->src
.box
.width
== dst_width
&&
1019 info
->src
.box
.height
== dst_height
&& info
->src
.box
.depth
== 1 && !dst
->surface
.is_linear
&&
1020 (!dst
->cmask_buffer
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1021 /* Check the last constraint. */
1022 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1023 /* The next fast clear will switch to this mode to
1024 * get direct hw resolve next time if the mode is
1027 * TODO-GFX10: This does not work in GFX10 because MSAA
1028 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1029 * In some cases we could change the swizzle of the
1030 * destination texture instead, but the more general
1031 * solution is to implement compute shader resolve.
1033 src
->last_msaa_resolve_target_micro_mode
= dst
->surface
.micro_tile_mode
;
1034 goto resolve_to_temp
;
1037 /* Resolving into a surface with DCC is unsupported. Since
1038 * it's being overwritten anyway, clear it to uncompressed.
1039 * This is still the fastest codepath even with this clear.
1041 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1042 if (!vi_dcc_clear_level(sctx
, dst
, info
->dst
.level
, DCC_UNCOMPRESSED
))
1043 goto resolve_to_temp
;
1045 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1048 /* Resolve directly from src to dst. */
1049 si_do_CB_resolve(sctx
, info
, info
->dst
.resource
, info
->dst
.level
, info
->dst
.box
.z
, format
);
1054 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1055 * a temporary texture and blit.
1057 memset(&templ
, 0, sizeof(templ
));
1058 templ
.target
= PIPE_TEXTURE_2D
;
1059 templ
.format
= info
->src
.resource
->format
;
1060 templ
.width0
= info
->src
.resource
->width0
;
1061 templ
.height0
= info
->src
.resource
->height0
;
1063 templ
.array_size
= 1;
1064 templ
.usage
= PIPE_USAGE_DEFAULT
;
1065 templ
.flags
= SI_RESOURCE_FLAG_FORCE_MSAA_TILING
| SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
|
1066 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src
->surface
.micro_tile_mode
) |
1067 SI_RESOURCE_FLAG_DISABLE_DCC
;
1069 /* The src and dst microtile modes must be the same. */
1070 if (sctx
->chip_class
<= GFX8
&& src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1071 templ
.bind
= PIPE_BIND_SCANOUT
;
1075 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1078 stmp
= (struct si_texture
*)tmp
;
1080 assert(!stmp
->surface
.is_linear
);
1081 assert(src
->surface
.micro_tile_mode
== stmp
->surface
.micro_tile_mode
);
1084 si_do_CB_resolve(sctx
, info
, tmp
, 0, 0, format
);
1088 blit
.src
.resource
= tmp
;
1091 si_blitter_begin(sctx
, SI_BLIT
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1092 util_blitter_blit(sctx
->blitter
, &blit
);
1093 si_blitter_end(sctx
);
1095 pipe_resource_reference(&tmp
, NULL
);
1099 static void si_blit(struct pipe_context
*ctx
, const struct pipe_blit_info
*info
)
1101 struct si_context
*sctx
= (struct si_context
*)ctx
;
1102 struct si_texture
*dst
= (struct si_texture
*)info
->dst
.resource
;
1104 if (do_hardware_msaa_resolve(ctx
, info
)) {
1108 /* Using SDMA for copying to a linear texture in GTT is much faster.
1109 * This improves DRI PRIME performance.
1111 * resource_copy_region can't do this yet, because dma_copy calls it
1112 * on failure (recursion).
1114 if (dst
->surface
.is_linear
&& util_can_blit_via_copy_region(info
, false)) {
1115 sctx
->dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
, info
->dst
.box
.x
, info
->dst
.box
.y
,
1116 info
->dst
.box
.z
, info
->src
.resource
, info
->src
.level
, &info
->src
.box
);
1120 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1122 /* The driver doesn't decompress resources automatically while
1123 * u_blitter is rendering. */
1124 vi_disable_dcc_if_incompatible_format(sctx
, info
->src
.resource
, info
->src
.level
,
1126 vi_disable_dcc_if_incompatible_format(sctx
, info
->dst
.resource
, info
->dst
.level
,
1128 si_decompress_subresource(ctx
, info
->src
.resource
, PIPE_MASK_RGBAZS
, info
->src
.level
,
1129 info
->src
.box
.z
, info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1131 if (sctx
->screen
->debug_flags
& DBG(FORCE_SDMA
) && util_try_blit_via_copy_region(ctx
, info
))
1134 si_blitter_begin(sctx
, SI_BLIT
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1135 util_blitter_blit(sctx
->blitter
, info
);
1136 si_blitter_end(sctx
);
1139 static bool si_generate_mipmap(struct pipe_context
*ctx
, struct pipe_resource
*tex
,
1140 enum pipe_format format
, unsigned base_level
, unsigned last_level
,
1141 unsigned first_layer
, unsigned last_layer
)
1143 struct si_context
*sctx
= (struct si_context
*)ctx
;
1144 struct si_texture
*stex
= (struct si_texture
*)tex
;
1146 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1149 /* The driver doesn't decompress resources automatically while
1150 * u_blitter is rendering. */
1151 vi_disable_dcc_if_incompatible_format(sctx
, tex
, base_level
, format
);
1152 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
, base_level
, first_layer
, last_layer
);
1154 /* Clear dirty_level_mask for the levels that will be overwritten. */
1155 assert(base_level
< last_level
);
1156 stex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1, last_level
- base_level
);
1158 sctx
->generate_mipmap_for_depth
= stex
->is_depth
;
1160 si_blitter_begin(sctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1161 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
, base_level
, last_level
, first_layer
,
1163 si_blitter_end(sctx
);
1165 sctx
->generate_mipmap_for_depth
= false;
1169 static void si_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*res
)
1171 struct si_context
*sctx
= (struct si_context
*)ctx
;
1172 struct si_texture
*tex
= (struct si_texture
*)res
;
1174 assert(res
->target
!= PIPE_BUFFER
);
1175 assert(!tex
->dcc_separate_buffer
|| tex
->dcc_gather_statistics
);
1177 /* st/dri calls flush twice per frame (not a bug), this prevents double
1179 if (tex
->dcc_separate_buffer
&& !tex
->separate_dcc_dirty
)
1182 if (!tex
->is_depth
&& (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
1183 si_blit_decompress_color(sctx
, tex
, 0, res
->last_level
, 0, util_max_layer(res
, 0),
1184 tex
->dcc_separate_buffer
!= NULL
, false);
1186 if (tex
->surface
.display_dcc_offset
&& tex
->displayable_dcc_dirty
) {
1187 si_retile_dcc(sctx
, tex
);
1188 tex
->displayable_dcc_dirty
= false;
1192 /* Always do the analysis even if DCC is disabled at the moment. */
1193 if (tex
->dcc_gather_statistics
) {
1194 bool separate_dcc_dirty
= tex
->separate_dcc_dirty
;
1196 /* If the color buffer hasn't been unbound and fast clear hasn't
1197 * been used, separate_dcc_dirty is false, but there may have been
1198 * new rendering. Check if the color buffer is bound and assume
1201 * Note that DRI2 never unbinds window colorbuffers, which means
1202 * the DCC pipeline statistics query would never be re-set and would
1203 * keep adding new results until all free memory is exhausted if we
1206 if (!separate_dcc_dirty
) {
1207 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
1208 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
1209 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== res
) {
1210 separate_dcc_dirty
= true;
1216 if (separate_dcc_dirty
) {
1217 tex
->separate_dcc_dirty
= false;
1218 vi_separate_dcc_process_and_reset_stats(ctx
, tex
);
1223 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
1225 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1226 * be compressed either. The caller should simply discard it.
1228 if (!tex
->surface
.dcc_offset
|| !sctx
->has_graphics
)
1231 if (sctx
->chip_class
== GFX8
) {
1232 si_blit_decompress_color(sctx
, tex
, 0, tex
->buffer
.b
.b
.last_level
, 0,
1233 util_max_layer(&tex
->buffer
.b
.b
, 0), true, false);
1235 struct pipe_resource
*ptex
= &tex
->buffer
.b
.b
;
1237 /* DCC decompression using a compute shader. */
1238 for (unsigned level
= 0; level
< tex
->surface
.num_dcc_levels
; level
++) {
1239 struct pipe_box box
;
1241 u_box_3d(0, 0, 0, u_minify(ptex
->width0
, level
),
1242 u_minify(ptex
->height0
, level
),
1243 util_num_layers(ptex
, level
), &box
);
1244 si_compute_copy_image(sctx
, ptex
, level
, ptex
, level
, 0, 0, 0, &box
,
1248 /* Now clear DCC metadata to uncompressed. */
1249 uint32_t clear_value
= DCC_UNCOMPRESSED
;
1250 si_clear_buffer(sctx
, ptex
, tex
->surface
.dcc_offset
,
1251 tex
->surface
.dcc_size
, &clear_value
, 4,
1252 SI_COHERENCY_CB_META
, false);
1256 void si_init_blit_functions(struct si_context
*sctx
)
1258 sctx
->b
.resource_copy_region
= si_resource_copy_region
;
1260 if (sctx
->has_graphics
) {
1261 sctx
->b
.blit
= si_blit
;
1262 sctx
->b
.flush_resource
= si_flush_resource
;
1263 sctx
->b
.generate_mipmap
= si_generate_mipmap
;