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radeonsi: don't update clear color registers if they don't change
[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct r600_texture *rtex)
39 {
40 if (rtex->cmask_buffer)
41 return;
42
43 assert(rtex->cmask.size == 0);
44
45 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
46 if (!rtex->cmask.size)
47 return;
48
49 rtex->cmask_buffer =
50 si_aligned_buffer_create(&sscreen->b,
51 SI_RESOURCE_FLAG_UNMAPPABLE,
52 PIPE_USAGE_DEFAULT,
53 rtex->cmask.size,
54 rtex->cmask.alignment);
55 if (rtex->cmask_buffer == NULL) {
56 rtex->cmask.size = 0;
57 return;
58 }
59
60 /* update colorbuffer state bits */
61 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
62
63 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
64
65 p_atomic_inc(&sscreen->compressed_colortex_counter);
66 }
67
68 static bool si_set_clear_color(struct r600_texture *rtex,
69 enum pipe_format surface_format,
70 const union pipe_color_union *color)
71 {
72 union util_color uc;
73
74 memset(&uc, 0, sizeof(uc));
75
76 if (rtex->surface.bpe == 16) {
77 /* DCC fast clear only:
78 * CLEAR_WORD0 = R = G = B
79 * CLEAR_WORD1 = A
80 */
81 assert(color->ui[0] == color->ui[1] &&
82 color->ui[0] == color->ui[2]);
83 uc.ui[0] = color->ui[0];
84 uc.ui[1] = color->ui[3];
85 } else if (util_format_is_pure_uint(surface_format)) {
86 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
87 } else if (util_format_is_pure_sint(surface_format)) {
88 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
89 } else {
90 util_pack_color(color->f, surface_format, &uc);
91 }
92
93 if (memcmp(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
94 return false;
95
96 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
97 return true;
98 }
99
100 /** Linearize and convert luminace/intensity to red. */
101 enum pipe_format si_simplify_cb_format(enum pipe_format format)
102 {
103 format = util_format_linear(format);
104 format = util_format_luminance_to_red(format);
105 return util_format_intensity_to_red(format);
106 }
107
108 bool vi_alpha_is_on_msb(enum pipe_format format)
109 {
110 format = si_simplify_cb_format(format);
111
112 /* Formats with 3 channels can't have alpha. */
113 if (util_format_description(format)->nr_channels == 3)
114 return true; /* same as xxxA; is any value OK here? */
115
116 return si_translate_colorswap(format, false) <= 1;
117 }
118
119 static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
120 enum pipe_format surface_format,
121 const union pipe_color_union *color,
122 uint32_t* clear_value,
123 bool *eliminate_needed)
124 {
125 /* If we want to clear without needing a fast clear eliminate step, we
126 * can set color and alpha independently to 0 or 1 (or 0/max for integer
127 * formats).
128 */
129 bool values[4] = {}; /* whether to clear to 0 or 1 */
130 bool color_value = false; /* clear color to 0 or 1 */
131 bool alpha_value = false; /* clear alpha to 0 or 1 */
132 int alpha_channel; /* index of the alpha component */
133 bool has_color = false;
134 bool has_alpha = false;
135
136 const struct util_format_description *desc =
137 util_format_description(si_simplify_cb_format(surface_format));
138
139 /* 128-bit fast clear with different R,G,B values is unsupported. */
140 if (desc->block.bits == 128 &&
141 (color->ui[0] != color->ui[1] ||
142 color->ui[0] != color->ui[2]))
143 return false;
144
145 *eliminate_needed = true;
146 *clear_value = 0x20202020U; /* use CB clear color registers */
147
148 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
149 return true; /* need ELIMINATE_FAST_CLEAR */
150
151 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(base_format);
152 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(surface_format);
153
154 /* Formats with 3 channels can't have alpha. */
155 if (desc->nr_channels == 3)
156 alpha_channel = -1;
157 else if (surf_alpha_is_on_msb)
158 alpha_channel = desc->nr_channels - 1;
159 else
160 alpha_channel = 0;
161
162 for (int i = 0; i < 4; ++i) {
163 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
164 continue;
165
166 if (desc->channel[i].pure_integer &&
167 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
168 /* Use the maximum value for clamping the clear color. */
169 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
170
171 values[i] = color->i[i] != 0;
172 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
173 return true; /* need ELIMINATE_FAST_CLEAR */
174 } else if (desc->channel[i].pure_integer &&
175 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
176 /* Use the maximum value for clamping the clear color. */
177 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
178
179 values[i] = color->ui[i] != 0U;
180 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
181 return true; /* need ELIMINATE_FAST_CLEAR */
182 } else {
183 values[i] = color->f[i] != 0.0F;
184 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
185 return true; /* need ELIMINATE_FAST_CLEAR */
186 }
187
188 if (desc->swizzle[i] == alpha_channel) {
189 alpha_value = values[i];
190 has_alpha = true;
191 } else {
192 color_value = values[i];
193 has_color = true;
194 }
195 }
196
197 /* If alpha isn't present, make it the same as color, and vice versa. */
198 if (!has_alpha)
199 alpha_value = color_value;
200 else if (!has_color)
201 color_value = alpha_value;
202
203 if (color_value != alpha_value &&
204 base_alpha_is_on_msb != surf_alpha_is_on_msb)
205 return true; /* require ELIMINATE_FAST_CLEAR */
206
207 /* Check if all color values are equal if they are present. */
208 for (int i = 0; i < 4; ++i) {
209 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
210 desc->swizzle[i] != alpha_channel &&
211 values[i] != color_value)
212 return true; /* require ELIMINATE_FAST_CLEAR */
213 }
214
215 /* This doesn't need ELIMINATE_FAST_CLEAR.
216 * CB uses both the DCC clear codes and the CB clear color registers,
217 * so they must match.
218 */
219 *eliminate_needed = false;
220
221 if (color_value)
222 *clear_value |= 0x80808080U;
223 if (alpha_value)
224 *clear_value |= 0x40404040U;
225 return true;
226 }
227
228 void vi_dcc_clear_level(struct si_context *sctx,
229 struct r600_texture *rtex,
230 unsigned level, unsigned clear_value)
231 {
232 struct pipe_resource *dcc_buffer;
233 uint64_t dcc_offset, clear_size;
234
235 assert(vi_dcc_enabled(rtex, level));
236
237 if (rtex->dcc_separate_buffer) {
238 dcc_buffer = &rtex->dcc_separate_buffer->b.b;
239 dcc_offset = 0;
240 } else {
241 dcc_buffer = &rtex->buffer.b.b;
242 dcc_offset = rtex->dcc_offset;
243 }
244
245 if (sctx->chip_class >= GFX9) {
246 /* Mipmap level clears aren't implemented. */
247 assert(rtex->buffer.b.b.last_level == 0);
248 /* 4x and 8x MSAA needs a sophisticated compute shader for
249 * the clear. See AMDVLK. */
250 assert(rtex->buffer.b.b.nr_samples <= 2);
251 clear_size = rtex->surface.dcc_size;
252 } else {
253 unsigned num_layers = util_num_layers(&rtex->buffer.b.b, level);
254
255 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
256 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
257 /* Layered 4x and 8x MSAA DCC fast clears need to clear
258 * dcc_fast_clear_size bytes for each layer. A compute shader
259 * would be more efficient than separate per-layer clear operations.
260 */
261 assert(rtex->buffer.b.b.nr_samples <= 2 || num_layers == 1);
262
263 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
264 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
265 num_layers;
266 }
267
268 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
269 clear_value, SI_COHERENCY_CB_META);
270 }
271
272 /* Set the same micro tile mode as the destination of the last MSAA resolve.
273 * This allows hitting the MSAA resolve fast path, which requires that both
274 * src and dst micro tile modes match.
275 */
276 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
277 struct r600_texture *rtex)
278 {
279 if (rtex->buffer.b.is_shared ||
280 rtex->buffer.b.b.nr_samples <= 1 ||
281 rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
282 return;
283
284 assert(sscreen->info.chip_class >= GFX9 ||
285 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
286 assert(rtex->buffer.b.b.last_level == 0);
287
288 if (sscreen->info.chip_class >= GFX9) {
289 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
290 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
291
292 /* If you do swizzle_mode % 4, you'll get:
293 * 0 = Depth
294 * 1 = Standard,
295 * 2 = Displayable
296 * 3 = Rotated
297 *
298 * Depth-sample order isn't allowed:
299 */
300 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
301
302 switch (rtex->last_msaa_resolve_target_micro_mode) {
303 case RADEON_MICRO_MODE_DISPLAY:
304 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
305 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
306 break;
307 case RADEON_MICRO_MODE_THIN:
308 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
309 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
310 break;
311 case RADEON_MICRO_MODE_ROTATED:
312 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
313 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
314 break;
315 default: /* depth */
316 assert(!"unexpected micro mode");
317 return;
318 }
319 } else if (sscreen->info.chip_class >= CIK) {
320 /* These magic numbers were copied from addrlib. It doesn't use
321 * any definitions for them either. They are all 2D_TILED_THIN1
322 * modes with different bpp and micro tile mode.
323 */
324 switch (rtex->last_msaa_resolve_target_micro_mode) {
325 case RADEON_MICRO_MODE_DISPLAY:
326 rtex->surface.u.legacy.tiling_index[0] = 10;
327 break;
328 case RADEON_MICRO_MODE_THIN:
329 rtex->surface.u.legacy.tiling_index[0] = 14;
330 break;
331 case RADEON_MICRO_MODE_ROTATED:
332 rtex->surface.u.legacy.tiling_index[0] = 28;
333 break;
334 default: /* depth, thick */
335 assert(!"unexpected micro mode");
336 return;
337 }
338 } else { /* SI */
339 switch (rtex->last_msaa_resolve_target_micro_mode) {
340 case RADEON_MICRO_MODE_DISPLAY:
341 switch (rtex->surface.bpe) {
342 case 1:
343 rtex->surface.u.legacy.tiling_index[0] = 10;
344 break;
345 case 2:
346 rtex->surface.u.legacy.tiling_index[0] = 11;
347 break;
348 default: /* 4, 8 */
349 rtex->surface.u.legacy.tiling_index[0] = 12;
350 break;
351 }
352 break;
353 case RADEON_MICRO_MODE_THIN:
354 switch (rtex->surface.bpe) {
355 case 1:
356 rtex->surface.u.legacy.tiling_index[0] = 14;
357 break;
358 case 2:
359 rtex->surface.u.legacy.tiling_index[0] = 15;
360 break;
361 case 4:
362 rtex->surface.u.legacy.tiling_index[0] = 16;
363 break;
364 default: /* 8, 16 */
365 rtex->surface.u.legacy.tiling_index[0] = 17;
366 break;
367 }
368 break;
369 default: /* depth, thick */
370 assert(!"unexpected micro mode");
371 return;
372 }
373 }
374
375 rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
376
377 p_atomic_inc(&sscreen->dirty_tex_counter);
378 }
379
380 static void si_do_fast_color_clear(struct si_context *sctx,
381 unsigned *buffers,
382 const union pipe_color_union *color)
383 {
384 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
385 int i;
386
387 /* This function is broken in BE, so just disable this path for now */
388 #ifdef PIPE_ARCH_BIG_ENDIAN
389 return;
390 #endif
391
392 if (sctx->render_cond)
393 return;
394
395 for (i = 0; i < fb->nr_cbufs; i++) {
396 struct r600_texture *tex;
397 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
398
399 if (!fb->cbufs[i])
400 continue;
401
402 /* if this colorbuffer is not being cleared */
403 if (!(*buffers & clear_bit))
404 continue;
405
406 unsigned level = fb->cbufs[i]->u.tex.level;
407 if (level > 0)
408 continue;
409
410 tex = (struct r600_texture *)fb->cbufs[i]->texture;
411
412 /* TODO: GFX9: Implement DCC fast clear for level 0 of
413 * mipmapped textures. Mipmapped DCC has to clear a rectangular
414 * area of DCC for level 0 (because the whole miptree is
415 * organized in a 2D plane).
416 */
417 if (sctx->chip_class >= GFX9 &&
418 tex->buffer.b.b.last_level > 0)
419 continue;
420
421 /* the clear is allowed if all layers are bound */
422 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
423 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
424 continue;
425 }
426
427 /* only supported on tiled surfaces */
428 if (tex->surface.is_linear) {
429 continue;
430 }
431
432 /* shared textures can't use fast clear without an explicit flush,
433 * because there is no way to communicate the clear color among
434 * all clients
435 */
436 if (tex->buffer.b.is_shared &&
437 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
438 continue;
439
440 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
441 if (sctx->chip_class == CIK &&
442 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
443 sctx->screen->info.drm_major == 2 &&
444 sctx->screen->info.drm_minor < 38) {
445 continue;
446 }
447
448 /* Fast clear is the most appropriate place to enable DCC for
449 * displayable surfaces.
450 */
451 if (sctx->chip_class >= VI &&
452 !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
453 vi_separate_dcc_try_enable(sctx, tex);
454
455 /* RB+ isn't supported with a CMASK clear only on Stoney,
456 * so all clears are considered to be hypothetically slow
457 * clears, which is weighed when determining whether to
458 * enable separate DCC.
459 */
460 if (tex->dcc_gather_statistics &&
461 sctx->family == CHIP_STONEY)
462 tex->num_slow_clears++;
463 }
464
465 bool need_decompress_pass = false;
466
467 /* Use a slow clear for small surfaces where the cost of
468 * the eliminate pass can be higher than the benefit of fast
469 * clear. The closed driver does this, but the numbers may differ.
470 *
471 * This helps on both dGPUs and APUs, even small APUs like Mullins.
472 */
473 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
474 tex->buffer.b.b.width0 *
475 tex->buffer.b.b.height0 <= 512 * 512;
476
477 /* Try to clear DCC first, otherwise try CMASK. */
478 if (vi_dcc_enabled(tex, 0)) {
479 uint32_t reset_value;
480 bool eliminate_needed;
481
482 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
483 continue;
484
485 /* This can only occur with MSAA. */
486 if (sctx->chip_class == VI &&
487 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
488 continue;
489
490 if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
491 fb->cbufs[i]->format,
492 color, &reset_value,
493 &eliminate_needed))
494 continue;
495
496 if (eliminate_needed && too_small)
497 continue;
498
499 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
500 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask.size) {
501 /* TODO: This doesn't work with MSAA. */
502 if (eliminate_needed)
503 continue;
504
505 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
506 tex->cmask.offset, tex->cmask.size,
507 0xCCCCCCCC, SI_COHERENCY_CB_META);
508 need_decompress_pass = true;
509 }
510
511 vi_dcc_clear_level(sctx, tex, 0, reset_value);
512
513 if (eliminate_needed)
514 need_decompress_pass = true;
515
516 tex->separate_dcc_dirty = true;
517 } else {
518 if (too_small)
519 continue;
520
521 /* 128-bit formats are unusupported */
522 if (tex->surface.bpe > 8) {
523 continue;
524 }
525
526 /* RB+ doesn't work with CMASK fast clear on Stoney. */
527 if (sctx->family == CHIP_STONEY)
528 continue;
529
530 /* ensure CMASK is enabled */
531 si_alloc_separate_cmask(sctx->screen, tex);
532 if (tex->cmask.size == 0) {
533 continue;
534 }
535
536 /* Do the fast clear. */
537 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
538 tex->cmask.offset, tex->cmask.size, 0,
539 SI_COHERENCY_CB_META);
540 need_decompress_pass = true;
541 }
542
543 if (need_decompress_pass &&
544 !(tex->dirty_level_mask & (1 << level))) {
545 tex->dirty_level_mask |= 1 << level;
546 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
547 }
548
549 /* We can change the micro tile mode before a full clear. */
550 si_set_optimal_micro_tile_mode(sctx->screen, tex);
551
552 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
553 sctx->framebuffer.dirty_cbufs |= 1 << i;
554 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
555 }
556 *buffers &= ~clear_bit;
557 }
558 }
559
560 static void si_clear(struct pipe_context *ctx, unsigned buffers,
561 const union pipe_color_union *color,
562 double depth, unsigned stencil)
563 {
564 struct si_context *sctx = (struct si_context *)ctx;
565 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
566 struct pipe_surface *zsbuf = fb->zsbuf;
567 struct r600_texture *zstex =
568 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
569
570 if (buffers & PIPE_CLEAR_COLOR) {
571 si_do_fast_color_clear(sctx, &buffers, color);
572 if (!buffers)
573 return; /* all buffers have been fast cleared */
574
575 /* These buffers cannot use fast clear, make sure to disable expansion. */
576 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
577 struct r600_texture *tex;
578
579 /* If not clearing this buffer, skip. */
580 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
581 continue;
582
583 tex = (struct r600_texture *)fb->cbufs[i]->texture;
584 if (tex->surface.fmask_size == 0)
585 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
586 }
587 }
588
589 if (zstex &&
590 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
591 zsbuf->u.tex.first_layer == 0 &&
592 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
593 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
594 if (buffers & PIPE_CLEAR_DEPTH &&
595 (!zstex->tc_compatible_htile ||
596 depth == 0 || depth == 1)) {
597 /* Need to disable EXPCLEAR temporarily if clearing
598 * to a new value. */
599 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
600 sctx->db_depth_disable_expclear = true;
601 }
602
603 if (zstex->depth_clear_value != (float)depth) {
604 /* Update DB_DEPTH_CLEAR. */
605 zstex->depth_clear_value = depth;
606 sctx->framebuffer.dirty_zsbuf = true;
607 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
608 }
609 sctx->db_depth_clear = true;
610 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
611 }
612
613 /* TC-compatible HTILE only supports stencil clears to 0. */
614 if (buffers & PIPE_CLEAR_STENCIL &&
615 (!zstex->tc_compatible_htile || stencil == 0)) {
616 stencil &= 0xff;
617
618 /* Need to disable EXPCLEAR temporarily if clearing
619 * to a new value. */
620 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
621 sctx->db_stencil_disable_expclear = true;
622 }
623
624 if (zstex->stencil_clear_value != (uint8_t)stencil) {
625 /* Update DB_STENCIL_CLEAR. */
626 zstex->stencil_clear_value = stencil;
627 sctx->framebuffer.dirty_zsbuf = true;
628 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
629 }
630 sctx->db_stencil_clear = true;
631 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
632 }
633
634 /* TODO: Find out what's wrong here. Fast depth clear leads to
635 * corruption in ARK: Survival Evolved, but that may just be
636 * a coincidence and the root cause is elsewhere.
637 *
638 * The corruption can be fixed by putting the DB flush before
639 * or after the depth clear. (surprisingly)
640 *
641 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
642 *
643 * This hack decreases back-to-back ClearDepth performance.
644 */
645 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
646 sctx->screen->clear_db_cache_before_clear)
647 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
648 }
649
650 si_blitter_begin(sctx, SI_CLEAR);
651 util_blitter_clear(sctx->blitter, fb->width, fb->height,
652 util_framebuffer_get_num_layers(fb),
653 buffers, color, depth, stencil);
654 si_blitter_end(sctx);
655
656 if (sctx->db_depth_clear) {
657 sctx->db_depth_clear = false;
658 sctx->db_depth_disable_expclear = false;
659 zstex->depth_cleared = true;
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
661 }
662
663 if (sctx->db_stencil_clear) {
664 sctx->db_stencil_clear = false;
665 sctx->db_stencil_disable_expclear = false;
666 zstex->stencil_cleared = true;
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
668 }
669 }
670
671 static void si_clear_render_target(struct pipe_context *ctx,
672 struct pipe_surface *dst,
673 const union pipe_color_union *color,
674 unsigned dstx, unsigned dsty,
675 unsigned width, unsigned height,
676 bool render_condition_enabled)
677 {
678 struct si_context *sctx = (struct si_context *)ctx;
679
680 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
681 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
682 util_blitter_clear_render_target(sctx->blitter, dst, color,
683 dstx, dsty, width, height);
684 si_blitter_end(sctx);
685 }
686
687 static void si_clear_depth_stencil(struct pipe_context *ctx,
688 struct pipe_surface *dst,
689 unsigned clear_flags,
690 double depth,
691 unsigned stencil,
692 unsigned dstx, unsigned dsty,
693 unsigned width, unsigned height,
694 bool render_condition_enabled)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697
698 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
699 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
700 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
701 dstx, dsty, width, height);
702 si_blitter_end(sctx);
703 }
704
705 static void si_clear_texture(struct pipe_context *pipe,
706 struct pipe_resource *tex,
707 unsigned level,
708 const struct pipe_box *box,
709 const void *data)
710 {
711 struct pipe_screen *screen = pipe->screen;
712 struct r600_texture *rtex = (struct r600_texture*)tex;
713 struct pipe_surface tmpl = {{0}};
714 struct pipe_surface *sf;
715 const struct util_format_description *desc =
716 util_format_description(tex->format);
717
718 tmpl.format = tex->format;
719 tmpl.u.tex.first_layer = box->z;
720 tmpl.u.tex.last_layer = box->z + box->depth - 1;
721 tmpl.u.tex.level = level;
722 sf = pipe->create_surface(pipe, tex, &tmpl);
723 if (!sf)
724 return;
725
726 if (rtex->is_depth) {
727 unsigned clear;
728 float depth;
729 uint8_t stencil = 0;
730
731 /* Depth is always present. */
732 clear = PIPE_CLEAR_DEPTH;
733 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
734
735 if (rtex->surface.has_stencil) {
736 clear |= PIPE_CLEAR_STENCIL;
737 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
738 }
739
740 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
741 box->x, box->y,
742 box->width, box->height, false);
743 } else {
744 union pipe_color_union color;
745
746 /* pipe_color_union requires the full vec4 representation. */
747 if (util_format_is_pure_uint(tex->format))
748 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
749 else if (util_format_is_pure_sint(tex->format))
750 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
751 else
752 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
753
754 if (screen->is_format_supported(screen, tex->format,
755 tex->target, 0,
756 PIPE_BIND_RENDER_TARGET)) {
757 si_clear_render_target(pipe, sf, &color,
758 box->x, box->y,
759 box->width, box->height, false);
760 } else {
761 /* Software fallback - just for R9G9B9E5_FLOAT */
762 util_clear_render_target(pipe, sf, &color,
763 box->x, box->y,
764 box->width, box->height);
765 }
766 }
767 pipe_surface_reference(&sf, NULL);
768 }
769
770 void si_init_clear_functions(struct si_context *sctx)
771 {
772 sctx->b.clear = si_clear;
773 sctx->b.clear_render_target = si_clear_render_target;
774 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
775 sctx->b.clear_texture = si_clear_texture;
776 }