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radeonsi/gfx10: fix intensity formats
[mesa.git] / src / gallium / drivers / radeonsi / si_clear.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27
28 #include "util/u_format.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
34 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
35 };
36
37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
38 struct si_texture *tex)
39 {
40 /* CMASK for MSAA is allocated in advance or always disabled
41 * by "nofmask" option.
42 */
43 if (tex->cmask_buffer || !tex->surface.cmask_size ||
44 tex->buffer.b.b.nr_samples >= 2)
45 return;
46
47 tex->cmask_buffer =
48 si_aligned_buffer_create(&sscreen->b,
49 SI_RESOURCE_FLAG_UNMAPPABLE,
50 PIPE_USAGE_DEFAULT,
51 tex->surface.cmask_size,
52 tex->surface.cmask_alignment);
53 if (tex->cmask_buffer == NULL)
54 return;
55
56 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
57 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
58
59 p_atomic_inc(&sscreen->compressed_colortex_counter);
60 }
61
62 static bool si_set_clear_color(struct si_texture *tex,
63 enum pipe_format surface_format,
64 const union pipe_color_union *color)
65 {
66 union util_color uc;
67
68 memset(&uc, 0, sizeof(uc));
69
70 if (tex->surface.bpe == 16) {
71 /* DCC fast clear only:
72 * CLEAR_WORD0 = R = G = B
73 * CLEAR_WORD1 = A
74 */
75 assert(color->ui[0] == color->ui[1] &&
76 color->ui[0] == color->ui[2]);
77 uc.ui[0] = color->ui[0];
78 uc.ui[1] = color->ui[3];
79 } else if (util_format_is_pure_uint(surface_format)) {
80 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
81 } else if (util_format_is_pure_sint(surface_format)) {
82 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
83 } else {
84 util_pack_color(color->f, surface_format, &uc);
85 }
86
87 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
88 return false;
89
90 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
91 return true;
92 }
93
94 /** Linearize and convert luminace/intensity to red. */
95 enum pipe_format si_simplify_cb_format(enum pipe_format format)
96 {
97 format = util_format_linear(format);
98 format = util_format_luminance_to_red(format);
99 return util_format_intensity_to_red(format);
100 }
101
102 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
103 {
104 format = si_simplify_cb_format(format);
105 const struct util_format_description *desc = util_format_description(format);
106
107 /* Formats with 3 channels can't have alpha. */
108 if (desc->nr_channels == 3)
109 return true; /* same as xxxA; is any value OK here? */
110
111 if (sscreen->info.chip_class >= GFX10 && desc->nr_channels == 1)
112 return desc->swizzle[3] == PIPE_SWIZZLE_X;
113
114 return si_translate_colorswap(format, false) <= 1;
115 }
116
117 static bool vi_get_fast_clear_parameters(struct si_screen *sscreen,
118 enum pipe_format base_format,
119 enum pipe_format surface_format,
120 const union pipe_color_union *color,
121 uint32_t* clear_value,
122 bool *eliminate_needed)
123 {
124 /* If we want to clear without needing a fast clear eliminate step, we
125 * can set color and alpha independently to 0 or 1 (or 0/max for integer
126 * formats).
127 */
128 bool values[4] = {}; /* whether to clear to 0 or 1 */
129 bool color_value = false; /* clear color to 0 or 1 */
130 bool alpha_value = false; /* clear alpha to 0 or 1 */
131 int alpha_channel; /* index of the alpha component */
132 bool has_color = false;
133 bool has_alpha = false;
134
135 const struct util_format_description *desc =
136 util_format_description(si_simplify_cb_format(surface_format));
137
138 /* 128-bit fast clear with different R,G,B values is unsupported. */
139 if (desc->block.bits == 128 &&
140 (color->ui[0] != color->ui[1] ||
141 color->ui[0] != color->ui[2]))
142 return false;
143
144 *eliminate_needed = true;
145 *clear_value = DCC_CLEAR_COLOR_REG;
146
147 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
148 return true; /* need ELIMINATE_FAST_CLEAR */
149
150 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format);
151 bool surf_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, surface_format);
152
153 /* Formats with 3 channels can't have alpha. */
154 if (desc->nr_channels == 3)
155 alpha_channel = -1;
156 else if (surf_alpha_is_on_msb)
157 alpha_channel = desc->nr_channels - 1;
158 else
159 alpha_channel = 0;
160
161 for (int i = 0; i < 4; ++i) {
162 if (desc->swizzle[i] >= PIPE_SWIZZLE_0)
163 continue;
164
165 if (desc->channel[i].pure_integer &&
166 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
167 /* Use the maximum value for clamping the clear color. */
168 int max = u_bit_consecutive(0, desc->channel[i].size - 1);
169
170 values[i] = color->i[i] != 0;
171 if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
172 return true; /* need ELIMINATE_FAST_CLEAR */
173 } else if (desc->channel[i].pure_integer &&
174 desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
175 /* Use the maximum value for clamping the clear color. */
176 unsigned max = u_bit_consecutive(0, desc->channel[i].size);
177
178 values[i] = color->ui[i] != 0U;
179 if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
180 return true; /* need ELIMINATE_FAST_CLEAR */
181 } else {
182 values[i] = color->f[i] != 0.0F;
183 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
184 return true; /* need ELIMINATE_FAST_CLEAR */
185 }
186
187 if (desc->swizzle[i] == alpha_channel) {
188 alpha_value = values[i];
189 has_alpha = true;
190 } else {
191 color_value = values[i];
192 has_color = true;
193 }
194 }
195
196 /* If alpha isn't present, make it the same as color, and vice versa. */
197 if (!has_alpha)
198 alpha_value = color_value;
199 else if (!has_color)
200 color_value = alpha_value;
201
202 if (color_value != alpha_value &&
203 base_alpha_is_on_msb != surf_alpha_is_on_msb)
204 return true; /* require ELIMINATE_FAST_CLEAR */
205
206 /* Check if all color values are equal if they are present. */
207 for (int i = 0; i < 4; ++i) {
208 if (desc->swizzle[i] <= PIPE_SWIZZLE_W &&
209 desc->swizzle[i] != alpha_channel &&
210 values[i] != color_value)
211 return true; /* require ELIMINATE_FAST_CLEAR */
212 }
213
214 /* This doesn't need ELIMINATE_FAST_CLEAR.
215 * On chips predating Raven2, the DCC clear codes and the CB clear
216 * color registers must match.
217 */
218 *eliminate_needed = false;
219
220 if (color_value) {
221 if (alpha_value)
222 *clear_value = DCC_CLEAR_COLOR_1111;
223 else
224 *clear_value = DCC_CLEAR_COLOR_1110;
225 } else {
226 if (alpha_value)
227 *clear_value = DCC_CLEAR_COLOR_0001;
228 else
229 *clear_value = DCC_CLEAR_COLOR_0000;
230 }
231 return true;
232 }
233
234 void vi_dcc_clear_level(struct si_context *sctx,
235 struct si_texture *tex,
236 unsigned level, unsigned clear_value)
237 {
238 struct pipe_resource *dcc_buffer;
239 uint64_t dcc_offset, clear_size;
240
241 assert(vi_dcc_enabled(tex, level));
242
243 if (tex->dcc_separate_buffer) {
244 dcc_buffer = &tex->dcc_separate_buffer->b.b;
245 dcc_offset = 0;
246 } else {
247 dcc_buffer = &tex->buffer.b.b;
248 dcc_offset = tex->dcc_offset;
249 }
250
251 if (sctx->chip_class >= GFX9) {
252 /* Mipmap level clears aren't implemented. */
253 assert(tex->buffer.b.b.last_level == 0);
254 /* 4x and 8x MSAA needs a sophisticated compute shader for
255 * the clear. See AMDVLK. */
256 assert(tex->buffer.b.b.nr_storage_samples <= 2);
257 clear_size = tex->surface.dcc_size;
258 } else {
259 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
260
261 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
262 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
263 /* Layered 4x and 8x MSAA DCC fast clears need to clear
264 * dcc_fast_clear_size bytes for each layer. A compute shader
265 * would be more efficient than separate per-layer clear operations.
266 */
267 assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
268
269 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
270 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
271 num_layers;
272 }
273
274 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
275 &clear_value, 4, SI_COHERENCY_CB_META, false);
276 }
277
278 /* Set the same micro tile mode as the destination of the last MSAA resolve.
279 * This allows hitting the MSAA resolve fast path, which requires that both
280 * src and dst micro tile modes match.
281 */
282 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
283 struct si_texture *tex)
284 {
285 if (sscreen->info.chip_class >= GFX10 ||
286 tex->buffer.b.is_shared ||
287 tex->buffer.b.b.nr_samples <= 1 ||
288 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
289 return;
290
291 assert(sscreen->info.chip_class >= GFX9 ||
292 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
293 assert(tex->buffer.b.b.last_level == 0);
294
295 if (sscreen->info.chip_class >= GFX9) {
296 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
297 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
298
299 /* If you do swizzle_mode % 4, you'll get:
300 * 0 = Depth
301 * 1 = Standard,
302 * 2 = Displayable
303 * 3 = Rotated
304 *
305 * Depth-sample order isn't allowed:
306 */
307 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
308
309 switch (tex->last_msaa_resolve_target_micro_mode) {
310 case RADEON_MICRO_MODE_DISPLAY:
311 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
312 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
313 break;
314 case RADEON_MICRO_MODE_THIN:
315 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
316 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
317 break;
318 case RADEON_MICRO_MODE_ROTATED:
319 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
320 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
321 break;
322 default: /* depth */
323 assert(!"unexpected micro mode");
324 return;
325 }
326 } else if (sscreen->info.chip_class >= GFX7) {
327 /* These magic numbers were copied from addrlib. It doesn't use
328 * any definitions for them either. They are all 2D_TILED_THIN1
329 * modes with different bpp and micro tile mode.
330 */
331 switch (tex->last_msaa_resolve_target_micro_mode) {
332 case RADEON_MICRO_MODE_DISPLAY:
333 tex->surface.u.legacy.tiling_index[0] = 10;
334 break;
335 case RADEON_MICRO_MODE_THIN:
336 tex->surface.u.legacy.tiling_index[0] = 14;
337 break;
338 case RADEON_MICRO_MODE_ROTATED:
339 tex->surface.u.legacy.tiling_index[0] = 28;
340 break;
341 default: /* depth, thick */
342 assert(!"unexpected micro mode");
343 return;
344 }
345 } else { /* GFX6 */
346 switch (tex->last_msaa_resolve_target_micro_mode) {
347 case RADEON_MICRO_MODE_DISPLAY:
348 switch (tex->surface.bpe) {
349 case 1:
350 tex->surface.u.legacy.tiling_index[0] = 10;
351 break;
352 case 2:
353 tex->surface.u.legacy.tiling_index[0] = 11;
354 break;
355 default: /* 4, 8 */
356 tex->surface.u.legacy.tiling_index[0] = 12;
357 break;
358 }
359 break;
360 case RADEON_MICRO_MODE_THIN:
361 switch (tex->surface.bpe) {
362 case 1:
363 tex->surface.u.legacy.tiling_index[0] = 14;
364 break;
365 case 2:
366 tex->surface.u.legacy.tiling_index[0] = 15;
367 break;
368 case 4:
369 tex->surface.u.legacy.tiling_index[0] = 16;
370 break;
371 default: /* 8, 16 */
372 tex->surface.u.legacy.tiling_index[0] = 17;
373 break;
374 }
375 break;
376 default: /* depth, thick */
377 assert(!"unexpected micro mode");
378 return;
379 }
380 }
381
382 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
383
384 p_atomic_inc(&sscreen->dirty_tex_counter);
385 }
386
387 static void si_do_fast_color_clear(struct si_context *sctx,
388 unsigned *buffers,
389 const union pipe_color_union *color)
390 {
391 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
392 int i;
393
394 /* This function is broken in BE, so just disable this path for now */
395 #ifdef PIPE_ARCH_BIG_ENDIAN
396 return;
397 #endif
398
399 if (sctx->render_cond)
400 return;
401
402 for (i = 0; i < fb->nr_cbufs; i++) {
403 struct si_texture *tex;
404 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
405
406 if (!fb->cbufs[i])
407 continue;
408
409 /* if this colorbuffer is not being cleared */
410 if (!(*buffers & clear_bit))
411 continue;
412
413 unsigned level = fb->cbufs[i]->u.tex.level;
414 if (level > 0)
415 continue;
416
417 tex = (struct si_texture *)fb->cbufs[i]->texture;
418
419 /* TODO: GFX9: Implement DCC fast clear for level 0 of
420 * mipmapped textures. Mipmapped DCC has to clear a rectangular
421 * area of DCC for level 0 (because the whole miptree is
422 * organized in a 2D plane).
423 */
424 if (sctx->chip_class >= GFX9 &&
425 tex->buffer.b.b.last_level > 0)
426 continue;
427
428 /* the clear is allowed if all layers are bound */
429 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
430 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) {
431 continue;
432 }
433
434 /* only supported on tiled surfaces */
435 if (tex->surface.is_linear) {
436 continue;
437 }
438
439 /* shared textures can't use fast clear without an explicit flush,
440 * because there is no way to communicate the clear color among
441 * all clients
442 */
443 if (tex->buffer.b.is_shared &&
444 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
445 continue;
446
447 if (sctx->chip_class <= GFX8 &&
448 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
449 !sctx->screen->info.htile_cmask_support_1d_tiling)
450 continue;
451
452 /* Use a slow clear for small surfaces where the cost of
453 * the eliminate pass can be higher than the benefit of fast
454 * clear. The closed driver does this, but the numbers may differ.
455 *
456 * This helps on both dGPUs and APUs, even small APUs like Mullins.
457 */
458 bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
459 tex->buffer.b.b.width0 *
460 tex->buffer.b.b.height0 <= 512 * 512;
461 bool eliminate_needed = false;
462 bool fmask_decompress_needed = false;
463
464 /* Fast clear is the most appropriate place to enable DCC for
465 * displayable surfaces.
466 */
467 if (sctx->family == CHIP_STONEY && !too_small) {
468 vi_separate_dcc_try_enable(sctx, tex);
469
470 /* RB+ isn't supported with a CMASK clear only on Stoney,
471 * so all clears are considered to be hypothetically slow
472 * clears, which is weighed when determining whether to
473 * enable separate DCC.
474 */
475 if (tex->dcc_gather_statistics) /* only for Stoney */
476 tex->num_slow_clears++;
477 }
478
479 /* Try to clear DCC first, otherwise try CMASK. */
480 if (vi_dcc_enabled(tex, 0)) {
481 uint32_t reset_value;
482
483 if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
484 continue;
485
486 /* This can happen with mipmapping or MSAA. */
487 if (sctx->chip_class == GFX8 &&
488 !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
489 continue;
490
491 if (!vi_get_fast_clear_parameters(sctx->screen,
492 tex->buffer.b.b.format,
493 fb->cbufs[i]->format,
494 color, &reset_value,
495 &eliminate_needed))
496 continue;
497
498 if (eliminate_needed && too_small)
499 continue;
500
501 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
502 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
503 /* TODO: This doesn't work with MSAA. */
504 if (eliminate_needed)
505 continue;
506
507 uint32_t clear_value = 0xCCCCCCCC;
508 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
509 tex->cmask_offset, tex->surface.cmask_size,
510 &clear_value, 4, SI_COHERENCY_CB_META, false);
511 fmask_decompress_needed = true;
512 }
513
514 vi_dcc_clear_level(sctx, tex, 0, reset_value);
515 tex->separate_dcc_dirty = true;
516 } else {
517 if (too_small)
518 continue;
519
520 /* 128-bit formats are unusupported */
521 if (tex->surface.bpe > 8) {
522 continue;
523 }
524
525 /* RB+ doesn't work with CMASK fast clear on Stoney. */
526 if (sctx->family == CHIP_STONEY)
527 continue;
528
529 /* ensure CMASK is enabled */
530 si_alloc_separate_cmask(sctx->screen, tex);
531 if (!tex->cmask_buffer)
532 continue;
533
534 /* Do the fast clear. */
535 uint32_t clear_value = 0;
536 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
537 tex->cmask_offset, tex->surface.cmask_size,
538 &clear_value, 4, SI_COHERENCY_CB_META, false);
539 eliminate_needed = true;
540 }
541
542 if ((eliminate_needed || fmask_decompress_needed) &&
543 !(tex->dirty_level_mask & (1 << level))) {
544 tex->dirty_level_mask |= 1 << level;
545 p_atomic_inc(&sctx->screen->compressed_colortex_counter);
546 }
547
548 /* We can change the micro tile mode before a full clear. */
549 si_set_optimal_micro_tile_mode(sctx->screen, tex);
550
551 *buffers &= ~clear_bit;
552
553 /* Chips with DCC constant encoding don't need to set the clear
554 * color registers for DCC clear values 0 and 1.
555 */
556 if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
557 continue;
558
559 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
560 sctx->framebuffer.dirty_cbufs |= 1 << i;
561 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
562 }
563 }
564 }
565
566 static void si_clear(struct pipe_context *ctx, unsigned buffers,
567 const union pipe_color_union *color,
568 double depth, unsigned stencil)
569 {
570 struct si_context *sctx = (struct si_context *)ctx;
571 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
572 struct pipe_surface *zsbuf = fb->zsbuf;
573 struct si_texture *zstex =
574 zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
575
576 if (buffers & PIPE_CLEAR_COLOR) {
577 si_do_fast_color_clear(sctx, &buffers, color);
578 if (!buffers)
579 return; /* all buffers have been fast cleared */
580
581 /* These buffers cannot use fast clear, make sure to disable expansion. */
582 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
583 struct si_texture *tex;
584
585 /* If not clearing this buffer, skip. */
586 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
587 continue;
588
589 tex = (struct si_texture *)fb->cbufs[i]->texture;
590 if (tex->surface.fmask_size == 0)
591 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
592 }
593 }
594
595 if (zstex &&
596 si_htile_enabled(zstex, zsbuf->u.tex.level) &&
597 zsbuf->u.tex.first_layer == 0 &&
598 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
599 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
600 if (buffers & PIPE_CLEAR_DEPTH &&
601 (!zstex->tc_compatible_htile ||
602 depth == 0 || depth == 1)) {
603 /* Need to disable EXPCLEAR temporarily if clearing
604 * to a new value. */
605 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
606 sctx->db_depth_disable_expclear = true;
607 }
608
609 if (zstex->depth_clear_value != (float)depth) {
610 /* Update DB_DEPTH_CLEAR. */
611 zstex->depth_clear_value = depth;
612 sctx->framebuffer.dirty_zsbuf = true;
613 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
614 }
615 sctx->db_depth_clear = true;
616 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
617 }
618
619 /* TC-compatible HTILE only supports stencil clears to 0. */
620 if (buffers & PIPE_CLEAR_STENCIL &&
621 (!zstex->tc_compatible_htile || stencil == 0)) {
622 stencil &= 0xff;
623
624 /* Need to disable EXPCLEAR temporarily if clearing
625 * to a new value. */
626 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
627 sctx->db_stencil_disable_expclear = true;
628 }
629
630 if (zstex->stencil_clear_value != (uint8_t)stencil) {
631 /* Update DB_STENCIL_CLEAR. */
632 zstex->stencil_clear_value = stencil;
633 sctx->framebuffer.dirty_zsbuf = true;
634 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
635 }
636 sctx->db_stencil_clear = true;
637 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
638 }
639
640 /* TODO: Find out what's wrong here. Fast depth clear leads to
641 * corruption in ARK: Survival Evolved, but that may just be
642 * a coincidence and the root cause is elsewhere.
643 *
644 * The corruption can be fixed by putting the DB flush before
645 * or after the depth clear. (surprisingly)
646 *
647 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
648 *
649 * This hack decreases back-to-back ClearDepth performance.
650 */
651 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
652 sctx->screen->options.clear_db_cache_before_clear)
653 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
654 }
655
656 si_blitter_begin(sctx, SI_CLEAR);
657 util_blitter_clear(sctx->blitter, fb->width, fb->height,
658 util_framebuffer_get_num_layers(fb),
659 buffers, color, depth, stencil);
660 si_blitter_end(sctx);
661
662 if (sctx->db_depth_clear) {
663 sctx->db_depth_clear = false;
664 sctx->db_depth_disable_expclear = false;
665 zstex->depth_cleared = true;
666 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
667 }
668
669 if (sctx->db_stencil_clear) {
670 sctx->db_stencil_clear = false;
671 sctx->db_stencil_disable_expclear = false;
672 zstex->stencil_cleared = true;
673 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
674 }
675 }
676
677 static void si_clear_render_target(struct pipe_context *ctx,
678 struct pipe_surface *dst,
679 const union pipe_color_union *color,
680 unsigned dstx, unsigned dsty,
681 unsigned width, unsigned height,
682 bool render_condition_enabled)
683 {
684 struct si_context *sctx = (struct si_context *)ctx;
685 struct si_texture *sdst = (struct si_texture*)dst->texture;
686
687 if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
688 si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
689 height, render_condition_enabled);
690 return;
691 }
692
693 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
694 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
695 util_blitter_clear_render_target(sctx->blitter, dst, color,
696 dstx, dsty, width, height);
697 si_blitter_end(sctx);
698 }
699
700 static void si_clear_depth_stencil(struct pipe_context *ctx,
701 struct pipe_surface *dst,
702 unsigned clear_flags,
703 double depth,
704 unsigned stencil,
705 unsigned dstx, unsigned dsty,
706 unsigned width, unsigned height,
707 bool render_condition_enabled)
708 {
709 struct si_context *sctx = (struct si_context *)ctx;
710
711 si_blitter_begin(sctx, SI_CLEAR_SURFACE |
712 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
713 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
714 dstx, dsty, width, height);
715 si_blitter_end(sctx);
716 }
717
718 static void si_clear_texture(struct pipe_context *pipe,
719 struct pipe_resource *tex,
720 unsigned level,
721 const struct pipe_box *box,
722 const void *data)
723 {
724 struct pipe_screen *screen = pipe->screen;
725 struct si_texture *stex = (struct si_texture*)tex;
726 struct pipe_surface tmpl = {{0}};
727 struct pipe_surface *sf;
728 const struct util_format_description *desc =
729 util_format_description(tex->format);
730
731 tmpl.format = tex->format;
732 tmpl.u.tex.first_layer = box->z;
733 tmpl.u.tex.last_layer = box->z + box->depth - 1;
734 tmpl.u.tex.level = level;
735 sf = pipe->create_surface(pipe, tex, &tmpl);
736 if (!sf)
737 return;
738
739 if (stex->is_depth) {
740 unsigned clear;
741 float depth;
742 uint8_t stencil = 0;
743
744 /* Depth is always present. */
745 clear = PIPE_CLEAR_DEPTH;
746 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
747
748 if (stex->surface.has_stencil) {
749 clear |= PIPE_CLEAR_STENCIL;
750 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
751 }
752
753 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
754 box->x, box->y,
755 box->width, box->height, false);
756 } else {
757 union pipe_color_union color;
758
759 /* pipe_color_union requires the full vec4 representation. */
760 if (util_format_is_pure_uint(tex->format))
761 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
762 else if (util_format_is_pure_sint(tex->format))
763 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
764 else
765 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
766
767 if (screen->is_format_supported(screen, tex->format,
768 tex->target, 0, 0,
769 PIPE_BIND_RENDER_TARGET)) {
770 si_clear_render_target(pipe, sf, &color,
771 box->x, box->y,
772 box->width, box->height, false);
773 } else {
774 /* Software fallback - just for R9G9B9E5_FLOAT */
775 util_clear_render_target(pipe, sf, &color,
776 box->x, box->y,
777 box->width, box->height);
778 }
779 }
780 pipe_surface_reference(&sf, NULL);
781 }
782
783 void si_init_clear_functions(struct si_context *sctx)
784 {
785 sctx->b.clear_render_target = si_clear_render_target;
786 sctx->b.clear_texture = si_clear_texture;
787
788 if (sctx->has_graphics) {
789 sctx->b.clear = si_clear;
790 sctx->b.clear_depth_stencil = si_clear_depth_stencil;
791 }
792 }