src/gallium/drivers/radeonsi/si_clear.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27
  28 #include "util/u_format.h"
  29 #include "util/u_pack_color.h"
  30 #include "util/u_surface.h"
  31
  32 enum {
  33         SI_CLEAR         = SI_SAVE_FRAGMENT_STATE,
  34         SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
  35 };
  36
  37 static void si_alloc_separate_cmask(struct si_screen *sscreen,
  38                                     struct r600_texture *rtex)
  39 {
  40         if (rtex->cmask_buffer)
  41                 return;
  42
  43         assert(rtex->cmask.size == 0);
  44
  45         si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
  46         if (!rtex->cmask.size)
  47                 return;
  48
  49         rtex->cmask_buffer = (struct r600_resource *)
  50                 si_aligned_buffer_create(&sscreen->b,
  51                                          SI_RESOURCE_FLAG_UNMAPPABLE,
  52                                          PIPE_USAGE_DEFAULT,
  53                                          rtex->cmask.size,
  54                                          rtex->cmask.alignment);
  55         if (rtex->cmask_buffer == NULL) {
  56                 rtex->cmask.size = 0;
  57                 return;
  58         }
  59
  60         /* update colorbuffer state bits */
  61         rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
  62
  63         rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
  64
  65         p_atomic_inc(&sscreen->compressed_colortex_counter);
  66 }
  67
  68 static void si_set_clear_color(struct r600_texture *rtex,
  69                                enum pipe_format surface_format,
  70                                const union pipe_color_union *color)
  71 {
  72         union util_color uc;
  73
  74         memset(&uc, 0, sizeof(uc));
  75
  76         if (rtex->surface.bpe == 16) {
  77                 /* DCC fast clear only:
  78                  *   CLEAR_WORD0 = R = G = B
  79                  *   CLEAR_WORD1 = A
  80                  */
  81                 assert(color->ui[0] == color->ui[1] &&
  82                        color->ui[0] == color->ui[2]);
  83                 uc.ui[0] = color->ui[0];
  84                 uc.ui[1] = color->ui[3];
  85         } else if (util_format_is_pure_uint(surface_format)) {
  86                 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
  87         } else if (util_format_is_pure_sint(surface_format)) {
  88                 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
  89         } else {
  90                 util_pack_color(color->f, surface_format, &uc);
  91         }
  92
  93         memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
  94 }
  95
  96 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format,
  97                                          const union pipe_color_union *color,
  98                                          uint32_t* clear_value,
  99                                          bool *eliminate_needed)
 100 {
 101         /* If we want to clear without needing a fast clear eliminate step, we
 102          * can set color and alpha independently to 0 or 1 (or 0/max for integer
 103          * formats).
 104          */
 105         bool values[4] = {}; /* whether to clear to 0 or 1 */
 106         int i;
 107         bool color_value = false; /* clear color to 0 or 1 */
 108         bool alpha_value = false; /* clear alpha to 0 or 1 */
 109         int alpha_channel; /* index of the alpha component */
 110
 111         /* Convert luminance to red. (the latter can't handle L8_SRGB,
 112          * so convert to linear) */
 113         surface_format = util_format_linear(surface_format);
 114         surface_format = util_format_luminance_to_red(surface_format);
 115
 116         const struct util_format_description *desc = util_format_description(surface_format);
 117
 118         /* 128-bit fast clear with different R,G,B values is unsupported. */
 119         if (desc->block.bits == 128 &&
 120             (color->ui[0] != color->ui[1] ||
 121              color->ui[0] != color->ui[2]))
 122                 return false;
 123
 124         *eliminate_needed = true;
 125         *clear_value = 0x20202020U; /* use CB clear color registers */
 126
 127         if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
 128             surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
 129             surface_format == PIPE_FORMAT_B5G6R5_SRGB ||
 130             util_format_is_alpha(surface_format)) {
 131                 alpha_channel = -1;
 132         } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
 133                 if (si_translate_colorswap(surface_format, false) <= 1)
 134                         alpha_channel = desc->nr_channels - 1;
 135                 else
 136                         alpha_channel = 0;
 137         } else
 138                 return true; /* need ELIMINATE_FAST_CLEAR */
 139
 140         for (i = 0; i < 4; ++i) {
 141                 int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
 142
 143                 if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
 144                     desc->swizzle[i] > PIPE_SWIZZLE_W)
 145                         continue;
 146
 147                 if (desc->channel[i].pure_integer &&
 148                     desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 149                         /* Use the maximum value for clamping the clear color. */
 150                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
 151
 152                         values[i] = color->i[i] != 0;
 153                         if (color->i[i] != 0 && MIN2(color->i[i], max) != max)
 154                                 return true; /* need ELIMINATE_FAST_CLEAR */
 155                 } else if (desc->channel[i].pure_integer &&
 156                            desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
 157                         /* Use the maximum value for clamping the clear color. */
 158                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
 159
 160                         values[i] = color->ui[i] != 0U;
 161                         if (color->ui[i] != 0U && MIN2(color->ui[i], max) != max)
 162                                 return true; /* need ELIMINATE_FAST_CLEAR */
 163                 } else {
 164                         values[i] = color->f[i] != 0.0F;
 165                         if (color->f[i] != 0.0F && color->f[i] != 1.0F)
 166                                 return true; /* need ELIMINATE_FAST_CLEAR */
 167                 }
 168
 169                 if (index == alpha_channel)
 170                         alpha_value = values[i];
 171                 else
 172                         color_value = values[i];
 173         }
 174
 175         for (int i = 0; i < 4; ++i)
 176                 if (values[i] != color_value &&
 177                     desc->swizzle[i] - PIPE_SWIZZLE_X != alpha_channel &&
 178                     desc->swizzle[i] >= PIPE_SWIZZLE_X &&
 179                     desc->swizzle[i] <= PIPE_SWIZZLE_W)
 180                         return true; /* need ELIMINATE_FAST_CLEAR */
 181
 182         /* This doesn't need ELIMINATE_FAST_CLEAR.
 183          * CB uses both the DCC clear codes and the CB clear color registers,
 184          * so they must match.
 185          */
 186         *eliminate_needed = false;
 187
 188         if (color_value)
 189                 *clear_value |= 0x80808080U;
 190         if (alpha_value)
 191                 *clear_value |= 0x40404040U;
 192         return true;
 193 }
 194
 195 void vi_dcc_clear_level(struct si_context *sctx,
 196                         struct r600_texture *rtex,
 197                         unsigned level, unsigned clear_value)
 198 {
 199         struct pipe_resource *dcc_buffer;
 200         uint64_t dcc_offset, clear_size;
 201
 202         assert(vi_dcc_enabled(rtex, level));
 203
 204         if (rtex->dcc_separate_buffer) {
 205                 dcc_buffer = &rtex->dcc_separate_buffer->b.b;
 206                 dcc_offset = 0;
 207         } else {
 208                 dcc_buffer = &rtex->resource.b.b;
 209                 dcc_offset = rtex->dcc_offset;
 210         }
 211
 212         if (sctx->chip_class >= GFX9) {
 213                 /* Mipmap level clears aren't implemented. */
 214                 assert(rtex->resource.b.b.last_level == 0);
 215                 /* 4x and 8x MSAA needs a sophisticated compute shader for
 216                  * the clear. See AMDVLK. */
 217                 assert(rtex->resource.b.b.nr_samples <= 2);
 218                 clear_size = rtex->surface.dcc_size;
 219         } else {
 220                 unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
 221
 222                 /* If this is 0, fast clear isn't possible. (can occur with MSAA) */
 223                 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
 224                 /* Layered 4x and 8x MSAA DCC fast clears need to clear
 225                  * dcc_fast_clear_size bytes for each layer. A compute shader
 226                  * would be more efficient than separate per-layer clear operations.
 227                  */
 228                 assert(rtex->resource.b.b.nr_samples <= 2 || num_layers == 1);
 229
 230                 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
 231                 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
 232                              num_layers;
 233         }
 234
 235         si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
 236                         clear_value, SI_COHERENCY_CB_META);
 237 }
 238
 239 /* Set the same micro tile mode as the destination of the last MSAA resolve.
 240  * This allows hitting the MSAA resolve fast path, which requires that both
 241  * src and dst micro tile modes match.
 242  */
 243 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
 244                                            struct r600_texture *rtex)
 245 {
 246         if (rtex->resource.b.is_shared ||
 247             rtex->resource.b.b.nr_samples <= 1 ||
 248             rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
 249                 return;
 250
 251         assert(sscreen->info.chip_class >= GFX9 ||
 252                rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
 253         assert(rtex->resource.b.b.last_level == 0);
 254
 255         if (sscreen->info.chip_class >= GFX9) {
 256                 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
 257                 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
 258
 259                 /* If you do swizzle_mode % 4, you'll get:
 260                  *   0 = Depth
 261                  *   1 = Standard,
 262                  *   2 = Displayable
 263                  *   3 = Rotated
 264                  *
 265                  * Depth-sample order isn't allowed:
 266                  */
 267                 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
 268
 269                 switch (rtex->last_msaa_resolve_target_micro_mode) {
 270                 case RADEON_MICRO_MODE_DISPLAY:
 271                         rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
 272                         rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
 273                         break;
 274                 case RADEON_MICRO_MODE_THIN:
 275                         rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
 276                         rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
 277                         break;
 278                 case RADEON_MICRO_MODE_ROTATED:
 279                         rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
 280                         rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
 281                         break;
 282                 default: /* depth */
 283                         assert(!"unexpected micro mode");
 284                         return;
 285                 }
 286         } else if (sscreen->info.chip_class >= CIK) {
 287                 /* These magic numbers were copied from addrlib. It doesn't use
 288                  * any definitions for them either. They are all 2D_TILED_THIN1
 289                  * modes with different bpp and micro tile mode.
 290                  */
 291                 switch (rtex->last_msaa_resolve_target_micro_mode) {
 292                 case RADEON_MICRO_MODE_DISPLAY:
 293                         rtex->surface.u.legacy.tiling_index[0] = 10;
 294                         break;
 295                 case RADEON_MICRO_MODE_THIN:
 296                         rtex->surface.u.legacy.tiling_index[0] = 14;
 297                         break;
 298                 case RADEON_MICRO_MODE_ROTATED:
 299                         rtex->surface.u.legacy.tiling_index[0] = 28;
 300                         break;
 301                 default: /* depth, thick */
 302                         assert(!"unexpected micro mode");
 303                         return;
 304                 }
 305         } else { /* SI */
 306                 switch (rtex->last_msaa_resolve_target_micro_mode) {
 307                 case RADEON_MICRO_MODE_DISPLAY:
 308                         switch (rtex->surface.bpe) {
 309                         case 1:
 310                             rtex->surface.u.legacy.tiling_index[0] = 10;
 311                             break;
 312                         case 2:
 313                             rtex->surface.u.legacy.tiling_index[0] = 11;
 314                             break;
 315                         default: /* 4, 8 */
 316                             rtex->surface.u.legacy.tiling_index[0] = 12;
 317                             break;
 318                         }
 319                         break;
 320                 case RADEON_MICRO_MODE_THIN:
 321                         switch (rtex->surface.bpe) {
 322                         case 1:
 323                                 rtex->surface.u.legacy.tiling_index[0] = 14;
 324                                 break;
 325                         case 2:
 326                                 rtex->surface.u.legacy.tiling_index[0] = 15;
 327                                 break;
 328                         case 4:
 329                                 rtex->surface.u.legacy.tiling_index[0] = 16;
 330                                 break;
 331                         default: /* 8, 16 */
 332                                 rtex->surface.u.legacy.tiling_index[0] = 17;
 333                                 break;
 334                         }
 335                         break;
 336                 default: /* depth, thick */
 337                         assert(!"unexpected micro mode");
 338                         return;
 339                 }
 340         }
 341
 342         rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
 343
 344         p_atomic_inc(&sscreen->dirty_tex_counter);
 345 }
 346
 347 static void si_do_fast_color_clear(struct si_context *sctx,
 348                                    unsigned *buffers,
 349                                    const union pipe_color_union *color)
 350 {
 351         struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
 352         int i;
 353
 354         /* This function is broken in BE, so just disable this path for now */
 355 #ifdef PIPE_ARCH_BIG_ENDIAN
 356         return;
 357 #endif
 358
 359         if (sctx->render_cond)
 360                 return;
 361
 362         for (i = 0; i < fb->nr_cbufs; i++) {
 363                 struct r600_texture *tex;
 364                 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
 365
 366                 if (!fb->cbufs[i])
 367                         continue;
 368
 369                 /* if this colorbuffer is not being cleared */
 370                 if (!(*buffers & clear_bit))
 371                         continue;
 372
 373                 unsigned level = fb->cbufs[i]->u.tex.level;
 374                 if (level > 0)
 375                         continue;
 376
 377                 tex = (struct r600_texture *)fb->cbufs[i]->texture;
 378
 379                 /* TODO: GFX9: Implement DCC fast clear for level 0 of
 380                  * mipmapped textures. Mipmapped DCC has to clear a rectangular
 381                  * area of DCC for level 0 (because the whole miptree is
 382                  * organized in a 2D plane).
 383                  */
 384                 if (sctx->chip_class >= GFX9 &&
 385                     tex->resource.b.b.last_level > 0)
 386                         continue;
 387
 388                 /* the clear is allowed if all layers are bound */
 389                 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
 390                     fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
 391                         continue;
 392                 }
 393
 394                 /* only supported on tiled surfaces */
 395                 if (tex->surface.is_linear) {
 396                         continue;
 397                 }
 398
 399                 /* shared textures can't use fast clear without an explicit flush,
 400                  * because there is no way to communicate the clear color among
 401                  * all clients
 402                  */
 403                 if (tex->resource.b.is_shared &&
 404                     !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
 405                         continue;
 406
 407                 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
 408                 if (sctx->chip_class == CIK &&
 409                     tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
 410                     sctx->screen->info.drm_major == 2 &&
 411                     sctx->screen->info.drm_minor < 38) {
 412                         continue;
 413                 }
 414
 415                 /* Fast clear is the most appropriate place to enable DCC for
 416                  * displayable surfaces.
 417                  */
 418                 if (sctx->chip_class >= VI &&
 419                     !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) {
 420                         vi_separate_dcc_try_enable(sctx, tex);
 421
 422                         /* RB+ isn't supported with a CMASK clear only on Stoney,
 423                          * so all clears are considered to be hypothetically slow
 424                          * clears, which is weighed when determining whether to
 425                          * enable separate DCC.
 426                          */
 427                         if (tex->dcc_gather_statistics &&
 428                             sctx->family == CHIP_STONEY)
 429                                 tex->num_slow_clears++;
 430                 }
 431
 432                 bool need_decompress_pass = false;
 433
 434                 /* Use a slow clear for small surfaces where the cost of
 435                  * the eliminate pass can be higher than the benefit of fast
 436                  * clear. The closed driver does this, but the numbers may differ.
 437                  *
 438                  * This helps on both dGPUs and APUs, even small APUs like Mullins.
 439                  */
 440                 bool too_small = tex->resource.b.b.nr_samples <= 1 &&
 441                                  tex->resource.b.b.width0 *
 442                                  tex->resource.b.b.height0 <= 512 * 512;
 443
 444                 /* Try to clear DCC first, otherwise try CMASK. */
 445                 if (vi_dcc_enabled(tex, 0)) {
 446                         uint32_t reset_value;
 447                         bool eliminate_needed;
 448
 449                         if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
 450                                 continue;
 451
 452                         /* This can only occur with MSAA. */
 453                         if (sctx->chip_class == VI &&
 454                             !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
 455                                 continue;
 456
 457                         if (!vi_get_fast_clear_parameters(fb->cbufs[i]->format,
 458                                                           color, &reset_value,
 459                                                           &eliminate_needed))
 460                                 continue;
 461
 462                         if (eliminate_needed && too_small)
 463                                 continue;
 464
 465                         /* DCC fast clear with MSAA should clear CMASK to 0xC. */
 466                         if (tex->resource.b.b.nr_samples >= 2 && tex->cmask.size) {
 467                                 /* TODO: This doesn't work with MSAA. */
 468                                 if (eliminate_needed)
 469                                         continue;
 470
 471                                 si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
 472                                                 tex->cmask.offset, tex->cmask.size,
 473                                                 0xCCCCCCCC, SI_COHERENCY_CB_META);
 474                                 need_decompress_pass = true;
 475                         }
 476
 477                         vi_dcc_clear_level(sctx, tex, 0, reset_value);
 478
 479                         if (eliminate_needed)
 480                                 need_decompress_pass = true;
 481
 482                         tex->separate_dcc_dirty = true;
 483                 } else {
 484                         if (too_small)
 485                                 continue;
 486
 487                         /* 128-bit formats are unusupported */
 488                         if (tex->surface.bpe > 8) {
 489                                 continue;
 490                         }
 491
 492                         /* RB+ doesn't work with CMASK fast clear on Stoney. */
 493                         if (sctx->family == CHIP_STONEY)
 494                                 continue;
 495
 496                         /* ensure CMASK is enabled */
 497                         si_alloc_separate_cmask(sctx->screen, tex);
 498                         if (tex->cmask.size == 0) {
 499                                 continue;
 500                         }
 501
 502                         /* Do the fast clear. */
 503                         si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
 504                                         tex->cmask.offset, tex->cmask.size, 0,
 505                                         SI_COHERENCY_CB_META);
 506                         need_decompress_pass = true;
 507                 }
 508
 509                 if (need_decompress_pass &&
 510                     !(tex->dirty_level_mask & (1 << level))) {
 511                         tex->dirty_level_mask |= 1 << level;
 512                         p_atomic_inc(&sctx->screen->compressed_colortex_counter);
 513                 }
 514
 515                 /* We can change the micro tile mode before a full clear. */
 516                 si_set_optimal_micro_tile_mode(sctx->screen, tex);
 517
 518                 si_set_clear_color(tex, fb->cbufs[i]->format, color);
 519
 520                 sctx->framebuffer.dirty_cbufs |= 1 << i;
 521                 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
 522                 *buffers &= ~clear_bit;
 523         }
 524 }
 525
 526 static void si_clear(struct pipe_context *ctx, unsigned buffers,
 527                      const union pipe_color_union *color,
 528                      double depth, unsigned stencil)
 529 {
 530         struct si_context *sctx = (struct si_context *)ctx;
 531         struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
 532         struct pipe_surface *zsbuf = fb->zsbuf;
 533         struct r600_texture *zstex =
 534                 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
 535
 536         if (buffers & PIPE_CLEAR_COLOR) {
 537                 si_do_fast_color_clear(sctx, &buffers, color);
 538                 if (!buffers)
 539                         return; /* all buffers have been fast cleared */
 540
 541                 /* These buffers cannot use fast clear, make sure to disable expansion. */
 542                 for (unsigned i = 0; i < fb->nr_cbufs; i++) {
 543                         struct r600_texture *tex;
 544
 545                         /* If not clearing this buffer, skip. */
 546                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
 547                                 continue;
 548
 549                         tex = (struct r600_texture *)fb->cbufs[i]->texture;
 550                         if (tex->fmask.size == 0)
 551                                 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
 552                 }
 553         }
 554
 555         if (zstex &&
 556             si_htile_enabled(zstex, zsbuf->u.tex.level) &&
 557             zsbuf->u.tex.first_layer == 0 &&
 558             zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
 559                 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
 560                 if (buffers & PIPE_CLEAR_DEPTH &&
 561                     (!zstex->tc_compatible_htile ||
 562                      depth == 0 || depth == 1)) {
 563                         /* Need to disable EXPCLEAR temporarily if clearing
 564                          * to a new value. */
 565                         if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
 566                                 sctx->db_depth_disable_expclear = true;
 567                         }
 568
 569                         zstex->depth_clear_value = depth;
 570                         sctx->framebuffer.dirty_zsbuf = true;
 571                         si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
 572                         sctx->db_depth_clear = true;
 573                         si_mark_atom_dirty(sctx, &sctx->db_render_state);
 574                 }
 575
 576                 /* TC-compatible HTILE only supports stencil clears to 0. */
 577                 if (buffers & PIPE_CLEAR_STENCIL &&
 578                     (!zstex->tc_compatible_htile || stencil == 0)) {
 579                         stencil &= 0xff;
 580
 581                         /* Need to disable EXPCLEAR temporarily if clearing
 582                          * to a new value. */
 583                         if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
 584                                 sctx->db_stencil_disable_expclear = true;
 585                         }
 586
 587                         zstex->stencil_clear_value = stencil;
 588                         sctx->framebuffer.dirty_zsbuf = true;
 589                         si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
 590                         sctx->db_stencil_clear = true;
 591                         si_mark_atom_dirty(sctx, &sctx->db_render_state);
 592                 }
 593
 594                 /* TODO: Find out what's wrong here. Fast depth clear leads to
 595                  * corruption in ARK: Survival Evolved, but that may just be
 596                  * a coincidence and the root cause is elsewhere.
 597                  *
 598                  * The corruption can be fixed by putting the DB flush before
 599                  * or after the depth clear. (surprisingly)
 600                  *
 601                  * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
 602                  *
 603                  * This hack decreases back-to-back ClearDepth performance.
 604                  */
 605                 if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
 606                     sctx->screen->clear_db_cache_before_clear)
 607                         sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
 608         }
 609
 610         si_blitter_begin(sctx, SI_CLEAR);
 611         util_blitter_clear(sctx->blitter, fb->width, fb->height,
 612                            util_framebuffer_get_num_layers(fb),
 613                            buffers, color, depth, stencil);
 614         si_blitter_end(sctx);
 615
 616         if (sctx->db_depth_clear) {
 617                 sctx->db_depth_clear = false;
 618                 sctx->db_depth_disable_expclear = false;
 619                 zstex->depth_cleared = true;
 620                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
 621         }
 622
 623         if (sctx->db_stencil_clear) {
 624                 sctx->db_stencil_clear = false;
 625                 sctx->db_stencil_disable_expclear = false;
 626                 zstex->stencil_cleared = true;
 627                 si_mark_atom_dirty(sctx, &sctx->db_render_state);
 628         }
 629 }
 630
 631 static void si_clear_render_target(struct pipe_context *ctx,
 632                                    struct pipe_surface *dst,
 633                                    const union pipe_color_union *color,
 634                                    unsigned dstx, unsigned dsty,
 635                                    unsigned width, unsigned height,
 636                                    bool render_condition_enabled)
 637 {
 638         struct si_context *sctx = (struct si_context *)ctx;
 639
 640         si_blitter_begin(sctx, SI_CLEAR_SURFACE |
 641                          (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
 642         util_blitter_clear_render_target(sctx->blitter, dst, color,
 643                                          dstx, dsty, width, height);
 644         si_blitter_end(sctx);
 645 }
 646
 647 static void si_clear_depth_stencil(struct pipe_context *ctx,
 648                                    struct pipe_surface *dst,
 649                                    unsigned clear_flags,
 650                                    double depth,
 651                                    unsigned stencil,
 652                                    unsigned dstx, unsigned dsty,
 653                                    unsigned width, unsigned height,
 654                                    bool render_condition_enabled)
 655 {
 656         struct si_context *sctx = (struct si_context *)ctx;
 657
 658         si_blitter_begin(sctx, SI_CLEAR_SURFACE |
 659                          (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
 660         util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
 661                                          dstx, dsty, width, height);
 662         si_blitter_end(sctx);
 663 }
 664
 665 static void si_clear_texture(struct pipe_context *pipe,
 666                              struct pipe_resource *tex,
 667                              unsigned level,
 668                              const struct pipe_box *box,
 669                              const void *data)
 670 {
 671         struct pipe_screen *screen = pipe->screen;
 672         struct r600_texture *rtex = (struct r600_texture*)tex;
 673         struct pipe_surface tmpl = {{0}};
 674         struct pipe_surface *sf;
 675         const struct util_format_description *desc =
 676                 util_format_description(tex->format);
 677
 678         tmpl.format = tex->format;
 679         tmpl.u.tex.first_layer = box->z;
 680         tmpl.u.tex.last_layer = box->z + box->depth - 1;
 681         tmpl.u.tex.level = level;
 682         sf = pipe->create_surface(pipe, tex, &tmpl);
 683         if (!sf)
 684                 return;
 685
 686         if (rtex->is_depth) {
 687                 unsigned clear;
 688                 float depth;
 689                 uint8_t stencil = 0;
 690
 691                 /* Depth is always present. */
 692                 clear = PIPE_CLEAR_DEPTH;
 693                 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 694
 695                 if (rtex->surface.has_stencil) {
 696                         clear |= PIPE_CLEAR_STENCIL;
 697                         desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 698                 }
 699
 700                 si_clear_depth_stencil(pipe, sf, clear, depth, stencil,
 701                                        box->x, box->y,
 702                                        box->width, box->height, false);
 703         } else {
 704                 union pipe_color_union color;
 705
 706                 /* pipe_color_union requires the full vec4 representation. */
 707                 if (util_format_is_pure_uint(tex->format))
 708                         desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
 709                 else if (util_format_is_pure_sint(tex->format))
 710                         desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
 711                 else
 712                         desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
 713
 714                 if (screen->is_format_supported(screen, tex->format,
 715                                                 tex->target, 0,
 716                                                 PIPE_BIND_RENDER_TARGET)) {
 717                         si_clear_render_target(pipe, sf, &color,
 718                                                box->x, box->y,
 719                                                box->width, box->height, false);
 720                 } else {
 721                         /* Software fallback - just for R9G9B9E5_FLOAT */
 722                         util_clear_render_target(pipe, sf, &color,
 723                                                  box->x, box->y,
 724                                                  box->width, box->height);
 725                 }
 726         }
 727         pipe_surface_reference(&sf, NULL);
 728 }
 729
 730 void si_init_clear_functions(struct si_context *sctx)
 731 {
 732         sctx->b.clear = si_clear;
 733         sctx->b.clear_render_target = si_clear_render_target;
 734         sctx->b.clear_depth_stencil = si_clear_depth_stencil;
 735         sctx->b.clear_texture = si_clear_texture;
 736 }