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radeonsi: compile all TGSI compute shaders asynchronously
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28
29 #include "amd_kernel_code_t.h"
30 #include "radeon/r600_cs.h"
31 #include "si_pipe.h"
32 #include "sid.h"
33
34 #define MAX_GLOBAL_BUFFERS 22
35
36 struct si_compute {
37 struct si_screen *screen;
38 struct tgsi_token *tokens;
39 struct util_queue_fence ready;
40 struct si_compiler_ctx_state compiler_ctx_state;
41
42 unsigned ir_type;
43 unsigned local_size;
44 unsigned private_size;
45 unsigned input_size;
46 struct si_shader shader;
47
48 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
49 unsigned use_code_object_v2 : 1;
50 unsigned variable_group_size : 1;
51 };
52
53 struct dispatch_packet {
54 uint16_t header;
55 uint16_t setup;
56 uint16_t workgroup_size_x;
57 uint16_t workgroup_size_y;
58 uint16_t workgroup_size_z;
59 uint16_t reserved0;
60 uint32_t grid_size_x;
61 uint32_t grid_size_y;
62 uint32_t grid_size_z;
63 uint32_t private_segment_size;
64 uint32_t group_segment_size;
65 uint64_t kernel_object;
66 uint64_t kernarg_address;
67 uint64_t reserved2;
68 };
69
70 static const amd_kernel_code_t *si_compute_get_code_object(
71 const struct si_compute *program,
72 uint64_t symbol_offset)
73 {
74 if (!program->use_code_object_v2) {
75 return NULL;
76 }
77 return (const amd_kernel_code_t*)
78 (program->shader.binary.code + symbol_offset);
79 }
80
81 static void code_object_to_config(const amd_kernel_code_t *code_object,
82 struct si_shader_config *out_config) {
83
84 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
85 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
86 out_config->num_sgprs = code_object->wavefront_sgpr_count;
87 out_config->num_vgprs = code_object->workitem_vgpr_count;
88 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
89 out_config->rsrc1 = rsrc1;
90 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
91 out_config->rsrc2 = rsrc2;
92 out_config->scratch_bytes_per_wave =
93 align(code_object->workitem_private_segment_byte_size * 64, 1024);
94 }
95
96 /* Asynchronous compute shader compilation. */
97 static void si_create_compute_state_async(void *job, int thread_index)
98 {
99 struct si_compute *program = (struct si_compute *)job;
100 struct si_shader *shader = &program->shader;
101 struct si_shader_selector sel;
102 LLVMTargetMachineRef tm;
103 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
104
105 if (thread_index >= 0) {
106 assert(thread_index < ARRAY_SIZE(program->screen->tm));
107 tm = program->screen->tm[thread_index];
108 if (!debug->async)
109 debug = NULL;
110 } else {
111 tm = program->compiler_ctx_state.tm;
112 }
113
114 memset(&sel, 0, sizeof(sel));
115
116 tgsi_scan_shader(program->tokens, &sel.info);
117 sel.tokens = program->tokens;
118 sel.type = PIPE_SHADER_COMPUTE;
119 sel.local_size = program->local_size;
120
121 program->shader.selector = &sel;
122 program->shader.is_monolithic = true;
123
124 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
125 program->shader.compilation_failed = true;
126 } else {
127 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
128
129 shader->config.rsrc1 =
130 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
131 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
132 S_00B848_DX10_CLAMP(1) |
133 S_00B848_FLOAT_MODE(shader->config.float_mode);
134
135 shader->config.rsrc2 =
136 S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
137 S_00B84C_SCRATCH_EN(scratch_enabled) |
138 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
139 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
140 S_00B84C_LDS_SIZE(shader->config.lds_size);
141
142 program->variable_group_size =
143 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
144 }
145
146 FREE(program->tokens);
147 program->shader.selector = NULL;
148 }
149
150 static void *si_create_compute_state(
151 struct pipe_context *ctx,
152 const struct pipe_compute_state *cso)
153 {
154 struct si_context *sctx = (struct si_context *)ctx;
155 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
156 struct si_compute *program = CALLOC_STRUCT(si_compute);
157
158 program->screen = (struct si_screen *)ctx->screen;
159 program->ir_type = cso->ir_type;
160 program->local_size = cso->req_local_mem;
161 program->private_size = cso->req_private_mem;
162 program->input_size = cso->req_input_mem;
163 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
164 cso->ir_type == PIPE_SHADER_IR_NATIVE;
165
166 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
167 program->tokens = tgsi_dup_tokens(cso->prog);
168 if (!program->tokens) {
169 FREE(program);
170 return NULL;
171 }
172
173 program->compiler_ctx_state.tm = sctx->tm;
174 program->compiler_ctx_state.debug = sctx->b.debug;
175 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
176 p_atomic_inc(&sscreen->b.num_shaders_created);
177 util_queue_fence_init(&program->ready);
178
179 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
180 sctx->is_debug ||
181 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE))
182 si_create_compute_state_async(program, -1);
183 else
184 util_queue_add_job(&sscreen->shader_compiler_queue,
185 program, &program->ready,
186 si_create_compute_state_async, NULL);
187 } else {
188 const struct pipe_llvm_program_header *header;
189 const char *code;
190 header = cso->prog;
191 code = cso->prog + sizeof(struct pipe_llvm_program_header);
192
193 ac_elf_read(code, header->num_bytes, &program->shader.binary);
194 if (program->use_code_object_v2) {
195 const amd_kernel_code_t *code_object =
196 si_compute_get_code_object(program, 0);
197 code_object_to_config(code_object, &program->shader.config);
198 } else {
199 si_shader_binary_read_config(&program->shader.binary,
200 &program->shader.config, 0);
201 }
202 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
203 PIPE_SHADER_COMPUTE, stderr, true);
204 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
205 fprintf(stderr, "LLVM failed to upload shader\n");
206 FREE(program);
207 return NULL;
208 }
209 }
210
211 return program;
212 }
213
214 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
215 {
216 struct si_context *sctx = (struct si_context*)ctx;
217 sctx->cs_shader_state.program = (struct si_compute*)state;
218 }
219
220 static void si_set_global_binding(
221 struct pipe_context *ctx, unsigned first, unsigned n,
222 struct pipe_resource **resources,
223 uint32_t **handles)
224 {
225 unsigned i;
226 struct si_context *sctx = (struct si_context*)ctx;
227 struct si_compute *program = sctx->cs_shader_state.program;
228
229 assert(first + n <= MAX_GLOBAL_BUFFERS);
230
231 if (!resources) {
232 for (i = 0; i < n; i++) {
233 pipe_resource_reference(&program->global_buffers[first + i], NULL);
234 }
235 return;
236 }
237
238 for (i = 0; i < n; i++) {
239 uint64_t va;
240 uint32_t offset;
241 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
242 va = r600_resource(resources[i])->gpu_address;
243 offset = util_le32_to_cpu(*handles[i]);
244 va += offset;
245 va = util_cpu_to_le64(va);
246 memcpy(handles[i], &va, sizeof(va));
247 }
248 }
249
250 static void si_initialize_compute(struct si_context *sctx)
251 {
252 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
253 uint64_t bc_va;
254
255 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
256 radeon_emit(cs, 0);
257 radeon_emit(cs, 0);
258 radeon_emit(cs, 0);
259
260 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
261 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
262 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
263 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
264
265 if (sctx->b.chip_class >= CIK) {
266 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
267 radeon_set_sh_reg_seq(cs,
268 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
269 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
270 S_00B864_SH1_CU_EN(0xffff));
271 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
272 S_00B868_SH1_CU_EN(0xffff));
273 }
274
275 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
276 * and is now per pipe, so it should be handled in the
277 * kernel if we want to use something other than the default value,
278 * which is now 0x22f.
279 */
280 if (sctx->b.chip_class <= SI) {
281 /* XXX: This should be:
282 * (number of compute units) * 4 * (waves per simd) - 1 */
283
284 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
285 0x190 /* Default value */);
286 }
287
288 /* Set the pointer to border colors. */
289 bc_va = sctx->border_color_buffer->gpu_address;
290
291 if (sctx->b.chip_class >= CIK) {
292 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
293 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
294 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
295 } else {
296 if (sctx->screen->b.info.drm_major == 3 ||
297 (sctx->screen->b.info.drm_major == 2 &&
298 sctx->screen->b.info.drm_minor >= 48)) {
299 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
300 bc_va >> 8);
301 }
302 }
303
304 sctx->cs_shader_state.emitted_program = NULL;
305 sctx->cs_shader_state.initialized = true;
306 }
307
308 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
309 struct si_shader *shader,
310 struct si_shader_config *config)
311 {
312 uint64_t scratch_bo_size, scratch_needed;
313 scratch_bo_size = 0;
314 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
315 if (sctx->compute_scratch_buffer)
316 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
317
318 if (scratch_bo_size < scratch_needed) {
319 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
320
321 sctx->compute_scratch_buffer = (struct r600_resource*)
322 r600_aligned_buffer_create(&sctx->screen->b.b,
323 R600_RESOURCE_FLAG_UNMAPPABLE,
324 PIPE_USAGE_DEFAULT,
325 scratch_needed, 256);
326
327 if (!sctx->compute_scratch_buffer)
328 return false;
329 }
330
331 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
332 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
333
334 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
335
336 if (si_shader_binary_upload(sctx->screen, shader))
337 return false;
338
339 r600_resource_reference(&shader->scratch_bo,
340 sctx->compute_scratch_buffer);
341 }
342
343 return true;
344 }
345
346 static bool si_switch_compute_shader(struct si_context *sctx,
347 struct si_compute *program,
348 struct si_shader *shader,
349 const amd_kernel_code_t *code_object,
350 unsigned offset)
351 {
352 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
353 struct si_shader_config inline_config = {0};
354 struct si_shader_config *config;
355 uint64_t shader_va;
356
357 if (sctx->cs_shader_state.emitted_program == program &&
358 sctx->cs_shader_state.offset == offset)
359 return true;
360
361 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
362 config = &shader->config;
363 } else {
364 unsigned lds_blocks;
365
366 config = &inline_config;
367 if (code_object) {
368 code_object_to_config(code_object, config);
369 } else {
370 si_shader_binary_read_config(&shader->binary, config, offset);
371 }
372
373 lds_blocks = config->lds_size;
374 /* XXX: We are over allocating LDS. For SI, the shader reports
375 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
376 * allocated in the shader and 4 bytes allocated by the state
377 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
378 */
379 if (sctx->b.chip_class <= SI) {
380 lds_blocks += align(program->local_size, 256) >> 8;
381 } else {
382 lds_blocks += align(program->local_size, 512) >> 9;
383 }
384
385 /* TODO: use si_multiwave_lds_size_workaround */
386 assert(lds_blocks <= 0xFF);
387
388 config->rsrc2 &= C_00B84C_LDS_SIZE;
389 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
390 }
391
392 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
393 return false;
394
395 if (shader->scratch_bo) {
396 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
397 "Total Scratch: %u bytes\n", sctx->scratch_waves,
398 config->scratch_bytes_per_wave,
399 config->scratch_bytes_per_wave *
400 sctx->scratch_waves);
401
402 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
403 shader->scratch_bo, RADEON_USAGE_READWRITE,
404 RADEON_PRIO_SCRATCH_BUFFER);
405 }
406
407 /* Prefetch the compute shader to TC L2.
408 *
409 * We should also prefetch graphics shaders if a compute dispatch was
410 * the last command, and the compute shader if a draw call was the last
411 * command. However, that would add more complexity and we're likely
412 * to get a shader state change in that case anyway.
413 */
414 if (sctx->b.chip_class >= CIK) {
415 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
416 0, program->shader.bo->b.b.width0);
417 }
418
419 shader_va = shader->bo->gpu_address + offset;
420 if (program->use_code_object_v2) {
421 /* Shader code is placed after the amd_kernel_code_t
422 * struct. */
423 shader_va += sizeof(amd_kernel_code_t);
424 }
425
426 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
427 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
428
429 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
430 radeon_emit(cs, shader_va >> 8);
431 radeon_emit(cs, shader_va >> 40);
432
433 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
434 radeon_emit(cs, config->rsrc1);
435 radeon_emit(cs, config->rsrc2);
436
437 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
438 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
439
440 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
441 S_00B860_WAVES(sctx->scratch_waves)
442 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
443
444 sctx->cs_shader_state.emitted_program = program;
445 sctx->cs_shader_state.offset = offset;
446 sctx->cs_shader_state.uses_scratch =
447 config->scratch_bytes_per_wave != 0;
448
449 return true;
450 }
451
452 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
453 const amd_kernel_code_t *code_object,
454 unsigned user_sgpr)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
457 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
458
459 unsigned max_private_element_size = AMD_HSA_BITS_GET(
460 code_object->code_properties,
461 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
462
463 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
464 uint32_t scratch_dword1 =
465 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
466 S_008F04_SWIZZLE_ENABLE(1);
467
468 /* Disable address clamping */
469 uint32_t scratch_dword2 = 0xffffffff;
470 uint32_t scratch_dword3 =
471 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
472 S_008F0C_INDEX_STRIDE(3) |
473 S_008F0C_ADD_TID_ENABLE(1);
474
475
476 if (sctx->screen->b.chip_class < VI) {
477 /* BUF_DATA_FORMAT is ignored, but it cannot be
478 BUF_DATA_FORMAT_INVALID. */
479 scratch_dword3 |=
480 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
481 }
482
483 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
484 (user_sgpr * 4), 4);
485 radeon_emit(cs, scratch_dword0);
486 radeon_emit(cs, scratch_dword1);
487 radeon_emit(cs, scratch_dword2);
488 radeon_emit(cs, scratch_dword3);
489 }
490
491 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
492 const amd_kernel_code_t *code_object,
493 const struct pipe_grid_info *info,
494 uint64_t kernel_args_va)
495 {
496 struct si_compute *program = sctx->cs_shader_state.program;
497 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
498
499 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
500 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
501 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
502 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
503 };
504
505 unsigned i, user_sgpr = 0;
506 if (AMD_HSA_BITS_GET(code_object->code_properties,
507 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
508 if (code_object->workitem_private_segment_byte_size > 0) {
509 setup_scratch_rsrc_user_sgprs(sctx, code_object,
510 user_sgpr);
511 }
512 user_sgpr += 4;
513 }
514
515 if (AMD_HSA_BITS_GET(code_object->code_properties,
516 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
517 struct dispatch_packet dispatch;
518 unsigned dispatch_offset;
519 struct r600_resource *dispatch_buf = NULL;
520 uint64_t dispatch_va;
521
522 /* Upload dispatch ptr */
523 memset(&dispatch, 0, sizeof(dispatch));
524
525 dispatch.workgroup_size_x = info->block[0];
526 dispatch.workgroup_size_y = info->block[1];
527 dispatch.workgroup_size_z = info->block[2];
528
529 dispatch.grid_size_x = info->grid[0] * info->block[0];
530 dispatch.grid_size_y = info->grid[1] * info->block[1];
531 dispatch.grid_size_z = info->grid[2] * info->block[2];
532
533 dispatch.private_segment_size = program->private_size;
534 dispatch.group_segment_size = program->local_size;
535
536 dispatch.kernarg_address = kernel_args_va;
537
538 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
539 256, &dispatch, &dispatch_offset,
540 (struct pipe_resource**)&dispatch_buf);
541
542 if (!dispatch_buf) {
543 fprintf(stderr, "Error: Failed to allocate dispatch "
544 "packet.");
545 }
546 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
547 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
548
549 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
550
551 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
552 (user_sgpr * 4), 2);
553 radeon_emit(cs, dispatch_va);
554 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
555 S_008F04_STRIDE(0));
556
557 r600_resource_reference(&dispatch_buf, NULL);
558 user_sgpr += 2;
559 }
560
561 if (AMD_HSA_BITS_GET(code_object->code_properties,
562 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
563 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
564 (user_sgpr * 4), 2);
565 radeon_emit(cs, kernel_args_va);
566 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
567 S_008F04_STRIDE(0));
568 user_sgpr += 2;
569 }
570
571 for (i = 0; i < 3 && user_sgpr < 16; i++) {
572 if (code_object->code_properties & workgroup_count_masks[i]) {
573 radeon_set_sh_reg_seq(cs,
574 R_00B900_COMPUTE_USER_DATA_0 +
575 (user_sgpr * 4), 1);
576 radeon_emit(cs, info->grid[i]);
577 user_sgpr += 1;
578 }
579 }
580 }
581
582 static void si_upload_compute_input(struct si_context *sctx,
583 const amd_kernel_code_t *code_object,
584 const struct pipe_grid_info *info)
585 {
586 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
587 struct si_compute *program = sctx->cs_shader_state.program;
588 struct r600_resource *input_buffer = NULL;
589 unsigned kernel_args_size;
590 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
591 uint32_t kernel_args_offset = 0;
592 uint32_t *kernel_args;
593 void *kernel_args_ptr;
594 uint64_t kernel_args_va;
595 unsigned i;
596
597 /* The extra num_work_size_bytes are for work group / work item size information */
598 kernel_args_size = program->input_size + num_work_size_bytes;
599
600 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
601 sctx->screen->b.info.tcc_cache_line_size,
602 &kernel_args_offset,
603 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
604
605 kernel_args = (uint32_t*)kernel_args_ptr;
606 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
607
608 if (!code_object) {
609 for (i = 0; i < 3; i++) {
610 kernel_args[i] = info->grid[i];
611 kernel_args[i + 3] = info->grid[i] * info->block[i];
612 kernel_args[i + 6] = info->block[i];
613 }
614 }
615
616 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
617 program->input_size);
618
619
620 for (i = 0; i < (kernel_args_size / 4); i++) {
621 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
622 kernel_args[i]);
623 }
624
625
626 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
627 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
628
629 if (code_object) {
630 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
631 } else {
632 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
633 radeon_emit(cs, kernel_args_va);
634 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
635 S_008F04_STRIDE(0));
636 }
637
638 r600_resource_reference(&input_buffer, NULL);
639 }
640
641 static void si_setup_tgsi_grid(struct si_context *sctx,
642 const struct pipe_grid_info *info)
643 {
644 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
645 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
646 4 * SI_SGPR_GRID_SIZE;
647
648 if (info->indirect) {
649 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
650 uint64_t va = base_va + info->indirect_offset;
651 int i;
652
653 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
654 (struct r600_resource *)info->indirect,
655 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
656
657 for (i = 0; i < 3; ++i) {
658 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
659 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
660 COPY_DATA_DST_SEL(COPY_DATA_REG));
661 radeon_emit(cs, (va + 4 * i));
662 radeon_emit(cs, (va + 4 * i) >> 32);
663 radeon_emit(cs, (grid_size_reg >> 2) + i);
664 radeon_emit(cs, 0);
665 }
666 } else {
667 struct si_compute *program = sctx->cs_shader_state.program;
668
669 radeon_set_sh_reg_seq(cs, grid_size_reg, program->variable_group_size ? 6 : 3);
670 radeon_emit(cs, info->grid[0]);
671 radeon_emit(cs, info->grid[1]);
672 radeon_emit(cs, info->grid[2]);
673 if (program->variable_group_size) {
674 radeon_emit(cs, info->block[0]);
675 radeon_emit(cs, info->block[1]);
676 radeon_emit(cs, info->block[2]);
677 }
678 }
679 }
680
681 static void si_emit_dispatch_packets(struct si_context *sctx,
682 const struct pipe_grid_info *info)
683 {
684 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
685 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
686 unsigned waves_per_threadgroup =
687 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
688
689 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
690 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
691
692 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
693 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
694 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
695 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
696
697 if (info->indirect) {
698 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
699
700 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
701 (struct r600_resource *)info->indirect,
702 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
703
704 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
705 PKT3_SHADER_TYPE_S(1));
706 radeon_emit(cs, 1);
707 radeon_emit(cs, base_va);
708 radeon_emit(cs, base_va >> 32);
709
710 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
711 PKT3_SHADER_TYPE_S(1));
712 radeon_emit(cs, info->indirect_offset);
713 radeon_emit(cs, 1);
714 } else {
715 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
716 PKT3_SHADER_TYPE_S(1));
717 radeon_emit(cs, info->grid[0]);
718 radeon_emit(cs, info->grid[1]);
719 radeon_emit(cs, info->grid[2]);
720 radeon_emit(cs, 1);
721 }
722 }
723
724
725 static void si_launch_grid(
726 struct pipe_context *ctx, const struct pipe_grid_info *info)
727 {
728 struct si_context *sctx = (struct si_context*)ctx;
729 struct si_compute *program = sctx->cs_shader_state.program;
730 const amd_kernel_code_t *code_object =
731 si_compute_get_code_object(program, info->pc);
732 int i;
733 /* HW bug workaround when CS threadgroups > 256 threads and async
734 * compute isn't used, i.e. only one compute job can run at a time.
735 * If async compute is possible, the threadgroup size must be limited
736 * to 256 threads on all queues to avoid the bug.
737 * Only SI and certain CIK chips are affected.
738 */
739 bool cs_regalloc_hang =
740 (sctx->b.chip_class == SI ||
741 sctx->b.family == CHIP_BONAIRE ||
742 sctx->b.family == CHIP_KABINI) &&
743 info->block[0] * info->block[1] * info->block[2] > 256;
744
745 if (cs_regalloc_hang)
746 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
747 SI_CONTEXT_CS_PARTIAL_FLUSH;
748
749 util_queue_fence_wait(&program->ready);
750 si_decompress_compute_textures(sctx);
751
752 /* Add buffer sizes for memory checking in need_cs_space. */
753 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
754 /* TODO: add the scratch buffer */
755
756 if (info->indirect) {
757 r600_context_add_resource_size(ctx, info->indirect);
758
759 /* The hw doesn't read the indirect buffer via TC L2. */
760 if (r600_resource(info->indirect)->TC_L2_dirty) {
761 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
762 r600_resource(info->indirect)->TC_L2_dirty = false;
763 }
764 }
765
766 si_need_cs_space(sctx);
767
768 if (!sctx->cs_shader_state.initialized)
769 si_initialize_compute(sctx);
770
771 if (sctx->b.flags)
772 si_emit_cache_flush(sctx);
773
774 if (!si_switch_compute_shader(sctx, program, &program->shader,
775 code_object, info->pc))
776 return;
777
778 si_upload_compute_shader_descriptors(sctx);
779 si_emit_compute_shader_userdata(sctx);
780
781 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
782 sctx->atoms.s.render_cond->emit(&sctx->b,
783 sctx->atoms.s.render_cond);
784 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
785 }
786
787 if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
788 si_upload_compute_input(sctx, code_object, info);
789
790 /* Global buffers */
791 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
792 struct r600_resource *buffer =
793 (struct r600_resource*)program->global_buffers[i];
794 if (!buffer) {
795 continue;
796 }
797 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
798 RADEON_USAGE_READWRITE,
799 RADEON_PRIO_COMPUTE_GLOBAL);
800 }
801
802 if (program->ir_type == PIPE_SHADER_IR_TGSI)
803 si_setup_tgsi_grid(sctx, info);
804
805 si_ce_pre_draw_synchronization(sctx);
806
807 si_emit_dispatch_packets(sctx, info);
808
809 si_ce_post_draw_synchronization(sctx);
810
811 sctx->compute_is_busy = true;
812 sctx->b.num_compute_calls++;
813 if (sctx->cs_shader_state.uses_scratch)
814 sctx->b.num_spill_compute_calls++;
815
816 if (cs_regalloc_hang)
817 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
818 }
819
820
821 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
822 struct si_compute *program = (struct si_compute *)state;
823 struct si_context *sctx = (struct si_context*)ctx;
824
825 if (!state) {
826 return;
827 }
828
829 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
830 util_queue_fence_wait(&program->ready);
831 util_queue_fence_destroy(&program->ready);
832 }
833
834 if (program == sctx->cs_shader_state.program)
835 sctx->cs_shader_state.program = NULL;
836
837 if (program == sctx->cs_shader_state.emitted_program)
838 sctx->cs_shader_state.emitted_program = NULL;
839
840 si_shader_destroy(&program->shader);
841 FREE(program);
842 }
843
844 static void si_set_compute_resources(struct pipe_context * ctx_,
845 unsigned start, unsigned count,
846 struct pipe_surface ** surfaces) { }
847
848 void si_init_compute_functions(struct si_context *sctx)
849 {
850 sctx->b.b.create_compute_state = si_create_compute_state;
851 sctx->b.b.delete_compute_state = si_delete_compute_state;
852 sctx->b.b.bind_compute_state = si_bind_compute_state;
853 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
854 sctx->b.b.set_compute_resources = si_set_compute_resources;
855 sctx->b.b.set_global_binding = si_set_global_binding;
856 sctx->b.b.launch_grid = si_launch_grid;
857 }