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radeonsi: rename and re-document cache flush flags
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "ac_rtld.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 if (!program->use_code_object_v2) {
63 return NULL;
64 }
65
66 struct ac_rtld_binary rtld;
67 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
68 .info = &program->screen->info,
69 .num_parts = 1,
70 .elf_ptrs = &program->shader.binary.elf_buffer,
71 .elf_sizes = &program->shader.binary.elf_size }))
72 return NULL;
73
74 const amd_kernel_code_t *result = NULL;
75 const char *text;
76 size_t size;
77 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
78 goto out;
79
80 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
81 goto out;
82
83 result = (const amd_kernel_code_t*)(text + symbol_offset);
84
85 out:
86 ac_rtld_close(&rtld);
87 return result;
88 }
89
90 static void code_object_to_config(const amd_kernel_code_t *code_object,
91 struct ac_shader_config *out_config) {
92
93 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
94 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
95 out_config->num_sgprs = code_object->wavefront_sgpr_count;
96 out_config->num_vgprs = code_object->workitem_vgpr_count;
97 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
98 out_config->rsrc1 = rsrc1;
99 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
100 out_config->rsrc2 = rsrc2;
101 out_config->scratch_bytes_per_wave =
102 align(code_object->workitem_private_segment_byte_size * 64, 1024);
103 }
104
105 /* Asynchronous compute shader compilation. */
106 static void si_create_compute_state_async(void *job, int thread_index)
107 {
108 struct si_compute *program = (struct si_compute *)job;
109 struct si_shader *shader = &program->shader;
110 struct si_shader_selector sel;
111 struct ac_llvm_compiler *compiler;
112 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
113 struct si_screen *sscreen = program->screen;
114
115 assert(!debug->debug_message || debug->async);
116 assert(thread_index >= 0);
117 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
118 compiler = &sscreen->compiler[thread_index];
119
120 memset(&sel, 0, sizeof(sel));
121
122 sel.screen = sscreen;
123
124 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
125 tgsi_scan_shader(program->ir.tgsi, &sel.info);
126 sel.tokens = program->ir.tgsi;
127 } else {
128 assert(program->ir_type == PIPE_SHADER_IR_NIR);
129 sel.nir = program->ir.nir;
130
131 si_nir_opts(sel.nir);
132 si_nir_scan_shader(sel.nir, &sel.info);
133 si_lower_nir(&sel);
134 }
135
136 /* Store the declared LDS size into tgsi_shader_info for the shader
137 * cache to include it.
138 */
139 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
140
141 sel.type = PIPE_SHADER_COMPUTE;
142 si_get_active_slot_masks(&sel.info,
143 &program->active_const_and_shader_buffers,
144 &program->active_samplers_and_images);
145
146 program->shader.selector = &sel;
147 program->shader.is_monolithic = true;
148 program->uses_grid_size = sel.info.uses_grid_size;
149 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
150 program->uses_bindless_images = sel.info.uses_bindless_images;
151 program->reads_variable_block_size =
152 sel.info.uses_block_size &&
153 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
154 program->num_cs_user_data_dwords =
155 sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
156
157 void *ir_binary = si_get_ir_binary(&sel);
158
159 /* Try to load the shader from the shader cache. */
160 mtx_lock(&sscreen->shader_cache_mutex);
161
162 if (ir_binary &&
163 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
164 mtx_unlock(&sscreen->shader_cache_mutex);
165
166 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
167 si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
168 stderr, true);
169
170 if (!si_shader_binary_upload(sscreen, shader, 0))
171 program->shader.compilation_failed = true;
172 } else {
173 mtx_unlock(&sscreen->shader_cache_mutex);
174
175 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
176 program->shader.compilation_failed = true;
177
178 if (program->ir_type == PIPE_SHADER_IR_TGSI)
179 FREE(program->ir.tgsi);
180 program->shader.selector = NULL;
181 return;
182 }
183
184 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
185 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
186 (sel.info.uses_grid_size ? 3 : 0) +
187 (program->reads_variable_block_size ? 3 : 0) +
188 program->num_cs_user_data_dwords;
189
190 shader->config.rsrc1 =
191 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
192 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
193 S_00B848_DX10_CLAMP(1) |
194 S_00B848_FLOAT_MODE(shader->config.float_mode);
195
196 shader->config.rsrc2 =
197 S_00B84C_USER_SGPR(user_sgprs) |
198 S_00B84C_SCRATCH_EN(scratch_enabled) |
199 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
200 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
201 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
202 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
203 sel.info.uses_thread_id[1] ? 1 : 0) |
204 S_00B84C_LDS_SIZE(shader->config.lds_size);
205
206 if (ir_binary) {
207 mtx_lock(&sscreen->shader_cache_mutex);
208 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
209 FREE(ir_binary);
210 mtx_unlock(&sscreen->shader_cache_mutex);
211 }
212 }
213
214 if (program->ir_type == PIPE_SHADER_IR_TGSI)
215 FREE(program->ir.tgsi);
216
217 program->shader.selector = NULL;
218 }
219
220 static void *si_create_compute_state(
221 struct pipe_context *ctx,
222 const struct pipe_compute_state *cso)
223 {
224 struct si_context *sctx = (struct si_context *)ctx;
225 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
226 struct si_compute *program = CALLOC_STRUCT(si_compute);
227
228 pipe_reference_init(&program->reference, 1);
229 program->screen = (struct si_screen *)ctx->screen;
230 program->ir_type = cso->ir_type;
231 program->local_size = cso->req_local_mem;
232 program->private_size = cso->req_private_mem;
233 program->input_size = cso->req_input_mem;
234 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
235
236 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
237 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
238 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
239 if (!program->ir.tgsi) {
240 FREE(program);
241 return NULL;
242 }
243 } else {
244 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
245 program->ir.nir = (struct nir_shader *) cso->prog;
246 }
247
248 program->compiler_ctx_state.debug = sctx->debug;
249 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
250 p_atomic_inc(&sscreen->num_shaders_created);
251
252 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
253 &program->ready,
254 &program->compiler_ctx_state,
255 program, si_create_compute_state_async);
256 } else {
257 const struct pipe_llvm_program_header *header;
258 const char *code;
259 header = cso->prog;
260 code = cso->prog + sizeof(struct pipe_llvm_program_header);
261
262 program->shader.binary.elf_size = header->num_bytes;
263 program->shader.binary.elf_buffer = malloc(header->num_bytes);
264 if (!program->shader.binary.elf_buffer) {
265 FREE(program);
266 return NULL;
267 }
268 memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
269
270 const amd_kernel_code_t *code_object =
271 si_compute_get_code_object(program, 0);
272 code_object_to_config(code_object, &program->shader.config);
273
274 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
275 PIPE_SHADER_COMPUTE, stderr, true);
276 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
277 fprintf(stderr, "LLVM failed to upload shader\n");
278 free((void *)program->shader.binary.elf_buffer);
279 FREE(program);
280 return NULL;
281 }
282 }
283
284 return program;
285 }
286
287 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
288 {
289 struct si_context *sctx = (struct si_context*)ctx;
290 struct si_compute *program = (struct si_compute*)state;
291
292 sctx->cs_shader_state.program = program;
293 if (!program)
294 return;
295
296 /* Wait because we need active slot usage masks. */
297 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
298 util_queue_fence_wait(&program->ready);
299
300 si_set_active_descriptors(sctx,
301 SI_DESCS_FIRST_COMPUTE +
302 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
303 program->active_const_and_shader_buffers);
304 si_set_active_descriptors(sctx,
305 SI_DESCS_FIRST_COMPUTE +
306 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
307 program->active_samplers_and_images);
308 }
309
310 static void si_set_global_binding(
311 struct pipe_context *ctx, unsigned first, unsigned n,
312 struct pipe_resource **resources,
313 uint32_t **handles)
314 {
315 unsigned i;
316 struct si_context *sctx = (struct si_context*)ctx;
317 struct si_compute *program = sctx->cs_shader_state.program;
318
319 assert(first + n <= MAX_GLOBAL_BUFFERS);
320
321 if (!resources) {
322 for (i = 0; i < n; i++) {
323 pipe_resource_reference(&program->global_buffers[first + i], NULL);
324 }
325 return;
326 }
327
328 for (i = 0; i < n; i++) {
329 uint64_t va;
330 uint32_t offset;
331 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
332 va = si_resource(resources[i])->gpu_address;
333 offset = util_le32_to_cpu(*handles[i]);
334 va += offset;
335 va = util_cpu_to_le64(va);
336 memcpy(handles[i], &va, sizeof(va));
337 }
338 }
339
340 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
341 {
342 uint64_t bc_va;
343
344 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
345 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
346 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
347 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
348
349 if (sctx->chip_class >= GFX7) {
350 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
351 radeon_set_sh_reg_seq(cs,
352 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
353 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
354 S_00B858_SH1_CU_EN(0xffff));
355 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
356 S_00B858_SH1_CU_EN(0xffff));
357 }
358
359 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
360 * and is now per pipe, so it should be handled in the
361 * kernel if we want to use something other than the default value,
362 * which is now 0x22f.
363 */
364 if (sctx->chip_class <= GFX6) {
365 /* XXX: This should be:
366 * (number of compute units) * 4 * (waves per simd) - 1 */
367
368 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
369 0x190 /* Default value */);
370 }
371
372 /* Set the pointer to border colors. */
373 bc_va = sctx->border_color_buffer->gpu_address;
374
375 if (sctx->chip_class >= GFX7) {
376 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
377 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
378 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
379 } else {
380 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
381 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
382 bc_va >> 8);
383 }
384 }
385 }
386
387 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
388 struct si_shader *shader,
389 struct ac_shader_config *config)
390 {
391 uint64_t scratch_bo_size, scratch_needed;
392 scratch_bo_size = 0;
393 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
394 if (sctx->compute_scratch_buffer)
395 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
396
397 if (scratch_bo_size < scratch_needed) {
398 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
399
400 sctx->compute_scratch_buffer =
401 si_aligned_buffer_create(&sctx->screen->b,
402 SI_RESOURCE_FLAG_UNMAPPABLE,
403 PIPE_USAGE_DEFAULT,
404 scratch_needed, 256);
405
406 if (!sctx->compute_scratch_buffer)
407 return false;
408 }
409
410 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
411 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
412
413 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
414 return false;
415
416 si_resource_reference(&shader->scratch_bo,
417 sctx->compute_scratch_buffer);
418 }
419
420 return true;
421 }
422
423 static bool si_switch_compute_shader(struct si_context *sctx,
424 struct si_compute *program,
425 struct si_shader *shader,
426 const amd_kernel_code_t *code_object,
427 unsigned offset)
428 {
429 struct radeon_cmdbuf *cs = sctx->gfx_cs;
430 struct ac_shader_config inline_config = {0};
431 struct ac_shader_config *config;
432 uint64_t shader_va;
433
434 if (sctx->cs_shader_state.emitted_program == program &&
435 sctx->cs_shader_state.offset == offset)
436 return true;
437
438 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
439 config = &shader->config;
440 } else {
441 unsigned lds_blocks;
442
443 config = &inline_config;
444 code_object_to_config(code_object, config);
445
446 lds_blocks = config->lds_size;
447 /* XXX: We are over allocating LDS. For GFX6, the shader reports
448 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
449 * allocated in the shader and 4 bytes allocated by the state
450 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
451 */
452 if (sctx->chip_class <= GFX6) {
453 lds_blocks += align(program->local_size, 256) >> 8;
454 } else {
455 lds_blocks += align(program->local_size, 512) >> 9;
456 }
457
458 /* TODO: use si_multiwave_lds_size_workaround */
459 assert(lds_blocks <= 0xFF);
460
461 config->rsrc2 &= C_00B84C_LDS_SIZE;
462 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
463 }
464
465 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
466 return false;
467
468 if (shader->scratch_bo) {
469 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
470 "Total Scratch: %u bytes\n", sctx->scratch_waves,
471 config->scratch_bytes_per_wave,
472 config->scratch_bytes_per_wave *
473 sctx->scratch_waves);
474
475 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
476 shader->scratch_bo, RADEON_USAGE_READWRITE,
477 RADEON_PRIO_SCRATCH_BUFFER);
478 }
479
480 /* Prefetch the compute shader to TC L2.
481 *
482 * We should also prefetch graphics shaders if a compute dispatch was
483 * the last command, and the compute shader if a draw call was the last
484 * command. However, that would add more complexity and we're likely
485 * to get a shader state change in that case anyway.
486 */
487 if (sctx->chip_class >= GFX7) {
488 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
489 0, program->shader.bo->b.b.width0);
490 }
491
492 shader_va = shader->bo->gpu_address + offset;
493 if (program->use_code_object_v2) {
494 /* Shader code is placed after the amd_kernel_code_t
495 * struct. */
496 shader_va += sizeof(amd_kernel_code_t);
497 }
498
499 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
500 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
501
502 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
503 radeon_emit(cs, shader_va >> 8);
504 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
505
506 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
507 radeon_emit(cs, config->rsrc1);
508 radeon_emit(cs, config->rsrc2);
509
510 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
511 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
512
513 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
514 S_00B860_WAVES(sctx->scratch_waves)
515 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
516
517 sctx->cs_shader_state.emitted_program = program;
518 sctx->cs_shader_state.offset = offset;
519 sctx->cs_shader_state.uses_scratch =
520 config->scratch_bytes_per_wave != 0;
521
522 return true;
523 }
524
525 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
526 const amd_kernel_code_t *code_object,
527 unsigned user_sgpr)
528 {
529 struct radeon_cmdbuf *cs = sctx->gfx_cs;
530 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
531
532 unsigned max_private_element_size = AMD_HSA_BITS_GET(
533 code_object->code_properties,
534 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
535
536 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
537 uint32_t scratch_dword1 =
538 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
539 S_008F04_SWIZZLE_ENABLE(1);
540
541 /* Disable address clamping */
542 uint32_t scratch_dword2 = 0xffffffff;
543 uint32_t scratch_dword3 =
544 S_008F0C_INDEX_STRIDE(3) |
545 S_008F0C_ADD_TID_ENABLE(1);
546
547 if (sctx->chip_class >= GFX9) {
548 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
549 } else {
550 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
551
552 if (sctx->chip_class < GFX8) {
553 /* BUF_DATA_FORMAT is ignored, but it cannot be
554 * BUF_DATA_FORMAT_INVALID. */
555 scratch_dword3 |=
556 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
557 }
558 }
559
560 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
561 (user_sgpr * 4), 4);
562 radeon_emit(cs, scratch_dword0);
563 radeon_emit(cs, scratch_dword1);
564 radeon_emit(cs, scratch_dword2);
565 radeon_emit(cs, scratch_dword3);
566 }
567
568 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
569 const amd_kernel_code_t *code_object,
570 const struct pipe_grid_info *info,
571 uint64_t kernel_args_va)
572 {
573 struct si_compute *program = sctx->cs_shader_state.program;
574 struct radeon_cmdbuf *cs = sctx->gfx_cs;
575
576 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
577 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
578 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
579 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
580 };
581
582 unsigned i, user_sgpr = 0;
583 if (AMD_HSA_BITS_GET(code_object->code_properties,
584 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
585 if (code_object->workitem_private_segment_byte_size > 0) {
586 setup_scratch_rsrc_user_sgprs(sctx, code_object,
587 user_sgpr);
588 }
589 user_sgpr += 4;
590 }
591
592 if (AMD_HSA_BITS_GET(code_object->code_properties,
593 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
594 struct dispatch_packet dispatch;
595 unsigned dispatch_offset;
596 struct si_resource *dispatch_buf = NULL;
597 uint64_t dispatch_va;
598
599 /* Upload dispatch ptr */
600 memset(&dispatch, 0, sizeof(dispatch));
601
602 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
603 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
604 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
605
606 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
607 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
608 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
609
610 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
611 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
612
613 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
614
615 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
616 256, &dispatch, &dispatch_offset,
617 (struct pipe_resource**)&dispatch_buf);
618
619 if (!dispatch_buf) {
620 fprintf(stderr, "Error: Failed to allocate dispatch "
621 "packet.");
622 }
623 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
624 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
625
626 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
627
628 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
629 (user_sgpr * 4), 2);
630 radeon_emit(cs, dispatch_va);
631 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
632 S_008F04_STRIDE(0));
633
634 si_resource_reference(&dispatch_buf, NULL);
635 user_sgpr += 2;
636 }
637
638 if (AMD_HSA_BITS_GET(code_object->code_properties,
639 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
640 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
641 (user_sgpr * 4), 2);
642 radeon_emit(cs, kernel_args_va);
643 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
644 S_008F04_STRIDE(0));
645 user_sgpr += 2;
646 }
647
648 for (i = 0; i < 3 && user_sgpr < 16; i++) {
649 if (code_object->code_properties & workgroup_count_masks[i]) {
650 radeon_set_sh_reg_seq(cs,
651 R_00B900_COMPUTE_USER_DATA_0 +
652 (user_sgpr * 4), 1);
653 radeon_emit(cs, info->grid[i]);
654 user_sgpr += 1;
655 }
656 }
657 }
658
659 static bool si_upload_compute_input(struct si_context *sctx,
660 const amd_kernel_code_t *code_object,
661 const struct pipe_grid_info *info)
662 {
663 struct radeon_cmdbuf *cs = sctx->gfx_cs;
664 struct si_compute *program = sctx->cs_shader_state.program;
665 struct si_resource *input_buffer = NULL;
666 unsigned kernel_args_size;
667 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
668 uint32_t kernel_args_offset = 0;
669 uint32_t *kernel_args;
670 void *kernel_args_ptr;
671 uint64_t kernel_args_va;
672 unsigned i;
673
674 /* The extra num_work_size_bytes are for work group / work item size information */
675 kernel_args_size = program->input_size + num_work_size_bytes;
676
677 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
678 sctx->screen->info.tcc_cache_line_size,
679 &kernel_args_offset,
680 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
681
682 if (unlikely(!kernel_args_ptr))
683 return false;
684
685 kernel_args = (uint32_t*)kernel_args_ptr;
686 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
687
688 if (!code_object) {
689 for (i = 0; i < 3; i++) {
690 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
691 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
692 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
693 }
694 }
695
696 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
697 program->input_size);
698
699
700 for (i = 0; i < (kernel_args_size / 4); i++) {
701 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
702 kernel_args[i]);
703 }
704
705
706 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
707 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
708
709 if (code_object) {
710 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
711 } else {
712 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
713 radeon_emit(cs, kernel_args_va);
714 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
715 S_008F04_STRIDE(0));
716 }
717
718 si_resource_reference(&input_buffer, NULL);
719
720 return true;
721 }
722
723 static void si_setup_tgsi_user_data(struct si_context *sctx,
724 const struct pipe_grid_info *info)
725 {
726 struct si_compute *program = sctx->cs_shader_state.program;
727 struct radeon_cmdbuf *cs = sctx->gfx_cs;
728 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
729 4 * SI_NUM_RESOURCE_SGPRS;
730 unsigned block_size_reg = grid_size_reg +
731 /* 12 bytes = 3 dwords. */
732 12 * program->uses_grid_size;
733 unsigned cs_user_data_reg = block_size_reg +
734 12 * program->reads_variable_block_size;
735
736 if (info->indirect) {
737 if (program->uses_grid_size) {
738 for (unsigned i = 0; i < 3; ++i) {
739 si_cp_copy_data(sctx, sctx->gfx_cs,
740 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
741 COPY_DATA_SRC_MEM, si_resource(info->indirect),
742 info->indirect_offset + 4 * i);
743 }
744 }
745 } else {
746 if (program->uses_grid_size) {
747 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
748 radeon_emit(cs, info->grid[0]);
749 radeon_emit(cs, info->grid[1]);
750 radeon_emit(cs, info->grid[2]);
751 }
752 if (program->reads_variable_block_size) {
753 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
754 radeon_emit(cs, info->block[0]);
755 radeon_emit(cs, info->block[1]);
756 radeon_emit(cs, info->block[2]);
757 }
758 }
759
760 if (program->num_cs_user_data_dwords) {
761 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
762 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
763 }
764 }
765
766 unsigned si_get_compute_resource_limits(struct si_screen *sscreen,
767 unsigned waves_per_threadgroup,
768 unsigned max_waves_per_sh,
769 unsigned threadgroups_per_cu)
770 {
771 unsigned compute_resource_limits =
772 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
773
774 if (sscreen->info.chip_class >= GFX7) {
775 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
776 sscreen->info.max_se;
777
778 /* Force even distribution on all SIMDs in CU if the workgroup
779 * size is 64. This has shown some good improvements if # of CUs
780 * per SE is not a multiple of 4.
781 */
782 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
783 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
784
785 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
786 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
787 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
788 } else {
789 /* GFX6 */
790 if (max_waves_per_sh) {
791 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
792 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
793 }
794 }
795 return compute_resource_limits;
796 }
797
798 static void si_emit_dispatch_packets(struct si_context *sctx,
799 const struct pipe_grid_info *info)
800 {
801 struct si_screen *sscreen = sctx->screen;
802 struct radeon_cmdbuf *cs = sctx->gfx_cs;
803 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
804 unsigned waves_per_threadgroup =
805 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
806
807 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
808 si_get_compute_resource_limits(sscreen, waves_per_threadgroup,
809 sctx->cs_max_waves_per_sh, 1));
810
811 unsigned dispatch_initiator =
812 S_00B800_COMPUTE_SHADER_EN(1) |
813 S_00B800_FORCE_START_AT_000(1) |
814 /* If the KMD allows it (there is a KMD hw register for it),
815 * allow launching waves out-of-order. (same as Vulkan) */
816 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
817
818 const uint *last_block = info->last_block;
819 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
820
821 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
822
823 if (partial_block_en) {
824 unsigned partial[3];
825
826 /* If no partial_block, these should be an entire block size, not 0. */
827 partial[0] = last_block[0] ? last_block[0] : info->block[0];
828 partial[1] = last_block[1] ? last_block[1] : info->block[1];
829 partial[2] = last_block[2] ? last_block[2] : info->block[2];
830
831 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
832 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
833 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
834 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
835 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
836 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
837
838 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
839 } else {
840 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
841 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
842 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
843 }
844
845 if (info->indirect) {
846 uint64_t base_va = si_resource(info->indirect)->gpu_address;
847
848 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
849 si_resource(info->indirect),
850 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
851
852 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
853 PKT3_SHADER_TYPE_S(1));
854 radeon_emit(cs, 1);
855 radeon_emit(cs, base_va);
856 radeon_emit(cs, base_va >> 32);
857
858 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
859 PKT3_SHADER_TYPE_S(1));
860 radeon_emit(cs, info->indirect_offset);
861 radeon_emit(cs, dispatch_initiator);
862 } else {
863 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
864 PKT3_SHADER_TYPE_S(1));
865 radeon_emit(cs, info->grid[0]);
866 radeon_emit(cs, info->grid[1]);
867 radeon_emit(cs, info->grid[2]);
868 radeon_emit(cs, dispatch_initiator);
869 }
870 }
871
872
873 static void si_launch_grid(
874 struct pipe_context *ctx, const struct pipe_grid_info *info)
875 {
876 struct si_context *sctx = (struct si_context*)ctx;
877 struct si_compute *program = sctx->cs_shader_state.program;
878 const amd_kernel_code_t *code_object =
879 si_compute_get_code_object(program, info->pc);
880 int i;
881 /* HW bug workaround when CS threadgroups > 256 threads and async
882 * compute isn't used, i.e. only one compute job can run at a time.
883 * If async compute is possible, the threadgroup size must be limited
884 * to 256 threads on all queues to avoid the bug.
885 * Only GFX6 and certain GFX7 chips are affected.
886 */
887 bool cs_regalloc_hang =
888 (sctx->chip_class == GFX6 ||
889 sctx->family == CHIP_BONAIRE ||
890 sctx->family == CHIP_KABINI) &&
891 info->block[0] * info->block[1] * info->block[2] > 256;
892
893 if (cs_regalloc_hang)
894 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
895 SI_CONTEXT_CS_PARTIAL_FLUSH;
896
897 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
898 program->shader.compilation_failed)
899 return;
900
901 if (sctx->has_graphics) {
902 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
903 si_update_fb_dirtiness_after_rendering(sctx);
904 sctx->last_num_draw_calls = sctx->num_draw_calls;
905 }
906
907 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
908 }
909
910 /* Add buffer sizes for memory checking in need_cs_space. */
911 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
912 /* TODO: add the scratch buffer */
913
914 if (info->indirect) {
915 si_context_add_resource_size(sctx, info->indirect);
916
917 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
918 if (sctx->chip_class <= GFX8 &&
919 si_resource(info->indirect)->TC_L2_dirty) {
920 sctx->flags |= SI_CONTEXT_WB_L2;
921 si_resource(info->indirect)->TC_L2_dirty = false;
922 }
923 }
924
925 si_need_gfx_cs_space(sctx);
926
927 if (sctx->bo_list_add_all_compute_resources)
928 si_compute_resources_add_all_to_bo_list(sctx);
929
930 if (!sctx->cs_shader_state.initialized) {
931 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
932
933 sctx->cs_shader_state.emitted_program = NULL;
934 sctx->cs_shader_state.initialized = true;
935 }
936
937 if (sctx->flags)
938 si_emit_cache_flush(sctx);
939
940 if (!si_switch_compute_shader(sctx, program, &program->shader,
941 code_object, info->pc))
942 return;
943
944 si_upload_compute_shader_descriptors(sctx);
945 si_emit_compute_shader_pointers(sctx);
946
947 if (sctx->has_graphics &&
948 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
949 sctx->atoms.s.render_cond.emit(sctx);
950 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
951 }
952
953 if ((program->input_size ||
954 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
955 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
956 return;
957 }
958
959 /* Global buffers */
960 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
961 struct si_resource *buffer =
962 si_resource(program->global_buffers[i]);
963 if (!buffer) {
964 continue;
965 }
966 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
967 RADEON_USAGE_READWRITE,
968 RADEON_PRIO_COMPUTE_GLOBAL);
969 }
970
971 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
972 si_setup_tgsi_user_data(sctx, info);
973
974 si_emit_dispatch_packets(sctx, info);
975
976 if (unlikely(sctx->current_saved_cs)) {
977 si_trace_emit(sctx);
978 si_log_compute_state(sctx, sctx->log);
979 }
980
981 sctx->compute_is_busy = true;
982 sctx->num_compute_calls++;
983 if (sctx->cs_shader_state.uses_scratch)
984 sctx->num_spill_compute_calls++;
985
986 if (cs_regalloc_hang)
987 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
988 }
989
990 void si_destroy_compute(struct si_compute *program)
991 {
992 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
993 util_queue_drop_job(&program->screen->shader_compiler_queue,
994 &program->ready);
995 util_queue_fence_destroy(&program->ready);
996 }
997
998 si_shader_destroy(&program->shader);
999 FREE(program);
1000 }
1001
1002 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
1003 struct si_compute *program = (struct si_compute *)state;
1004 struct si_context *sctx = (struct si_context*)ctx;
1005
1006 if (!state)
1007 return;
1008
1009 if (program == sctx->cs_shader_state.program)
1010 sctx->cs_shader_state.program = NULL;
1011
1012 if (program == sctx->cs_shader_state.emitted_program)
1013 sctx->cs_shader_state.emitted_program = NULL;
1014
1015 si_compute_reference(&program, NULL);
1016 }
1017
1018 static void si_set_compute_resources(struct pipe_context * ctx_,
1019 unsigned start, unsigned count,
1020 struct pipe_surface ** surfaces) { }
1021
1022 void si_init_compute_functions(struct si_context *sctx)
1023 {
1024 sctx->b.create_compute_state = si_create_compute_state;
1025 sctx->b.delete_compute_state = si_delete_compute_state;
1026 sctx->b.bind_compute_state = si_bind_compute_state;
1027 sctx->b.set_compute_resources = si_set_compute_resources;
1028 sctx->b.set_global_binding = si_set_global_binding;
1029 sctx->b.launch_grid = si_launch_grid;
1030 }