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amd: remove support for LLVM 3.9
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_async_debug.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "si_compute.h"
34 #include "sid.h"
35
36 #define COMPUTE_DBG(rscreen, fmt, args...) \
37 do { \
38 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 if (!program->use_code_object_v2) {
63 return NULL;
64 }
65 return (const amd_kernel_code_t*)
66 (program->shader.binary.code + symbol_offset);
67 }
68
69 static void code_object_to_config(const amd_kernel_code_t *code_object,
70 struct si_shader_config *out_config) {
71
72 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
73 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
74 out_config->num_sgprs = code_object->wavefront_sgpr_count;
75 out_config->num_vgprs = code_object->workitem_vgpr_count;
76 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
77 out_config->rsrc1 = rsrc1;
78 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
79 out_config->rsrc2 = rsrc2;
80 out_config->scratch_bytes_per_wave =
81 align(code_object->workitem_private_segment_byte_size * 64, 1024);
82 }
83
84 /* Asynchronous compute shader compilation. */
85 static void si_create_compute_state_async(void *job, int thread_index)
86 {
87 struct si_compute *program = (struct si_compute *)job;
88 struct si_shader *shader = &program->shader;
89 struct si_shader_selector sel;
90 LLVMTargetMachineRef tm;
91 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
92
93 assert(!debug->debug_message || debug->async);
94 assert(thread_index >= 0);
95 assert(thread_index < ARRAY_SIZE(program->screen->tm));
96 tm = program->screen->tm[thread_index];
97
98 memset(&sel, 0, sizeof(sel));
99
100 sel.screen = program->screen;
101 tgsi_scan_shader(program->tokens, &sel.info);
102 sel.tokens = program->tokens;
103 sel.type = PIPE_SHADER_COMPUTE;
104 sel.local_size = program->local_size;
105 si_get_active_slot_masks(&sel.info,
106 &program->active_const_and_shader_buffers,
107 &program->active_samplers_and_images);
108
109 program->shader.selector = &sel;
110 program->shader.is_monolithic = true;
111 program->uses_grid_size = sel.info.uses_grid_size;
112 program->uses_block_size = sel.info.uses_block_size;
113 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
114 program->uses_bindless_images = sel.info.uses_bindless_images;
115
116 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
117 program->shader.compilation_failed = true;
118 } else {
119 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
120 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
121 (sel.info.uses_grid_size ? 3 : 0) +
122 (sel.info.uses_block_size ? 3 : 0);
123
124 shader->config.rsrc1 =
125 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
126 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
127 S_00B848_DX10_CLAMP(1) |
128 S_00B848_FLOAT_MODE(shader->config.float_mode);
129
130 shader->config.rsrc2 =
131 S_00B84C_USER_SGPR(user_sgprs) |
132 S_00B84C_SCRATCH_EN(scratch_enabled) |
133 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
134 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
135 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
136 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
137 sel.info.uses_thread_id[1] ? 1 : 0) |
138 S_00B84C_LDS_SIZE(shader->config.lds_size);
139
140 program->variable_group_size =
141 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
142 }
143
144 FREE(program->tokens);
145 program->shader.selector = NULL;
146 }
147
148 static void *si_create_compute_state(
149 struct pipe_context *ctx,
150 const struct pipe_compute_state *cso)
151 {
152 struct si_context *sctx = (struct si_context *)ctx;
153 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
154 struct si_compute *program = CALLOC_STRUCT(si_compute);
155
156 pipe_reference_init(&program->reference, 1);
157 program->screen = (struct si_screen *)ctx->screen;
158 program->ir_type = cso->ir_type;
159 program->local_size = cso->req_local_mem;
160 program->private_size = cso->req_private_mem;
161 program->input_size = cso->req_input_mem;
162 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
163
164 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
165 program->tokens = tgsi_dup_tokens(cso->prog);
166 if (!program->tokens) {
167 FREE(program);
168 return NULL;
169 }
170
171 program->compiler_ctx_state.debug = sctx->debug;
172 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
173 p_atomic_inc(&sscreen->num_shaders_created);
174 util_queue_fence_init(&program->ready);
175
176 struct util_async_debug_callback async_debug;
177 bool wait =
178 (sctx->debug.debug_message && !sctx->debug.async) ||
179 sctx->is_debug ||
180 si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE);
181
182 if (wait) {
183 u_async_debug_init(&async_debug);
184 program->compiler_ctx_state.debug = async_debug.base;
185 }
186
187 util_queue_add_job(&sscreen->shader_compiler_queue,
188 program, &program->ready,
189 si_create_compute_state_async, NULL);
190
191 if (wait) {
192 util_queue_fence_wait(&program->ready);
193 u_async_debug_drain(&async_debug, &sctx->debug);
194 u_async_debug_cleanup(&async_debug);
195 }
196 } else {
197 const struct pipe_llvm_program_header *header;
198 const char *code;
199 header = cso->prog;
200 code = cso->prog + sizeof(struct pipe_llvm_program_header);
201
202 ac_elf_read(code, header->num_bytes, &program->shader.binary);
203 if (program->use_code_object_v2) {
204 const amd_kernel_code_t *code_object =
205 si_compute_get_code_object(program, 0);
206 code_object_to_config(code_object, &program->shader.config);
207 } else {
208 si_shader_binary_read_config(&program->shader.binary,
209 &program->shader.config, 0);
210 }
211 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
212 PIPE_SHADER_COMPUTE, stderr, true);
213 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
214 fprintf(stderr, "LLVM failed to upload shader\n");
215 FREE(program);
216 return NULL;
217 }
218 }
219
220 return program;
221 }
222
223 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
224 {
225 struct si_context *sctx = (struct si_context*)ctx;
226 struct si_compute *program = (struct si_compute*)state;
227
228 sctx->cs_shader_state.program = program;
229 if (!program)
230 return;
231
232 /* Wait because we need active slot usage masks. */
233 if (program->ir_type == PIPE_SHADER_IR_TGSI)
234 util_queue_fence_wait(&program->ready);
235
236 si_set_active_descriptors(sctx,
237 SI_DESCS_FIRST_COMPUTE +
238 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
239 program->active_const_and_shader_buffers);
240 si_set_active_descriptors(sctx,
241 SI_DESCS_FIRST_COMPUTE +
242 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
243 program->active_samplers_and_images);
244 }
245
246 static void si_set_global_binding(
247 struct pipe_context *ctx, unsigned first, unsigned n,
248 struct pipe_resource **resources,
249 uint32_t **handles)
250 {
251 unsigned i;
252 struct si_context *sctx = (struct si_context*)ctx;
253 struct si_compute *program = sctx->cs_shader_state.program;
254
255 assert(first + n <= MAX_GLOBAL_BUFFERS);
256
257 if (!resources) {
258 for (i = 0; i < n; i++) {
259 pipe_resource_reference(&program->global_buffers[first + i], NULL);
260 }
261 return;
262 }
263
264 for (i = 0; i < n; i++) {
265 uint64_t va;
266 uint32_t offset;
267 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
268 va = r600_resource(resources[i])->gpu_address;
269 offset = util_le32_to_cpu(*handles[i]);
270 va += offset;
271 va = util_cpu_to_le64(va);
272 memcpy(handles[i], &va, sizeof(va));
273 }
274 }
275
276 static void si_initialize_compute(struct si_context *sctx)
277 {
278 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
279 uint64_t bc_va;
280
281 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
282 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
283 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
284 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
285
286 if (sctx->b.chip_class >= CIK) {
287 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
288 radeon_set_sh_reg_seq(cs,
289 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
290 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
291 S_00B864_SH1_CU_EN(0xffff));
292 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
293 S_00B868_SH1_CU_EN(0xffff));
294 }
295
296 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
297 * and is now per pipe, so it should be handled in the
298 * kernel if we want to use something other than the default value,
299 * which is now 0x22f.
300 */
301 if (sctx->b.chip_class <= SI) {
302 /* XXX: This should be:
303 * (number of compute units) * 4 * (waves per simd) - 1 */
304
305 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
306 0x190 /* Default value */);
307 }
308
309 /* Set the pointer to border colors. */
310 bc_va = sctx->border_color_buffer->gpu_address;
311
312 if (sctx->b.chip_class >= CIK) {
313 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
314 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
315 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
316 } else {
317 if (sctx->screen->info.drm_major == 3 ||
318 (sctx->screen->info.drm_major == 2 &&
319 sctx->screen->info.drm_minor >= 48)) {
320 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
321 bc_va >> 8);
322 }
323 }
324
325 sctx->cs_shader_state.emitted_program = NULL;
326 sctx->cs_shader_state.initialized = true;
327 }
328
329 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
330 struct si_shader *shader,
331 struct si_shader_config *config)
332 {
333 uint64_t scratch_bo_size, scratch_needed;
334 scratch_bo_size = 0;
335 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
336 if (sctx->compute_scratch_buffer)
337 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
338
339 if (scratch_bo_size < scratch_needed) {
340 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
341
342 sctx->compute_scratch_buffer = (struct r600_resource*)
343 si_aligned_buffer_create(&sctx->screen->b,
344 R600_RESOURCE_FLAG_UNMAPPABLE,
345 PIPE_USAGE_DEFAULT,
346 scratch_needed, 256);
347
348 if (!sctx->compute_scratch_buffer)
349 return false;
350 }
351
352 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
353 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
354
355 si_shader_apply_scratch_relocs(shader, scratch_va);
356
357 if (si_shader_binary_upload(sctx->screen, shader))
358 return false;
359
360 r600_resource_reference(&shader->scratch_bo,
361 sctx->compute_scratch_buffer);
362 }
363
364 return true;
365 }
366
367 static bool si_switch_compute_shader(struct si_context *sctx,
368 struct si_compute *program,
369 struct si_shader *shader,
370 const amd_kernel_code_t *code_object,
371 unsigned offset)
372 {
373 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
374 struct si_shader_config inline_config = {0};
375 struct si_shader_config *config;
376 uint64_t shader_va;
377
378 if (sctx->cs_shader_state.emitted_program == program &&
379 sctx->cs_shader_state.offset == offset)
380 return true;
381
382 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
383 config = &shader->config;
384 } else {
385 unsigned lds_blocks;
386
387 config = &inline_config;
388 if (code_object) {
389 code_object_to_config(code_object, config);
390 } else {
391 si_shader_binary_read_config(&shader->binary, config, offset);
392 }
393
394 lds_blocks = config->lds_size;
395 /* XXX: We are over allocating LDS. For SI, the shader reports
396 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
397 * allocated in the shader and 4 bytes allocated by the state
398 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
399 */
400 if (sctx->b.chip_class <= SI) {
401 lds_blocks += align(program->local_size, 256) >> 8;
402 } else {
403 lds_blocks += align(program->local_size, 512) >> 9;
404 }
405
406 /* TODO: use si_multiwave_lds_size_workaround */
407 assert(lds_blocks <= 0xFF);
408
409 config->rsrc2 &= C_00B84C_LDS_SIZE;
410 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
411 }
412
413 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
414 return false;
415
416 if (shader->scratch_bo) {
417 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
418 "Total Scratch: %u bytes\n", sctx->scratch_waves,
419 config->scratch_bytes_per_wave,
420 config->scratch_bytes_per_wave *
421 sctx->scratch_waves);
422
423 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
424 shader->scratch_bo, RADEON_USAGE_READWRITE,
425 RADEON_PRIO_SCRATCH_BUFFER);
426 }
427
428 /* Prefetch the compute shader to TC L2.
429 *
430 * We should also prefetch graphics shaders if a compute dispatch was
431 * the last command, and the compute shader if a draw call was the last
432 * command. However, that would add more complexity and we're likely
433 * to get a shader state change in that case anyway.
434 */
435 if (sctx->b.chip_class >= CIK) {
436 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
437 0, program->shader.bo->b.b.width0);
438 }
439
440 shader_va = shader->bo->gpu_address + offset;
441 if (program->use_code_object_v2) {
442 /* Shader code is placed after the amd_kernel_code_t
443 * struct. */
444 shader_va += sizeof(amd_kernel_code_t);
445 }
446
447 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
448 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
449
450 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
451 radeon_emit(cs, shader_va >> 8);
452 radeon_emit(cs, shader_va >> 40);
453
454 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
455 radeon_emit(cs, config->rsrc1);
456 radeon_emit(cs, config->rsrc2);
457
458 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
459 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
460
461 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
462 S_00B860_WAVES(sctx->scratch_waves)
463 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
464
465 sctx->cs_shader_state.emitted_program = program;
466 sctx->cs_shader_state.offset = offset;
467 sctx->cs_shader_state.uses_scratch =
468 config->scratch_bytes_per_wave != 0;
469
470 return true;
471 }
472
473 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
474 const amd_kernel_code_t *code_object,
475 unsigned user_sgpr)
476 {
477 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
478 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
479
480 unsigned max_private_element_size = AMD_HSA_BITS_GET(
481 code_object->code_properties,
482 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
483
484 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
485 uint32_t scratch_dword1 =
486 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
487 S_008F04_SWIZZLE_ENABLE(1);
488
489 /* Disable address clamping */
490 uint32_t scratch_dword2 = 0xffffffff;
491 uint32_t scratch_dword3 =
492 S_008F0C_INDEX_STRIDE(3) |
493 S_008F0C_ADD_TID_ENABLE(1);
494
495 if (sctx->b.chip_class >= GFX9) {
496 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
497 } else {
498 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
499
500 if (sctx->b.chip_class < VI) {
501 /* BUF_DATA_FORMAT is ignored, but it cannot be
502 * BUF_DATA_FORMAT_INVALID. */
503 scratch_dword3 |=
504 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
505 }
506 }
507
508 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
509 (user_sgpr * 4), 4);
510 radeon_emit(cs, scratch_dword0);
511 radeon_emit(cs, scratch_dword1);
512 radeon_emit(cs, scratch_dword2);
513 radeon_emit(cs, scratch_dword3);
514 }
515
516 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
517 const amd_kernel_code_t *code_object,
518 const struct pipe_grid_info *info,
519 uint64_t kernel_args_va)
520 {
521 struct si_compute *program = sctx->cs_shader_state.program;
522 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
523
524 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
525 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
526 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
527 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
528 };
529
530 unsigned i, user_sgpr = 0;
531 if (AMD_HSA_BITS_GET(code_object->code_properties,
532 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
533 if (code_object->workitem_private_segment_byte_size > 0) {
534 setup_scratch_rsrc_user_sgprs(sctx, code_object,
535 user_sgpr);
536 }
537 user_sgpr += 4;
538 }
539
540 if (AMD_HSA_BITS_GET(code_object->code_properties,
541 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
542 struct dispatch_packet dispatch;
543 unsigned dispatch_offset;
544 struct r600_resource *dispatch_buf = NULL;
545 uint64_t dispatch_va;
546
547 /* Upload dispatch ptr */
548 memset(&dispatch, 0, sizeof(dispatch));
549
550 dispatch.workgroup_size_x = info->block[0];
551 dispatch.workgroup_size_y = info->block[1];
552 dispatch.workgroup_size_z = info->block[2];
553
554 dispatch.grid_size_x = info->grid[0] * info->block[0];
555 dispatch.grid_size_y = info->grid[1] * info->block[1];
556 dispatch.grid_size_z = info->grid[2] * info->block[2];
557
558 dispatch.private_segment_size = program->private_size;
559 dispatch.group_segment_size = program->local_size;
560
561 dispatch.kernarg_address = kernel_args_va;
562
563 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
564 256, &dispatch, &dispatch_offset,
565 (struct pipe_resource**)&dispatch_buf);
566
567 if (!dispatch_buf) {
568 fprintf(stderr, "Error: Failed to allocate dispatch "
569 "packet.");
570 }
571 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
572 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
573
574 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
575
576 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
577 (user_sgpr * 4), 2);
578 radeon_emit(cs, dispatch_va);
579 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
580 S_008F04_STRIDE(0));
581
582 r600_resource_reference(&dispatch_buf, NULL);
583 user_sgpr += 2;
584 }
585
586 if (AMD_HSA_BITS_GET(code_object->code_properties,
587 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
588 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
589 (user_sgpr * 4), 2);
590 radeon_emit(cs, kernel_args_va);
591 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
592 S_008F04_STRIDE(0));
593 user_sgpr += 2;
594 }
595
596 for (i = 0; i < 3 && user_sgpr < 16; i++) {
597 if (code_object->code_properties & workgroup_count_masks[i]) {
598 radeon_set_sh_reg_seq(cs,
599 R_00B900_COMPUTE_USER_DATA_0 +
600 (user_sgpr * 4), 1);
601 radeon_emit(cs, info->grid[i]);
602 user_sgpr += 1;
603 }
604 }
605 }
606
607 static bool si_upload_compute_input(struct si_context *sctx,
608 const amd_kernel_code_t *code_object,
609 const struct pipe_grid_info *info)
610 {
611 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
612 struct si_compute *program = sctx->cs_shader_state.program;
613 struct r600_resource *input_buffer = NULL;
614 unsigned kernel_args_size;
615 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
616 uint32_t kernel_args_offset = 0;
617 uint32_t *kernel_args;
618 void *kernel_args_ptr;
619 uint64_t kernel_args_va;
620 unsigned i;
621
622 /* The extra num_work_size_bytes are for work group / work item size information */
623 kernel_args_size = program->input_size + num_work_size_bytes;
624
625 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
626 sctx->screen->info.tcc_cache_line_size,
627 &kernel_args_offset,
628 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
629
630 if (unlikely(!kernel_args_ptr))
631 return false;
632
633 kernel_args = (uint32_t*)kernel_args_ptr;
634 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
635
636 if (!code_object) {
637 for (i = 0; i < 3; i++) {
638 kernel_args[i] = info->grid[i];
639 kernel_args[i + 3] = info->grid[i] * info->block[i];
640 kernel_args[i + 6] = info->block[i];
641 }
642 }
643
644 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
645 program->input_size);
646
647
648 for (i = 0; i < (kernel_args_size / 4); i++) {
649 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
650 kernel_args[i]);
651 }
652
653
654 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
655 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
656
657 if (code_object) {
658 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
659 } else {
660 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
661 radeon_emit(cs, kernel_args_va);
662 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
663 S_008F04_STRIDE(0));
664 }
665
666 r600_resource_reference(&input_buffer, NULL);
667
668 return true;
669 }
670
671 static void si_setup_tgsi_grid(struct si_context *sctx,
672 const struct pipe_grid_info *info)
673 {
674 struct si_compute *program = sctx->cs_shader_state.program;
675 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
676 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
677 4 * SI_NUM_RESOURCE_SGPRS;
678 unsigned block_size_reg = grid_size_reg +
679 /* 12 bytes = 3 dwords. */
680 12 * program->uses_grid_size;
681
682 if (info->indirect) {
683 if (program->uses_grid_size) {
684 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
685 uint64_t va = base_va + info->indirect_offset;
686 int i;
687
688 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
689 (struct r600_resource *)info->indirect,
690 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
691
692 for (i = 0; i < 3; ++i) {
693 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
694 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
695 COPY_DATA_DST_SEL(COPY_DATA_REG));
696 radeon_emit(cs, (va + 4 * i));
697 radeon_emit(cs, (va + 4 * i) >> 32);
698 radeon_emit(cs, (grid_size_reg >> 2) + i);
699 radeon_emit(cs, 0);
700 }
701 }
702 } else {
703 if (program->uses_grid_size) {
704 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
705 radeon_emit(cs, info->grid[0]);
706 radeon_emit(cs, info->grid[1]);
707 radeon_emit(cs, info->grid[2]);
708 }
709 if (program->variable_group_size && program->uses_block_size) {
710 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
711 radeon_emit(cs, info->block[0]);
712 radeon_emit(cs, info->block[1]);
713 radeon_emit(cs, info->block[2]);
714 }
715 }
716 }
717
718 static void si_emit_dispatch_packets(struct si_context *sctx,
719 const struct pipe_grid_info *info)
720 {
721 struct si_screen *sscreen = sctx->screen;
722 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
723 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
724 unsigned waves_per_threadgroup =
725 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
726 unsigned compute_resource_limits =
727 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
728
729 if (sctx->b.chip_class >= CIK) {
730 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
731 sscreen->info.max_se;
732
733 /* Force even distribution on all SIMDs in CU if the workgroup
734 * size is 64. This has shown some good improvements if # of CUs
735 * per SE is not a multiple of 4.
736 */
737 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
738 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
739 }
740
741 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
742 compute_resource_limits);
743
744 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
745 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
746 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
747 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
748
749 unsigned dispatch_initiator =
750 S_00B800_COMPUTE_SHADER_EN(1) |
751 S_00B800_FORCE_START_AT_000(1) |
752 /* If the KMD allows it (there is a KMD hw register for it),
753 * allow launching waves out-of-order. (same as Vulkan) */
754 S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK);
755
756 if (info->indirect) {
757 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
758
759 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
760 (struct r600_resource *)info->indirect,
761 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
762
763 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
764 PKT3_SHADER_TYPE_S(1));
765 radeon_emit(cs, 1);
766 radeon_emit(cs, base_va);
767 radeon_emit(cs, base_va >> 32);
768
769 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
770 PKT3_SHADER_TYPE_S(1));
771 radeon_emit(cs, info->indirect_offset);
772 radeon_emit(cs, dispatch_initiator);
773 } else {
774 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
775 PKT3_SHADER_TYPE_S(1));
776 radeon_emit(cs, info->grid[0]);
777 radeon_emit(cs, info->grid[1]);
778 radeon_emit(cs, info->grid[2]);
779 radeon_emit(cs, dispatch_initiator);
780 }
781 }
782
783
784 static void si_launch_grid(
785 struct pipe_context *ctx, const struct pipe_grid_info *info)
786 {
787 struct si_context *sctx = (struct si_context*)ctx;
788 struct si_compute *program = sctx->cs_shader_state.program;
789 const amd_kernel_code_t *code_object =
790 si_compute_get_code_object(program, info->pc);
791 int i;
792 /* HW bug workaround when CS threadgroups > 256 threads and async
793 * compute isn't used, i.e. only one compute job can run at a time.
794 * If async compute is possible, the threadgroup size must be limited
795 * to 256 threads on all queues to avoid the bug.
796 * Only SI and certain CIK chips are affected.
797 */
798 bool cs_regalloc_hang =
799 (sctx->b.chip_class == SI ||
800 sctx->b.family == CHIP_BONAIRE ||
801 sctx->b.family == CHIP_KABINI) &&
802 info->block[0] * info->block[1] * info->block[2] > 256;
803
804 if (cs_regalloc_hang)
805 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
806 SI_CONTEXT_CS_PARTIAL_FLUSH;
807
808 if (program->ir_type == PIPE_SHADER_IR_TGSI &&
809 program->shader.compilation_failed)
810 return;
811
812 if (sctx->b.last_num_draw_calls != sctx->b.num_draw_calls) {
813 si_update_fb_dirtiness_after_rendering(sctx);
814 sctx->b.last_num_draw_calls = sctx->b.num_draw_calls;
815 }
816
817 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
818
819 /* Add buffer sizes for memory checking in need_cs_space. */
820 si_context_add_resource_size(ctx, &program->shader.bo->b.b);
821 /* TODO: add the scratch buffer */
822
823 if (info->indirect) {
824 si_context_add_resource_size(ctx, info->indirect);
825
826 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
827 if (sctx->b.chip_class <= VI &&
828 r600_resource(info->indirect)->TC_L2_dirty) {
829 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
830 r600_resource(info->indirect)->TC_L2_dirty = false;
831 }
832 }
833
834 si_need_cs_space(sctx);
835
836 if (!sctx->cs_shader_state.initialized)
837 si_initialize_compute(sctx);
838
839 if (sctx->b.flags)
840 si_emit_cache_flush(sctx);
841
842 if (!si_switch_compute_shader(sctx, program, &program->shader,
843 code_object, info->pc))
844 return;
845
846 si_upload_compute_shader_descriptors(sctx);
847 si_emit_compute_shader_pointers(sctx);
848
849 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
850 sctx->atoms.s.render_cond->emit(&sctx->b,
851 sctx->atoms.s.render_cond);
852 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
853 }
854
855 if ((program->input_size ||
856 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
857 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
858 return;
859 }
860
861 /* Global buffers */
862 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
863 struct r600_resource *buffer =
864 (struct r600_resource*)program->global_buffers[i];
865 if (!buffer) {
866 continue;
867 }
868 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
869 RADEON_USAGE_READWRITE,
870 RADEON_PRIO_COMPUTE_GLOBAL);
871 }
872
873 if (program->ir_type == PIPE_SHADER_IR_TGSI)
874 si_setup_tgsi_grid(sctx, info);
875
876 si_emit_dispatch_packets(sctx, info);
877
878 if (unlikely(sctx->current_saved_cs)) {
879 si_trace_emit(sctx);
880 si_log_compute_state(sctx, sctx->b.log);
881 }
882
883 sctx->compute_is_busy = true;
884 sctx->b.num_compute_calls++;
885 if (sctx->cs_shader_state.uses_scratch)
886 sctx->b.num_spill_compute_calls++;
887
888 if (cs_regalloc_hang)
889 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
890 }
891
892 void si_destroy_compute(struct si_compute *program)
893 {
894 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
895 util_queue_drop_job(&program->screen->shader_compiler_queue,
896 &program->ready);
897 util_queue_fence_destroy(&program->ready);
898 }
899
900 si_shader_destroy(&program->shader);
901 FREE(program);
902 }
903
904 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
905 struct si_compute *program = (struct si_compute *)state;
906 struct si_context *sctx = (struct si_context*)ctx;
907
908 if (!state)
909 return;
910
911 if (program == sctx->cs_shader_state.program)
912 sctx->cs_shader_state.program = NULL;
913
914 if (program == sctx->cs_shader_state.emitted_program)
915 sctx->cs_shader_state.emitted_program = NULL;
916
917 si_compute_reference(&program, NULL);
918 }
919
920 static void si_set_compute_resources(struct pipe_context * ctx_,
921 unsigned start, unsigned count,
922 struct pipe_surface ** surfaces) { }
923
924 void si_init_compute_functions(struct si_context *sctx)
925 {
926 sctx->b.b.create_compute_state = si_create_compute_state;
927 sctx->b.b.delete_compute_state = si_delete_compute_state;
928 sctx->b.b.bind_compute_state = si_bind_compute_state;
929 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
930 sctx->b.b.set_compute_resources = si_set_compute_resources;
931 sctx->b.b.set_global_binding = si_set_global_binding;
932 sctx->b.b.launch_grid = si_launch_grid;
933 }