src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "radeon/r600_pipe_common.h"
  29 #include "radeon/radeon_elf_util.h"
  30
  31 #include "radeon/r600_cs.h"
  32 #include "si_pipe.h"
  33 #include "si_shader.h"
  34 #include "sid.h"
  35
  36 #define MAX_GLOBAL_BUFFERS 20
  37
  38 struct si_compute {
  39         unsigned ir_type;
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44
  45         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  46 };
  47
  48 static void *si_create_compute_state(
  49         struct pipe_context *ctx,
  50         const struct pipe_compute_state *cso)
  51 {
  52         struct si_context *sctx = (struct si_context *)ctx;
  53         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  54         struct si_compute *program = CALLOC_STRUCT(si_compute);
  55         struct si_shader *shader = &program->shader;
  56
  57
  58         program->ir_type = cso->ir_type;
  59         program->local_size = cso->req_local_mem;
  60         program->private_size = cso->req_private_mem;
  61         program->input_size = cso->req_input_mem;
  62
  63
  64         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
  65                 struct si_shader_selector sel;
  66                 bool scratch_enabled;
  67
  68                 memset(&sel, 0, sizeof(sel));
  69
  70                 sel.tokens = tgsi_dup_tokens(cso->prog);
  71                 if (!sel.tokens) {
  72                         FREE(program);
  73                         return NULL;
  74                 }
  75
  76                 tgsi_scan_shader(cso->prog, &sel.info);
  77                 sel.type = PIPE_SHADER_COMPUTE;
  78                 sel.local_size = cso->req_local_mem;
  79
  80                 p_atomic_inc(&sscreen->b.num_shaders_created);
  81
  82                 program->shader.selector = &sel;
  83
  84                 if (si_shader_create(sscreen, sctx->tm, &program->shader,
  85                                      &sctx->b.debug)) {
  86                         FREE(sel.tokens);
  87                         FREE(program);
  88                         return NULL;
  89                 }
  90
  91                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
  92
  93                 shader->config.rsrc1 =
  94                            S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
  95                            S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
  96                            S_00B848_DX10_CLAMP(1) |
  97                            S_00B848_FLOAT_MODE(shader->config.float_mode);
  98
  99                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
 100                            S_00B84C_SCRATCH_EN(scratch_enabled) |
 101                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 102                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 103                            S_00B84C_LDS_SIZE(shader->config.lds_size);
 104
 105                 FREE(sel.tokens);
 106         } else {
 107                 const struct pipe_llvm_program_header *header;
 108                 const char *code;
 109                 header = cso->prog;
 110                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 111
 112                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 113                 si_shader_binary_read_config(&program->shader.binary,
 114                              &program->shader.config, 0);
 115                 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 116                                PIPE_SHADER_COMPUTE, stderr);
 117                 si_shader_binary_upload(sctx->screen, &program->shader);
 118         }
 119
 120         return program;
 121 }
 122
 123 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 124 {
 125         struct si_context *sctx = (struct si_context*)ctx;
 126         sctx->cs_shader_state.program = (struct si_compute*)state;
 127 }
 128
 129 static void si_set_global_binding(
 130         struct pipe_context *ctx, unsigned first, unsigned n,
 131         struct pipe_resource **resources,
 132         uint32_t **handles)
 133 {
 134         unsigned i;
 135         struct si_context *sctx = (struct si_context*)ctx;
 136         struct si_compute *program = sctx->cs_shader_state.program;
 137
 138         if (!resources) {
 139                 for (i = first; i < first + n; i++) {
 140                         pipe_resource_reference(&program->global_buffers[i], NULL);
 141                 }
 142                 return;
 143         }
 144
 145         for (i = first; i < first + n; i++) {
 146                 uint64_t va;
 147                 uint32_t offset;
 148                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 149                 va = r600_resource(resources[i])->gpu_address;
 150                 offset = util_le32_to_cpu(*handles[i]);
 151                 va += offset;
 152                 va = util_cpu_to_le64(va);
 153                 memcpy(handles[i], &va, sizeof(va));
 154         }
 155 }
 156
 157 static void si_initialize_compute(struct si_context *sctx)
 158 {
 159         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 160
 161         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
 162         radeon_emit(cs, 0);
 163         radeon_emit(cs, 0);
 164         radeon_emit(cs, 0);
 165
 166         radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 167         /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
 168         radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 169         radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
 170
 171         if (sctx->b.chip_class >= CIK) {
 172                 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 173                 radeon_set_sh_reg_seq(cs,
 174                                      R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 175                 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
 176                                 S_00B864_SH1_CU_EN(0xffff));
 177                 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
 178                                 S_00B868_SH1_CU_EN(0xffff));
 179         }
 180
 181         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 182          * and is now per pipe, so it should be handled in the
 183          * kernel if we want to use something other than the default value,
 184          * which is now 0x22f.
 185          */
 186         if (sctx->b.chip_class <= SI) {
 187                 /* XXX: This should be:
 188                  * (number of compute units) * 4 * (waves per simd) - 1 */
 189
 190                 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
 191                                   0x190 /* Default value */);
 192         }
 193
 194         sctx->cs_shader_state.emitted_program = NULL;
 195         sctx->cs_shader_state.initialized = true;
 196 }
 197
 198 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 199                                             struct si_shader *shader,
 200                                             struct si_shader_config *config)
 201 {
 202         uint64_t scratch_bo_size, scratch_needed;
 203         scratch_bo_size = 0;
 204         scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 205         if (sctx->compute_scratch_buffer)
 206                 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 207
 208         if (scratch_bo_size < scratch_needed) {
 209                 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
 210
 211                 sctx->compute_scratch_buffer =
 212                                 si_resource_create_custom(&sctx->screen->b.b,
 213                                 PIPE_USAGE_DEFAULT, scratch_needed);
 214
 215                 if (!sctx->compute_scratch_buffer)
 216                         return false;
 217         }
 218
 219         if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 220                 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 221
 222                 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
 223
 224                 if (si_shader_binary_upload(sctx->screen, shader))
 225                         return false;
 226
 227                 r600_resource_reference(&shader->scratch_bo,
 228                                         sctx->compute_scratch_buffer);
 229         }
 230
 231         return true;
 232 }
 233
 234 static bool si_switch_compute_shader(struct si_context *sctx,
 235                                      struct si_compute *program,
 236                                      struct si_shader *shader, unsigned offset)
 237 {
 238         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 239         struct si_shader_config inline_config = {0};
 240         struct si_shader_config *config;
 241         uint64_t shader_va;
 242
 243         if (sctx->cs_shader_state.emitted_program == program &&
 244             sctx->cs_shader_state.offset == offset)
 245                 return true;
 246
 247         if (program->ir_type == PIPE_SHADER_IR_TGSI) {
 248                 config = &shader->config;
 249         } else {
 250                 unsigned lds_blocks;
 251
 252                 config = &inline_config;
 253                 si_shader_binary_read_config(&shader->binary, config, offset);
 254
 255                 lds_blocks = config->lds_size;
 256                 /* XXX: We are over allocating LDS.  For SI, the shader reports
 257                 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 258                 * allocated in the shader and 4 bytes allocated by the state
 259                 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 260                 */
 261                 if (sctx->b.chip_class <= SI) {
 262                         lds_blocks += align(program->local_size, 256) >> 8;
 263                 } else {
 264                         lds_blocks += align(program->local_size, 512) >> 9;
 265                 }
 266
 267                 assert(lds_blocks <= 0xFF);
 268
 269                 config->rsrc2 &= C_00B84C_LDS_SIZE;
 270                 config->rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 271         }
 272
 273         if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 274                 return false;
 275
 276         if (shader->scratch_bo) {
 277                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 278                             "Total Scratch: %u bytes\n", sctx->scratch_waves,
 279                             config->scratch_bytes_per_wave,
 280                             config->scratch_bytes_per_wave *
 281                             sctx->scratch_waves);
 282
 283                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 284                               shader->scratch_bo, RADEON_USAGE_READWRITE,
 285                               RADEON_PRIO_SCRATCH_BUFFER);
 286         }
 287
 288         shader_va = shader->bo->gpu_address + offset;
 289
 290         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 291                                   RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 292
 293         radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 294         radeon_emit(cs, shader_va >> 8);
 295         radeon_emit(cs, shader_va >> 40);
 296
 297         radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 298         radeon_emit(cs, config->rsrc1);
 299         radeon_emit(cs, config->rsrc2);
 300
 301         radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 302                   S_00B860_WAVES(sctx->scratch_waves)
 303                      | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
 304
 305         sctx->cs_shader_state.emitted_program = program;
 306         sctx->cs_shader_state.offset = offset;
 307         sctx->cs_shader_state.uses_scratch =
 308                 config->scratch_bytes_per_wave != 0;
 309
 310         return true;
 311 }
 312
 313 static void si_upload_compute_input(struct si_context *sctx,
 314                                   const struct pipe_grid_info *info)
 315 {
 316         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 317         struct si_compute *program = sctx->cs_shader_state.program;
 318         struct r600_resource *input_buffer = NULL;
 319         unsigned kernel_args_size;
 320         unsigned num_work_size_bytes = 36;
 321         uint32_t kernel_args_offset = 0;
 322         uint32_t *kernel_args;
 323         void *kernel_args_ptr;
 324         uint64_t kernel_args_va;
 325         unsigned i;
 326
 327         /* The extra num_work_size_bytes are for work group / work item size information */
 328         kernel_args_size = program->input_size + num_work_size_bytes;
 329
 330         u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
 331                        &kernel_args_offset,
 332                        (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 333
 334         kernel_args = (uint32_t*)kernel_args_ptr;
 335         for (i = 0; i < 3; i++) {
 336                 kernel_args[i] = info->grid[i];
 337                 kernel_args[i + 3] = info->grid[i] * info->block[i];
 338                 kernel_args[i + 6] = info->block[i];
 339         }
 340
 341         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 342                program->input_size);
 343
 344
 345         for (i = 0; i < (kernel_args_size / 4); i++) {
 346                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 347                         kernel_args[i]);
 348         }
 349
 350         kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 351
 352         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 353                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 354
 355         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 356         radeon_emit(cs, kernel_args_va);
 357         radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 358                         S_008F04_STRIDE(0));
 359
 360         r600_resource_reference(&input_buffer, NULL);
 361 }
 362
 363 static void si_setup_tgsi_grid(struct si_context *sctx,
 364                                 const struct pipe_grid_info *info)
 365 {
 366         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 367         unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
 368                                   4 * SI_SGPR_GRID_SIZE;
 369
 370         if (info->indirect) {
 371                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 372                 uint64_t va = base_va + info->indirect_offset;
 373                 int i;
 374
 375                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 376                                  (struct r600_resource *)info->indirect,
 377                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 378
 379                 for (i = 0; i < 3; ++i) {
 380                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 381                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 382                                         COPY_DATA_DST_SEL(COPY_DATA_REG));
 383                         radeon_emit(cs, (va +  4 * i));
 384                         radeon_emit(cs, (va + 4 * i) >> 32);
 385                         radeon_emit(cs, (grid_size_reg >> 2) + i);
 386                         radeon_emit(cs, 0);
 387                 }
 388         } else {
 389
 390                 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 391                 radeon_emit(cs, info->grid[0]);
 392                 radeon_emit(cs, info->grid[1]);
 393                 radeon_emit(cs, info->grid[2]);
 394         }
 395 }
 396
 397 static void si_emit_dispatch_packets(struct si_context *sctx,
 398                                      const struct pipe_grid_info *info)
 399 {
 400         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 401         bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 402         unsigned waves_per_threadgroup =
 403                 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
 404
 405         radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 406                           S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
 407
 408         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 409         radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 410         radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 411         radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 412
 413         if (info->indirect) {
 414                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 415
 416                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 417                                  (struct r600_resource *)info->indirect,
 418                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 419
 420                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
 421                                 PKT3_SHADER_TYPE_S(1));
 422                 radeon_emit(cs, 1);
 423                 radeon_emit(cs, base_va);
 424                 radeon_emit(cs, base_va >> 32);
 425
 426                 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
 427                                 PKT3_SHADER_TYPE_S(1));
 428                 radeon_emit(cs, info->indirect_offset);
 429                 radeon_emit(cs, 1);
 430         } else {
 431                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
 432                                 PKT3_SHADER_TYPE_S(1));
 433                 radeon_emit(cs, info->grid[0]);
 434                 radeon_emit(cs, info->grid[1]);
 435                 radeon_emit(cs, info->grid[2]);
 436                 radeon_emit(cs, 1);
 437         }
 438 }
 439
 440
 441 static void si_launch_grid(
 442                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 443 {
 444         struct si_context *sctx = (struct si_context*)ctx;
 445         struct si_compute *program = sctx->cs_shader_state.program;
 446         int i;
 447         /* HW bug workaround when CS threadgroups > 256 threads and async
 448          * compute isn't used, i.e. only one compute job can run at a time.
 449          * If async compute is possible, the threadgroup size must be limited
 450          * to 256 threads on all queues to avoid the bug.
 451          * Only SI and certain CIK chips are affected.
 452          */
 453         bool cs_regalloc_hang =
 454                 (sctx->b.chip_class == SI ||
 455                  sctx->b.family == CHIP_BONAIRE ||
 456                  sctx->b.family == CHIP_KABINI) &&
 457                 info->block[0] * info->block[1] * info->block[2] > 256;
 458
 459         if (cs_regalloc_hang)
 460                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 461                                  SI_CONTEXT_CS_PARTIAL_FLUSH;
 462
 463         si_decompress_compute_textures(sctx);
 464
 465         /* Add buffer sizes for memory checking in need_cs_space. */
 466         r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
 467         if (info->indirect)
 468                 r600_context_add_resource_size(ctx, info->indirect);
 469         /* TODO: add the scratch buffer */
 470
 471         si_need_cs_space(sctx);
 472
 473         if (!sctx->cs_shader_state.initialized)
 474                 si_initialize_compute(sctx);
 475
 476         if (sctx->b.flags)
 477                 si_emit_cache_flush(sctx, NULL);
 478
 479         if (!si_switch_compute_shader(sctx, program, &program->shader, info->pc))
 480                 return;
 481
 482         si_upload_compute_shader_descriptors(sctx);
 483         si_emit_compute_shader_userdata(sctx);
 484
 485         if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
 486                 sctx->atoms.s.render_cond->emit(&sctx->b,
 487                                                 sctx->atoms.s.render_cond);
 488                 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
 489         }
 490
 491         if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
 492                 si_upload_compute_input(sctx, info);
 493
 494         /* Global buffers */
 495         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 496                 struct r600_resource *buffer =
 497                                 (struct r600_resource*)program->global_buffers[i];
 498                 if (!buffer) {
 499                         continue;
 500                 }
 501                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 502                                           RADEON_USAGE_READWRITE,
 503                                           RADEON_PRIO_COMPUTE_GLOBAL);
 504         }
 505
 506         if (program->ir_type == PIPE_SHADER_IR_TGSI)
 507                 si_setup_tgsi_grid(sctx, info);
 508
 509         si_ce_pre_draw_synchronization(sctx);
 510
 511         si_emit_dispatch_packets(sctx, info);
 512
 513         si_ce_post_draw_synchronization(sctx);
 514
 515         sctx->compute_is_busy = true;
 516         sctx->b.num_compute_calls++;
 517         if (sctx->cs_shader_state.uses_scratch)
 518                 sctx->b.num_spill_compute_calls++;
 519
 520         if (cs_regalloc_hang)
 521                 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 522 }
 523
 524
 525 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 526         struct si_compute *program = (struct si_compute *)state;
 527         struct si_context *sctx = (struct si_context*)ctx;
 528
 529         if (!state) {
 530                 return;
 531         }
 532
 533         if (program == sctx->cs_shader_state.program)
 534                 sctx->cs_shader_state.program = NULL;
 535
 536         if (program == sctx->cs_shader_state.emitted_program)
 537                 sctx->cs_shader_state.emitted_program = NULL;
 538
 539         si_shader_destroy(&program->shader);
 540         FREE(program);
 541 }
 542
 543 static void si_set_compute_resources(struct pipe_context * ctx_,
 544                 unsigned start, unsigned count,
 545                 struct pipe_surface ** surfaces) { }
 546
 547 void si_init_compute_functions(struct si_context *sctx)
 548 {
 549         sctx->b.b.create_compute_state = si_create_compute_state;
 550         sctx->b.b.delete_compute_state = si_delete_compute_state;
 551         sctx->b.b.bind_compute_state = si_bind_compute_state;
 552 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 553         sctx->b.b.set_compute_resources = si_set_compute_resources;
 554         sctx->b.b.set_global_binding = si_set_global_binding;
 555         sctx->b.b.launch_grid = si_launch_grid;
 556 }