src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "radeon/r600_pipe_common.h"
  29 #include "radeon/radeon_elf_util.h"
  30
  31 #include "amd_kernel_code_t.h"
  32 #include "radeon/r600_cs.h"
  33 #include "si_pipe.h"
  34 #include "si_shader.h"
  35 #include "sid.h"
  36
  37 #define MAX_GLOBAL_BUFFERS 20
  38
  39 struct si_compute {
  40         unsigned ir_type;
  41         unsigned local_size;
  42         unsigned private_size;
  43         unsigned input_size;
  44         struct si_shader shader;
  45
  46         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  47         bool use_code_object_v2;
  48 };
  49
  50 struct dispatch_packet {
  51         uint16_t header;
  52         uint16_t setup;
  53         uint16_t workgroup_size_x;
  54         uint16_t workgroup_size_y;
  55         uint16_t workgroup_size_z;
  56         uint16_t reserved0;
  57         uint32_t grid_size_x;
  58         uint32_t grid_size_y;
  59         uint32_t grid_size_z;
  60         uint32_t private_segment_size;
  61         uint32_t group_segment_size;
  62         uint64_t kernel_object;
  63         uint64_t kernarg_address;
  64         uint64_t reserved2;
  65 };
  66
  67 static const amd_kernel_code_t *si_compute_get_code_object(
  68         const struct si_compute *program,
  69         uint64_t symbol_offset)
  70 {
  71         if (!program->use_code_object_v2) {
  72                 return NULL;
  73         }
  74         return (const amd_kernel_code_t*)
  75                 (program->shader.binary.code + symbol_offset);
  76 }
  77
  78 static void code_object_to_config(const amd_kernel_code_t *code_object,
  79                                   struct si_shader_config *out_config) {
  80
  81         uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
  82         uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
  83         out_config->num_sgprs = code_object->wavefront_sgpr_count;
  84         out_config->num_vgprs = code_object->workitem_vgpr_count;
  85         out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
  86         out_config->rsrc1 = rsrc1;
  87         out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
  88         out_config->rsrc2 = rsrc2;
  89         out_config->scratch_bytes_per_wave =
  90                 align(code_object->workitem_private_segment_byte_size * 64, 1024);
  91 }
  92
  93 static void *si_create_compute_state(
  94         struct pipe_context *ctx,
  95         const struct pipe_compute_state *cso)
  96 {
  97         struct si_context *sctx = (struct si_context *)ctx;
  98         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  99         struct si_compute *program = CALLOC_STRUCT(si_compute);
 100         struct si_shader *shader = &program->shader;
 101
 102
 103         program->ir_type = cso->ir_type;
 104         program->local_size = cso->req_local_mem;
 105         program->private_size = cso->req_private_mem;
 106         program->input_size = cso->req_input_mem;
 107         program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
 108                                         cso->ir_type == PIPE_SHADER_IR_NATIVE;
 109
 110
 111         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 112                 struct si_shader_selector sel;
 113                 bool scratch_enabled;
 114
 115                 memset(&sel, 0, sizeof(sel));
 116
 117                 sel.tokens = tgsi_dup_tokens(cso->prog);
 118                 if (!sel.tokens) {
 119                         FREE(program);
 120                         return NULL;
 121                 }
 122
 123                 tgsi_scan_shader(cso->prog, &sel.info);
 124                 sel.type = PIPE_SHADER_COMPUTE;
 125                 sel.local_size = cso->req_local_mem;
 126
 127                 p_atomic_inc(&sscreen->b.num_shaders_created);
 128
 129                 program->shader.selector = &sel;
 130
 131                 if (si_shader_create(sscreen, sctx->tm, &program->shader,
 132                                      &sctx->b.debug)) {
 133                         FREE(sel.tokens);
 134                         FREE(program);
 135                         return NULL;
 136                 }
 137
 138                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 139
 140                 shader->config.rsrc1 =
 141                            S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
 142                            S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
 143                            S_00B848_DX10_CLAMP(1) |
 144                            S_00B848_FLOAT_MODE(shader->config.float_mode);
 145
 146                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
 147                            S_00B84C_SCRATCH_EN(scratch_enabled) |
 148                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 149                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 150                            S_00B84C_LDS_SIZE(shader->config.lds_size);
 151
 152                 FREE(sel.tokens);
 153         } else {
 154                 const struct pipe_llvm_program_header *header;
 155                 const char *code;
 156                 header = cso->prog;
 157                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 158
 159                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 160                 if (program->use_code_object_v2) {
 161                         const amd_kernel_code_t *code_object =
 162                                 si_compute_get_code_object(program, 0);
 163                         code_object_to_config(code_object, &program->shader.config);
 164                 } else {
 165                         si_shader_binary_read_config(&program->shader.binary,
 166                                      &program->shader.config, 0);
 167                 }
 168                 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 169                                PIPE_SHADER_COMPUTE, stderr);
 170                 si_shader_binary_upload(sctx->screen, &program->shader);
 171         }
 172
 173         return program;
 174 }
 175
 176 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 177 {
 178         struct si_context *sctx = (struct si_context*)ctx;
 179         sctx->cs_shader_state.program = (struct si_compute*)state;
 180 }
 181
 182 static void si_set_global_binding(
 183         struct pipe_context *ctx, unsigned first, unsigned n,
 184         struct pipe_resource **resources,
 185         uint32_t **handles)
 186 {
 187         unsigned i;
 188         struct si_context *sctx = (struct si_context*)ctx;
 189         struct si_compute *program = sctx->cs_shader_state.program;
 190
 191         if (!resources) {
 192                 for (i = first; i < first + n; i++) {
 193                         pipe_resource_reference(&program->global_buffers[i], NULL);
 194                 }
 195                 return;
 196         }
 197
 198         for (i = first; i < first + n; i++) {
 199                 uint64_t va;
 200                 uint32_t offset;
 201                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 202                 va = r600_resource(resources[i])->gpu_address;
 203                 offset = util_le32_to_cpu(*handles[i]);
 204                 va += offset;
 205                 va = util_cpu_to_le64(va);
 206                 memcpy(handles[i], &va, sizeof(va));
 207         }
 208 }
 209
 210 static void si_initialize_compute(struct si_context *sctx)
 211 {
 212         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 213
 214         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
 215         radeon_emit(cs, 0);
 216         radeon_emit(cs, 0);
 217         radeon_emit(cs, 0);
 218
 219         radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 220         /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
 221         radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 222         radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
 223
 224         if (sctx->b.chip_class >= CIK) {
 225                 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 226                 radeon_set_sh_reg_seq(cs,
 227                                      R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 228                 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
 229                                 S_00B864_SH1_CU_EN(0xffff));
 230                 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
 231                                 S_00B868_SH1_CU_EN(0xffff));
 232         }
 233
 234         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 235          * and is now per pipe, so it should be handled in the
 236          * kernel if we want to use something other than the default value,
 237          * which is now 0x22f.
 238          */
 239         if (sctx->b.chip_class <= SI) {
 240                 /* XXX: This should be:
 241                  * (number of compute units) * 4 * (waves per simd) - 1 */
 242
 243                 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
 244                                   0x190 /* Default value */);
 245         }
 246
 247         sctx->cs_shader_state.emitted_program = NULL;
 248         sctx->cs_shader_state.initialized = true;
 249 }
 250
 251 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 252                                             struct si_shader *shader,
 253                                             struct si_shader_config *config)
 254 {
 255         uint64_t scratch_bo_size, scratch_needed;
 256         scratch_bo_size = 0;
 257         scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 258         if (sctx->compute_scratch_buffer)
 259                 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 260
 261         if (scratch_bo_size < scratch_needed) {
 262                 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
 263
 264                 sctx->compute_scratch_buffer =
 265                                 si_resource_create_custom(&sctx->screen->b.b,
 266                                 PIPE_USAGE_DEFAULT, scratch_needed);
 267
 268                 if (!sctx->compute_scratch_buffer)
 269                         return false;
 270         }
 271
 272         if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 273                 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 274
 275                 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
 276
 277                 if (si_shader_binary_upload(sctx->screen, shader))
 278                         return false;
 279
 280                 r600_resource_reference(&shader->scratch_bo,
 281                                         sctx->compute_scratch_buffer);
 282         }
 283
 284         return true;
 285 }
 286
 287 static bool si_switch_compute_shader(struct si_context *sctx,
 288                                      struct si_compute *program,
 289                                      struct si_shader *shader,
 290                                      const amd_kernel_code_t *code_object,
 291                                      unsigned offset)
 292 {
 293         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 294         struct si_shader_config inline_config = {0};
 295         struct si_shader_config *config;
 296         uint64_t shader_va;
 297
 298         if (sctx->cs_shader_state.emitted_program == program &&
 299             sctx->cs_shader_state.offset == offset)
 300                 return true;
 301
 302         if (program->ir_type == PIPE_SHADER_IR_TGSI) {
 303                 config = &shader->config;
 304         } else {
 305                 unsigned lds_blocks;
 306
 307                 config = &inline_config;
 308                 if (code_object) {
 309                         code_object_to_config(code_object, config);
 310                 } else {
 311                         si_shader_binary_read_config(&shader->binary, config, offset);
 312                 }
 313
 314                 lds_blocks = config->lds_size;
 315                 /* XXX: We are over allocating LDS.  For SI, the shader reports
 316                 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 317                 * allocated in the shader and 4 bytes allocated by the state
 318                 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 319                 */
 320                 if (sctx->b.chip_class <= SI) {
 321                         lds_blocks += align(program->local_size, 256) >> 8;
 322                 } else {
 323                         lds_blocks += align(program->local_size, 512) >> 9;
 324                 }
 325
 326                 assert(lds_blocks <= 0xFF);
 327
 328                 config->rsrc2 &= C_00B84C_LDS_SIZE;
 329                 config->rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 330         }
 331
 332         if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 333                 return false;
 334
 335         if (shader->scratch_bo) {
 336                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 337                             "Total Scratch: %u bytes\n", sctx->scratch_waves,
 338                             config->scratch_bytes_per_wave,
 339                             config->scratch_bytes_per_wave *
 340                             sctx->scratch_waves);
 341
 342                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 343                               shader->scratch_bo, RADEON_USAGE_READWRITE,
 344                               RADEON_PRIO_SCRATCH_BUFFER);
 345         }
 346
 347         shader_va = shader->bo->gpu_address + offset;
 348         if (program->use_code_object_v2) {
 349                 /* Shader code is placed after the amd_kernel_code_t
 350                  * struct. */
 351                 shader_va += sizeof(amd_kernel_code_t);
 352         }
 353
 354         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 355                                   RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 356
 357         radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 358         radeon_emit(cs, shader_va >> 8);
 359         radeon_emit(cs, shader_va >> 40);
 360
 361         radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 362         radeon_emit(cs, config->rsrc1);
 363         radeon_emit(cs, config->rsrc2);
 364
 365         COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
 366                 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
 367
 368         radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 369                   S_00B860_WAVES(sctx->scratch_waves)
 370                      | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
 371
 372         sctx->cs_shader_state.emitted_program = program;
 373         sctx->cs_shader_state.offset = offset;
 374         sctx->cs_shader_state.uses_scratch =
 375                 config->scratch_bytes_per_wave != 0;
 376
 377         return true;
 378 }
 379
 380 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 381                                           const amd_kernel_code_t *code_object,
 382                                           unsigned user_sgpr)
 383 {
 384         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 385         uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 386
 387         unsigned max_private_element_size = AMD_HSA_BITS_GET(
 388                         code_object->code_properties,
 389                         AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 390
 391         uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 392         uint32_t scratch_dword1 =
 393                 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
 394                 S_008F04_SWIZZLE_ENABLE(1);
 395
 396         /* Disable address clamping */
 397         uint32_t scratch_dword2 = 0xffffffff;
 398         uint32_t scratch_dword3 =
 399                 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
 400                 S_008F0C_INDEX_STRIDE(3) |
 401                 S_008F0C_ADD_TID_ENABLE(1);
 402
 403
 404         if (sctx->screen->b.chip_class < VI) {
 405                 /* BUF_DATA_FORMAT is ignored, but it cannot be
 406                    BUF_DATA_FORMAT_INVALID. */
 407                 scratch_dword3 |=
 408                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
 409         }
 410
 411         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 412                                                         (user_sgpr * 4), 4);
 413         radeon_emit(cs, scratch_dword0);
 414         radeon_emit(cs, scratch_dword1);
 415         radeon_emit(cs, scratch_dword2);
 416         radeon_emit(cs, scratch_dword3);
 417 }
 418
 419 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
 420                                       const amd_kernel_code_t *code_object,
 421                                       const struct pipe_grid_info *info,
 422                                       uint64_t kernel_args_va)
 423 {
 424         struct si_compute *program = sctx->cs_shader_state.program;
 425         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 426
 427         static const enum amd_code_property_mask_t workgroup_count_masks [] = {
 428                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
 429                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
 430                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
 431         };
 432
 433         unsigned i, user_sgpr = 0;
 434         if (AMD_HSA_BITS_GET(code_object->code_properties,
 435                         AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
 436                 if (code_object->workitem_private_segment_byte_size > 0) {
 437                         setup_scratch_rsrc_user_sgprs(sctx, code_object,
 438                                                                 user_sgpr);
 439                 }
 440                 user_sgpr += 4;
 441         }
 442
 443         if (AMD_HSA_BITS_GET(code_object->code_properties,
 444                         AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
 445                 struct dispatch_packet dispatch;
 446                 unsigned dispatch_offset;
 447                 struct r600_resource *dispatch_buf = NULL;
 448                 uint64_t dispatch_va;
 449
 450                 /* Upload dispatch ptr */
 451                 memset(&dispatch, 0, sizeof(dispatch));
 452
 453                 dispatch.workgroup_size_x = info->block[0];
 454                 dispatch.workgroup_size_y = info->block[1];
 455                 dispatch.workgroup_size_z = info->block[2];
 456
 457                 dispatch.grid_size_x = info->grid[0] * info->block[0];
 458                 dispatch.grid_size_y = info->grid[1] * info->block[1];
 459                 dispatch.grid_size_z = info->grid[2] * info->block[2];
 460
 461                 dispatch.private_segment_size = program->private_size;
 462                 dispatch.group_segment_size = program->local_size;
 463
 464                 dispatch.kernarg_address = kernel_args_va;
 465
 466                 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
 467                                 &dispatch, &dispatch_offset,
 468                                 (struct pipe_resource**)&dispatch_buf);
 469
 470                 if (!dispatch_buf) {
 471                         fprintf(stderr, "Error: Failed to allocate dispatch "
 472                                         "packet.");
 473                 }
 474                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
 475                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 476
 477                 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
 478
 479                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 480                                                         (user_sgpr * 4), 2);
 481                 radeon_emit(cs, dispatch_va);
 482                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
 483                                 S_008F04_STRIDE(0));
 484
 485                 r600_resource_reference(&dispatch_buf, NULL);
 486                 user_sgpr += 2;
 487         }
 488
 489         if (AMD_HSA_BITS_GET(code_object->code_properties,
 490                         AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
 491                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 492                                                         (user_sgpr * 4), 2);
 493                 radeon_emit(cs, kernel_args_va);
 494                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 495                                 S_008F04_STRIDE(0));
 496                 user_sgpr += 2;
 497         }
 498
 499         for (i = 0; i < 3 && user_sgpr < 16; i++) {
 500                 if (code_object->code_properties & workgroup_count_masks[i]) {
 501                         radeon_set_sh_reg_seq(cs,
 502                                 R_00B900_COMPUTE_USER_DATA_0 +
 503                                 (user_sgpr * 4), 1);
 504                         radeon_emit(cs, info->grid[i]);
 505                         user_sgpr += 1;
 506                 }
 507         }
 508 }
 509
 510 static void si_upload_compute_input(struct si_context *sctx,
 511                                     const amd_kernel_code_t *code_object,
 512                                     const struct pipe_grid_info *info)
 513 {
 514         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 515         struct si_compute *program = sctx->cs_shader_state.program;
 516         struct r600_resource *input_buffer = NULL;
 517         unsigned kernel_args_size;
 518         unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
 519         uint32_t kernel_args_offset = 0;
 520         uint32_t *kernel_args;
 521         void *kernel_args_ptr;
 522         uint64_t kernel_args_va;
 523         unsigned i;
 524
 525         /* The extra num_work_size_bytes are for work group / work item size information */
 526         kernel_args_size = program->input_size + num_work_size_bytes;
 527
 528         u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
 529                        &kernel_args_offset,
 530                        (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 531
 532         kernel_args = (uint32_t*)kernel_args_ptr;
 533         kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 534
 535         if (!code_object) {
 536                 for (i = 0; i < 3; i++) {
 537                         kernel_args[i] = info->grid[i];
 538                         kernel_args[i + 3] = info->grid[i] * info->block[i];
 539                         kernel_args[i + 6] = info->block[i];
 540                 }
 541         }
 542
 543         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 544                program->input_size);
 545
 546
 547         for (i = 0; i < (kernel_args_size / 4); i++) {
 548                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 549                         kernel_args[i]);
 550         }
 551
 552
 553         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 554                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 555
 556         if (code_object) {
 557                 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
 558         } else {
 559                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 560                 radeon_emit(cs, kernel_args_va);
 561                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 562                                 S_008F04_STRIDE(0));
 563         }
 564
 565         r600_resource_reference(&input_buffer, NULL);
 566 }
 567
 568 static void si_setup_tgsi_grid(struct si_context *sctx,
 569                                 const struct pipe_grid_info *info)
 570 {
 571         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 572         unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
 573                                   4 * SI_SGPR_GRID_SIZE;
 574
 575         if (info->indirect) {
 576                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 577                 uint64_t va = base_va + info->indirect_offset;
 578                 int i;
 579
 580                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 581                                  (struct r600_resource *)info->indirect,
 582                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 583
 584                 for (i = 0; i < 3; ++i) {
 585                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 586                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 587                                         COPY_DATA_DST_SEL(COPY_DATA_REG));
 588                         radeon_emit(cs, (va +  4 * i));
 589                         radeon_emit(cs, (va + 4 * i) >> 32);
 590                         radeon_emit(cs, (grid_size_reg >> 2) + i);
 591                         radeon_emit(cs, 0);
 592                 }
 593         } else {
 594
 595                 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 596                 radeon_emit(cs, info->grid[0]);
 597                 radeon_emit(cs, info->grid[1]);
 598                 radeon_emit(cs, info->grid[2]);
 599         }
 600 }
 601
 602 static void si_emit_dispatch_packets(struct si_context *sctx,
 603                                      const struct pipe_grid_info *info)
 604 {
 605         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 606         bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 607         unsigned waves_per_threadgroup =
 608                 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
 609
 610         radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 611                           S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
 612
 613         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 614         radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 615         radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 616         radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 617
 618         if (info->indirect) {
 619                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 620
 621                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 622                                  (struct r600_resource *)info->indirect,
 623                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 624
 625                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
 626                                 PKT3_SHADER_TYPE_S(1));
 627                 radeon_emit(cs, 1);
 628                 radeon_emit(cs, base_va);
 629                 radeon_emit(cs, base_va >> 32);
 630
 631                 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
 632                                 PKT3_SHADER_TYPE_S(1));
 633                 radeon_emit(cs, info->indirect_offset);
 634                 radeon_emit(cs, 1);
 635         } else {
 636                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
 637                                 PKT3_SHADER_TYPE_S(1));
 638                 radeon_emit(cs, info->grid[0]);
 639                 radeon_emit(cs, info->grid[1]);
 640                 radeon_emit(cs, info->grid[2]);
 641                 radeon_emit(cs, 1);
 642         }
 643 }
 644
 645
 646 static void si_launch_grid(
 647                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 648 {
 649         struct si_context *sctx = (struct si_context*)ctx;
 650         struct si_compute *program = sctx->cs_shader_state.program;
 651         const amd_kernel_code_t *code_object =
 652                 si_compute_get_code_object(program, info->pc);
 653         int i;
 654         /* HW bug workaround when CS threadgroups > 256 threads and async
 655          * compute isn't used, i.e. only one compute job can run at a time.
 656          * If async compute is possible, the threadgroup size must be limited
 657          * to 256 threads on all queues to avoid the bug.
 658          * Only SI and certain CIK chips are affected.
 659          */
 660         bool cs_regalloc_hang =
 661                 (sctx->b.chip_class == SI ||
 662                  sctx->b.family == CHIP_BONAIRE ||
 663                  sctx->b.family == CHIP_KABINI) &&
 664                 info->block[0] * info->block[1] * info->block[2] > 256;
 665
 666         if (cs_regalloc_hang)
 667                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 668                                  SI_CONTEXT_CS_PARTIAL_FLUSH;
 669
 670         si_decompress_compute_textures(sctx);
 671
 672         /* Add buffer sizes for memory checking in need_cs_space. */
 673         r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
 674         /* TODO: add the scratch buffer */
 675
 676         if (info->indirect) {
 677                 r600_context_add_resource_size(ctx, info->indirect);
 678
 679                 /* The hw doesn't read the indirect buffer via TC L2. */
 680                 if (r600_resource(info->indirect)->TC_L2_dirty) {
 681                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 682                         r600_resource(info->indirect)->TC_L2_dirty = false;
 683                 }
 684         }
 685
 686         si_need_cs_space(sctx);
 687
 688         if (!sctx->cs_shader_state.initialized)
 689                 si_initialize_compute(sctx);
 690
 691         if (sctx->b.flags)
 692                 si_emit_cache_flush(sctx);
 693
 694         if (!si_switch_compute_shader(sctx, program, &program->shader,
 695                                         code_object, info->pc))
 696                 return;
 697
 698         si_upload_compute_shader_descriptors(sctx);
 699         si_emit_compute_shader_userdata(sctx);
 700
 701         if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
 702                 sctx->atoms.s.render_cond->emit(&sctx->b,
 703                                                 sctx->atoms.s.render_cond);
 704                 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
 705         }
 706
 707         if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
 708                 si_upload_compute_input(sctx, code_object, info);
 709
 710         /* Global buffers */
 711         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 712                 struct r600_resource *buffer =
 713                                 (struct r600_resource*)program->global_buffers[i];
 714                 if (!buffer) {
 715                         continue;
 716                 }
 717                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 718                                           RADEON_USAGE_READWRITE,
 719                                           RADEON_PRIO_COMPUTE_GLOBAL);
 720         }
 721
 722         if (program->ir_type == PIPE_SHADER_IR_TGSI)
 723                 si_setup_tgsi_grid(sctx, info);
 724
 725         si_ce_pre_draw_synchronization(sctx);
 726
 727         si_emit_dispatch_packets(sctx, info);
 728
 729         si_ce_post_draw_synchronization(sctx);
 730
 731         sctx->compute_is_busy = true;
 732         sctx->b.num_compute_calls++;
 733         if (sctx->cs_shader_state.uses_scratch)
 734                 sctx->b.num_spill_compute_calls++;
 735
 736         if (cs_regalloc_hang)
 737                 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 738 }
 739
 740
 741 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 742         struct si_compute *program = (struct si_compute *)state;
 743         struct si_context *sctx = (struct si_context*)ctx;
 744
 745         if (!state) {
 746                 return;
 747         }
 748
 749         if (program == sctx->cs_shader_state.program)
 750                 sctx->cs_shader_state.program = NULL;
 751
 752         if (program == sctx->cs_shader_state.emitted_program)
 753                 sctx->cs_shader_state.emitted_program = NULL;
 754
 755         si_shader_destroy(&program->shader);
 756         FREE(program);
 757 }
 758
 759 static void si_set_compute_resources(struct pipe_context * ctx_,
 760                 unsigned start, unsigned count,
 761                 struct pipe_surface ** surfaces) { }
 762
 763 void si_init_compute_functions(struct si_context *sctx)
 764 {
 765         sctx->b.b.create_compute_state = si_create_compute_state;
 766         sctx->b.b.delete_compute_state = si_delete_compute_state;
 767         sctx->b.b.bind_compute_state = si_bind_compute_state;
 768 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 769         sctx->b.b.set_compute_resources = si_set_compute_resources;
 770         sctx->b.b.set_global_binding = si_set_global_binding;
 771         sctx->b.b.launch_grid = si_launch_grid;
 772 }