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gallium: add blob field to pipe_llvm_program_header
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "nir/tgsi_to_nir.h"
27 #include "tgsi/tgsi_parse.h"
28 #include "util/u_async_debug.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "ac_rtld.h"
33 #include "amd_kernel_code_t.h"
34 #include "si_build_pm4.h"
35 #include "si_compute.h"
36
37 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 do { \
39 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
40 } while (0);
41
42 struct dispatch_packet {
43 uint16_t header;
44 uint16_t setup;
45 uint16_t workgroup_size_x;
46 uint16_t workgroup_size_y;
47 uint16_t workgroup_size_z;
48 uint16_t reserved0;
49 uint32_t grid_size_x;
50 uint32_t grid_size_y;
51 uint32_t grid_size_z;
52 uint32_t private_segment_size;
53 uint32_t group_segment_size;
54 uint64_t kernel_object;
55 uint64_t kernarg_address;
56 uint64_t reserved2;
57 };
58
59 static const amd_kernel_code_t *si_compute_get_code_object(
60 const struct si_compute *program,
61 uint64_t symbol_offset)
62 {
63 const struct si_shader_selector *sel = &program->sel;
64
65 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
66 return NULL;
67
68 struct ac_rtld_binary rtld;
69 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
70 .info = &sel->screen->info,
71 .shader_type = MESA_SHADER_COMPUTE,
72 .wave_size = sel->screen->compute_wave_size,
73 .num_parts = 1,
74 .elf_ptrs = &program->shader.binary.elf_buffer,
75 .elf_sizes = &program->shader.binary.elf_size }))
76 return NULL;
77
78 const amd_kernel_code_t *result = NULL;
79 const char *text;
80 size_t size;
81 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
82 goto out;
83
84 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
85 goto out;
86
87 result = (const amd_kernel_code_t*)(text + symbol_offset);
88
89 out:
90 ac_rtld_close(&rtld);
91 return result;
92 }
93
94 static void code_object_to_config(const amd_kernel_code_t *code_object,
95 struct ac_shader_config *out_config) {
96
97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
99 out_config->num_sgprs = code_object->wavefront_sgpr_count;
100 out_config->num_vgprs = code_object->workitem_vgpr_count;
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
105 out_config->scratch_bytes_per_wave =
106 align(code_object->workitem_private_segment_byte_size * 64, 1024);
107 }
108
109 /* Asynchronous compute shader compilation. */
110 static void si_create_compute_state_async(void *job, int thread_index)
111 {
112 struct si_compute *program = (struct si_compute *)job;
113 struct si_shader_selector *sel = &program->sel;
114 struct si_shader *shader = &program->shader;
115 struct ac_llvm_compiler *compiler;
116 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
118
119 assert(!debug->debug_message || debug->async);
120 assert(thread_index >= 0);
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
123
124 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
125 tgsi_scan_shader(sel->tokens, &sel->info);
126 } else {
127 assert(program->ir_type == PIPE_SHADER_IR_NIR);
128
129 si_nir_opts(sel->nir);
130 si_nir_scan_shader(sel->nir, &sel->info);
131 si_lower_nir(sel);
132 }
133
134 /* Store the declared LDS size into tgsi_shader_info for the shader
135 * cache to include it.
136 */
137 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
138
139 si_get_active_slot_masks(&sel->info,
140 &sel->active_const_and_shader_buffers,
141 &sel->active_samplers_and_images);
142
143 program->shader.is_monolithic = true;
144 program->reads_variable_block_size =
145 sel->info.uses_block_size &&
146 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
147 program->num_cs_user_data_dwords =
148 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
149
150 void *ir_binary = si_get_ir_binary(sel, false, false);
151
152 /* Try to load the shader from the shader cache. */
153 mtx_lock(&sscreen->shader_cache_mutex);
154
155 if (ir_binary &&
156 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
157 mtx_unlock(&sscreen->shader_cache_mutex);
158
159 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
160 si_shader_dump(sscreen, shader, debug, stderr, true);
161
162 if (!si_shader_binary_upload(sscreen, shader, 0))
163 program->shader.compilation_failed = true;
164 } else {
165 mtx_unlock(&sscreen->shader_cache_mutex);
166
167 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
168 program->shader.compilation_failed = true;
169
170 if (program->ir_type == PIPE_SHADER_IR_TGSI)
171 FREE(sel->tokens);
172 return;
173 }
174
175 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
176 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
177 (sel->info.uses_grid_size ? 3 : 0) +
178 (program->reads_variable_block_size ? 3 : 0) +
179 program->num_cs_user_data_dwords;
180
181 shader->config.rsrc1 =
182 S_00B848_VGPRS((shader->config.num_vgprs - 1) /
183 (sscreen->compute_wave_size == 32 ? 8 : 4)) |
184 S_00B848_DX10_CLAMP(1) |
185 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
186 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
187 S_00B848_FLOAT_MODE(shader->config.float_mode);
188
189 if (sscreen->info.chip_class < GFX10) {
190 shader->config.rsrc1 |=
191 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
192 }
193
194 shader->config.rsrc2 =
195 S_00B84C_USER_SGPR(user_sgprs) |
196 S_00B84C_SCRATCH_EN(scratch_enabled) |
197 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
198 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
199 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
200 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
201 sel->info.uses_thread_id[1] ? 1 : 0) |
202 S_00B84C_LDS_SIZE(shader->config.lds_size);
203
204 if (ir_binary) {
205 mtx_lock(&sscreen->shader_cache_mutex);
206 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
207 FREE(ir_binary);
208 mtx_unlock(&sscreen->shader_cache_mutex);
209 }
210 }
211
212 if (program->ir_type == PIPE_SHADER_IR_TGSI)
213 FREE(sel->tokens);
214 }
215
216 static void *si_create_compute_state(
217 struct pipe_context *ctx,
218 const struct pipe_compute_state *cso)
219 {
220 struct si_context *sctx = (struct si_context *)ctx;
221 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
222 struct si_compute *program = CALLOC_STRUCT(si_compute);
223 struct si_shader_selector *sel = &program->sel;
224
225 pipe_reference_init(&sel->reference, 1);
226 sel->type = PIPE_SHADER_COMPUTE;
227 sel->screen = sscreen;
228 program->shader.selector = &program->sel;
229 program->ir_type = cso->ir_type;
230 program->local_size = cso->req_local_mem;
231 program->private_size = cso->req_private_mem;
232 program->input_size = cso->req_input_mem;
233
234 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
235 if (sscreen->options.enable_nir &&
236 cso->ir_type == PIPE_SHADER_IR_TGSI) {
237 program->ir_type = PIPE_SHADER_IR_NIR;
238 sel->nir = tgsi_to_nir(cso->prog, ctx->screen);
239 } else if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
240 sel->tokens = tgsi_dup_tokens(cso->prog);
241 if (!sel->tokens) {
242 FREE(program);
243 return NULL;
244 }
245 } else {
246 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
247 sel->nir = (struct nir_shader *) cso->prog;
248 }
249
250 sel->compiler_ctx_state.debug = sctx->debug;
251 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
252 p_atomic_inc(&sscreen->num_shaders_created);
253
254 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
255 &sel->ready,
256 &sel->compiler_ctx_state,
257 program, si_create_compute_state_async);
258 } else {
259 const struct pipe_llvm_program_header *header;
260 header = cso->prog;
261
262 program->shader.binary.elf_size = header->num_bytes;
263 program->shader.binary.elf_buffer = malloc(header->num_bytes);
264 if (!program->shader.binary.elf_buffer) {
265 FREE(program);
266 return NULL;
267 }
268 memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
269
270 const amd_kernel_code_t *code_object =
271 si_compute_get_code_object(program, 0);
272 code_object_to_config(code_object, &program->shader.config);
273
274 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
275 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
276 fprintf(stderr, "LLVM failed to upload shader\n");
277 free((void *)program->shader.binary.elf_buffer);
278 FREE(program);
279 return NULL;
280 }
281 }
282
283 return program;
284 }
285
286 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
287 {
288 struct si_context *sctx = (struct si_context*)ctx;
289 struct si_compute *program = (struct si_compute*)state;
290 struct si_shader_selector *sel = &program->sel;
291
292 sctx->cs_shader_state.program = program;
293 if (!program)
294 return;
295
296 /* Wait because we need active slot usage masks. */
297 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
298 util_queue_fence_wait(&sel->ready);
299
300 si_set_active_descriptors(sctx,
301 SI_DESCS_FIRST_COMPUTE +
302 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
303 sel->active_const_and_shader_buffers);
304 si_set_active_descriptors(sctx,
305 SI_DESCS_FIRST_COMPUTE +
306 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
307 sel->active_samplers_and_images);
308 }
309
310 static void si_set_global_binding(
311 struct pipe_context *ctx, unsigned first, unsigned n,
312 struct pipe_resource **resources,
313 uint32_t **handles)
314 {
315 unsigned i;
316 struct si_context *sctx = (struct si_context*)ctx;
317 struct si_compute *program = sctx->cs_shader_state.program;
318
319 if (first + n > program->max_global_buffers) {
320 unsigned old_max = program->max_global_buffers;
321 program->max_global_buffers = first + n;
322 program->global_buffers =
323 realloc(program->global_buffers,
324 program->max_global_buffers *
325 sizeof(program->global_buffers[0]));
326 if (!program->global_buffers) {
327 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
328 return;
329 }
330
331 memset(&program->global_buffers[old_max], 0,
332 (program->max_global_buffers - old_max) *
333 sizeof(program->global_buffers[0]));
334 }
335
336 if (!resources) {
337 for (i = 0; i < n; i++) {
338 pipe_resource_reference(&program->global_buffers[first + i], NULL);
339 }
340 return;
341 }
342
343 for (i = 0; i < n; i++) {
344 uint64_t va;
345 uint32_t offset;
346 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
347 va = si_resource(resources[i])->gpu_address;
348 offset = util_le32_to_cpu(*handles[i]);
349 va += offset;
350 va = util_cpu_to_le64(va);
351 memcpy(handles[i], &va, sizeof(va));
352 }
353 }
354
355 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
356 {
357 uint64_t bc_va;
358
359 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
360 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
361 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
362 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
363 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
364
365 if (sctx->chip_class >= GFX7) {
366 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
367 radeon_set_sh_reg_seq(cs,
368 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
369 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
370 S_00B858_SH1_CU_EN(0xffff));
371 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
372 S_00B858_SH1_CU_EN(0xffff));
373 }
374
375 if (sctx->chip_class >= GFX10)
376 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
377
378 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
379 * and is now per pipe, so it should be handled in the
380 * kernel if we want to use something other than the default value,
381 * which is now 0x22f.
382 */
383 if (sctx->chip_class <= GFX6) {
384 /* XXX: This should be:
385 * (number of compute units) * 4 * (waves per simd) - 1 */
386
387 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
388 0x190 /* Default value */);
389 }
390
391 /* Set the pointer to border colors. */
392 bc_va = sctx->border_color_buffer->gpu_address;
393
394 if (sctx->chip_class >= GFX7) {
395 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
396 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
397 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
398 } else {
399 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
400 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
401 bc_va >> 8);
402 }
403 }
404 }
405
406 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
407 struct si_shader *shader,
408 struct ac_shader_config *config)
409 {
410 uint64_t scratch_bo_size, scratch_needed;
411 scratch_bo_size = 0;
412 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
413 if (sctx->compute_scratch_buffer)
414 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
415
416 if (scratch_bo_size < scratch_needed) {
417 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
418
419 sctx->compute_scratch_buffer =
420 si_aligned_buffer_create(&sctx->screen->b,
421 SI_RESOURCE_FLAG_UNMAPPABLE,
422 PIPE_USAGE_DEFAULT,
423 scratch_needed,
424 sctx->screen->info.pte_fragment_size);
425
426 if (!sctx->compute_scratch_buffer)
427 return false;
428 }
429
430 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
431 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
432
433 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
434 return false;
435
436 si_resource_reference(&shader->scratch_bo,
437 sctx->compute_scratch_buffer);
438 }
439
440 return true;
441 }
442
443 static bool si_switch_compute_shader(struct si_context *sctx,
444 struct si_compute *program,
445 struct si_shader *shader,
446 const amd_kernel_code_t *code_object,
447 unsigned offset)
448 {
449 struct radeon_cmdbuf *cs = sctx->gfx_cs;
450 struct ac_shader_config inline_config = {0};
451 struct ac_shader_config *config;
452 uint64_t shader_va;
453
454 if (sctx->cs_shader_state.emitted_program == program &&
455 sctx->cs_shader_state.offset == offset)
456 return true;
457
458 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
459 config = &shader->config;
460 } else {
461 unsigned lds_blocks;
462
463 config = &inline_config;
464 code_object_to_config(code_object, config);
465
466 lds_blocks = config->lds_size;
467 /* XXX: We are over allocating LDS. For GFX6, the shader reports
468 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
469 * allocated in the shader and 4 bytes allocated by the state
470 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
471 */
472 if (sctx->chip_class <= GFX6) {
473 lds_blocks += align(program->local_size, 256) >> 8;
474 } else {
475 lds_blocks += align(program->local_size, 512) >> 9;
476 }
477
478 /* TODO: use si_multiwave_lds_size_workaround */
479 assert(lds_blocks <= 0xFF);
480
481 config->rsrc2 &= C_00B84C_LDS_SIZE;
482 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
483 }
484
485 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
486 return false;
487
488 if (shader->scratch_bo) {
489 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
490 "Total Scratch: %u bytes\n", sctx->scratch_waves,
491 config->scratch_bytes_per_wave,
492 config->scratch_bytes_per_wave *
493 sctx->scratch_waves);
494
495 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
496 shader->scratch_bo, RADEON_USAGE_READWRITE,
497 RADEON_PRIO_SCRATCH_BUFFER);
498 }
499
500 /* Prefetch the compute shader to TC L2.
501 *
502 * We should also prefetch graphics shaders if a compute dispatch was
503 * the last command, and the compute shader if a draw call was the last
504 * command. However, that would add more complexity and we're likely
505 * to get a shader state change in that case anyway.
506 */
507 if (sctx->chip_class >= GFX7) {
508 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
509 0, program->shader.bo->b.b.width0);
510 }
511
512 shader_va = shader->bo->gpu_address + offset;
513 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
514 /* Shader code is placed after the amd_kernel_code_t
515 * struct. */
516 shader_va += sizeof(amd_kernel_code_t);
517 }
518
519 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
520 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
521
522 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
523 radeon_emit(cs, shader_va >> 8);
524 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
525
526 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
527 radeon_emit(cs, config->rsrc1);
528 radeon_emit(cs, config->rsrc2);
529
530 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
531 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
532
533 sctx->max_seen_compute_scratch_bytes_per_wave =
534 MAX2(sctx->max_seen_compute_scratch_bytes_per_wave,
535 config->scratch_bytes_per_wave);
536
537 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
538 S_00B860_WAVES(sctx->scratch_waves)
539 | S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
540
541 sctx->cs_shader_state.emitted_program = program;
542 sctx->cs_shader_state.offset = offset;
543 sctx->cs_shader_state.uses_scratch =
544 config->scratch_bytes_per_wave != 0;
545
546 return true;
547 }
548
549 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
550 const amd_kernel_code_t *code_object,
551 unsigned user_sgpr)
552 {
553 struct radeon_cmdbuf *cs = sctx->gfx_cs;
554 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
555
556 unsigned max_private_element_size = AMD_HSA_BITS_GET(
557 code_object->code_properties,
558 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
559
560 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
561 uint32_t scratch_dword1 =
562 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
563 S_008F04_SWIZZLE_ENABLE(1);
564
565 /* Disable address clamping */
566 uint32_t scratch_dword2 = 0xffffffff;
567 uint32_t scratch_dword3 =
568 S_008F0C_INDEX_STRIDE(3) |
569 S_008F0C_ADD_TID_ENABLE(1);
570
571 if (sctx->chip_class >= GFX9) {
572 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
573 } else {
574 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
575
576 if (sctx->chip_class < GFX8) {
577 /* BUF_DATA_FORMAT is ignored, but it cannot be
578 * BUF_DATA_FORMAT_INVALID. */
579 scratch_dword3 |=
580 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
581 }
582 }
583
584 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
585 (user_sgpr * 4), 4);
586 radeon_emit(cs, scratch_dword0);
587 radeon_emit(cs, scratch_dword1);
588 radeon_emit(cs, scratch_dword2);
589 radeon_emit(cs, scratch_dword3);
590 }
591
592 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
593 const amd_kernel_code_t *code_object,
594 const struct pipe_grid_info *info,
595 uint64_t kernel_args_va)
596 {
597 struct si_compute *program = sctx->cs_shader_state.program;
598 struct radeon_cmdbuf *cs = sctx->gfx_cs;
599
600 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
601 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
602 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
603 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
604 };
605
606 unsigned i, user_sgpr = 0;
607 if (AMD_HSA_BITS_GET(code_object->code_properties,
608 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
609 if (code_object->workitem_private_segment_byte_size > 0) {
610 setup_scratch_rsrc_user_sgprs(sctx, code_object,
611 user_sgpr);
612 }
613 user_sgpr += 4;
614 }
615
616 if (AMD_HSA_BITS_GET(code_object->code_properties,
617 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
618 struct dispatch_packet dispatch;
619 unsigned dispatch_offset;
620 struct si_resource *dispatch_buf = NULL;
621 uint64_t dispatch_va;
622
623 /* Upload dispatch ptr */
624 memset(&dispatch, 0, sizeof(dispatch));
625
626 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
627 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
628 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
629
630 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
631 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
632 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
633
634 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
635 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
636
637 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
638
639 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
640 256, &dispatch, &dispatch_offset,
641 (struct pipe_resource**)&dispatch_buf);
642
643 if (!dispatch_buf) {
644 fprintf(stderr, "Error: Failed to allocate dispatch "
645 "packet.");
646 }
647 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
648 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
649
650 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
651
652 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
653 (user_sgpr * 4), 2);
654 radeon_emit(cs, dispatch_va);
655 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
656 S_008F04_STRIDE(0));
657
658 si_resource_reference(&dispatch_buf, NULL);
659 user_sgpr += 2;
660 }
661
662 if (AMD_HSA_BITS_GET(code_object->code_properties,
663 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
664 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
665 (user_sgpr * 4), 2);
666 radeon_emit(cs, kernel_args_va);
667 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
668 S_008F04_STRIDE(0));
669 user_sgpr += 2;
670 }
671
672 for (i = 0; i < 3 && user_sgpr < 16; i++) {
673 if (code_object->code_properties & workgroup_count_masks[i]) {
674 radeon_set_sh_reg_seq(cs,
675 R_00B900_COMPUTE_USER_DATA_0 +
676 (user_sgpr * 4), 1);
677 radeon_emit(cs, info->grid[i]);
678 user_sgpr += 1;
679 }
680 }
681 }
682
683 static bool si_upload_compute_input(struct si_context *sctx,
684 const amd_kernel_code_t *code_object,
685 const struct pipe_grid_info *info)
686 {
687 struct si_compute *program = sctx->cs_shader_state.program;
688 struct si_resource *input_buffer = NULL;
689 uint32_t kernel_args_offset = 0;
690 uint32_t *kernel_args;
691 void *kernel_args_ptr;
692 uint64_t kernel_args_va;
693
694 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
695 sctx->screen->info.tcc_cache_line_size,
696 &kernel_args_offset,
697 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
698
699 if (unlikely(!kernel_args_ptr))
700 return false;
701
702 kernel_args = (uint32_t*)kernel_args_ptr;
703 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
704
705 memcpy(kernel_args, info->input, program->input_size);
706
707 for (unsigned i = 0; i < program->input_size / 4; i++) {
708 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
709 kernel_args[i]);
710 }
711
712 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
713 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
714
715 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
716 si_resource_reference(&input_buffer, NULL);
717 return true;
718 }
719
720 static void si_setup_tgsi_user_data(struct si_context *sctx,
721 const struct pipe_grid_info *info)
722 {
723 struct si_compute *program = sctx->cs_shader_state.program;
724 struct si_shader_selector *sel = &program->sel;
725 struct radeon_cmdbuf *cs = sctx->gfx_cs;
726 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
727 4 * SI_NUM_RESOURCE_SGPRS;
728 unsigned block_size_reg = grid_size_reg +
729 /* 12 bytes = 3 dwords. */
730 12 * sel->info.uses_grid_size;
731 unsigned cs_user_data_reg = block_size_reg +
732 12 * program->reads_variable_block_size;
733
734 if (info->indirect) {
735 if (sel->info.uses_grid_size) {
736 for (unsigned i = 0; i < 3; ++i) {
737 si_cp_copy_data(sctx, sctx->gfx_cs,
738 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
739 COPY_DATA_SRC_MEM, si_resource(info->indirect),
740 info->indirect_offset + 4 * i);
741 }
742 }
743 } else {
744 if (sel->info.uses_grid_size) {
745 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
746 radeon_emit(cs, info->grid[0]);
747 radeon_emit(cs, info->grid[1]);
748 radeon_emit(cs, info->grid[2]);
749 }
750 if (program->reads_variable_block_size) {
751 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
752 radeon_emit(cs, info->block[0]);
753 radeon_emit(cs, info->block[1]);
754 radeon_emit(cs, info->block[2]);
755 }
756 }
757
758 if (program->num_cs_user_data_dwords) {
759 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
760 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
761 }
762 }
763
764 static void si_emit_dispatch_packets(struct si_context *sctx,
765 const struct pipe_grid_info *info)
766 {
767 struct si_screen *sscreen = sctx->screen;
768 struct radeon_cmdbuf *cs = sctx->gfx_cs;
769 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
770 unsigned threads_per_threadgroup =
771 info->block[0] * info->block[1] * info->block[2];
772 unsigned waves_per_threadgroup =
773 DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
774 unsigned threadgroups_per_cu = 1;
775
776 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
777 threadgroups_per_cu = 2;
778
779 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
780 ac_get_compute_resource_limits(&sscreen->info,
781 waves_per_threadgroup,
782 sctx->cs_max_waves_per_sh,
783 threadgroups_per_cu));
784
785 unsigned dispatch_initiator =
786 S_00B800_COMPUTE_SHADER_EN(1) |
787 S_00B800_FORCE_START_AT_000(1) |
788 /* If the KMD allows it (there is a KMD hw register for it),
789 * allow launching waves out-of-order. (same as Vulkan) */
790 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
791 S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
792
793 const uint *last_block = info->last_block;
794 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
795
796 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
797
798 if (partial_block_en) {
799 unsigned partial[3];
800
801 /* If no partial_block, these should be an entire block size, not 0. */
802 partial[0] = last_block[0] ? last_block[0] : info->block[0];
803 partial[1] = last_block[1] ? last_block[1] : info->block[1];
804 partial[2] = last_block[2] ? last_block[2] : info->block[2];
805
806 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
807 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
808 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
809 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
810 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
811 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
812
813 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
814 } else {
815 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
816 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
817 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
818 }
819
820 if (info->indirect) {
821 uint64_t base_va = si_resource(info->indirect)->gpu_address;
822
823 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
824 si_resource(info->indirect),
825 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
826
827 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
828 PKT3_SHADER_TYPE_S(1));
829 radeon_emit(cs, 1);
830 radeon_emit(cs, base_va);
831 radeon_emit(cs, base_va >> 32);
832
833 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
834 PKT3_SHADER_TYPE_S(1));
835 radeon_emit(cs, info->indirect_offset);
836 radeon_emit(cs, dispatch_initiator);
837 } else {
838 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
839 PKT3_SHADER_TYPE_S(1));
840 radeon_emit(cs, info->grid[0]);
841 radeon_emit(cs, info->grid[1]);
842 radeon_emit(cs, info->grid[2]);
843 radeon_emit(cs, dispatch_initiator);
844 }
845 }
846
847
848 static void si_launch_grid(
849 struct pipe_context *ctx, const struct pipe_grid_info *info)
850 {
851 struct si_context *sctx = (struct si_context*)ctx;
852 struct si_compute *program = sctx->cs_shader_state.program;
853 const amd_kernel_code_t *code_object =
854 si_compute_get_code_object(program, info->pc);
855 int i;
856 /* HW bug workaround when CS threadgroups > 256 threads and async
857 * compute isn't used, i.e. only one compute job can run at a time.
858 * If async compute is possible, the threadgroup size must be limited
859 * to 256 threads on all queues to avoid the bug.
860 * Only GFX6 and certain GFX7 chips are affected.
861 */
862 bool cs_regalloc_hang =
863 (sctx->chip_class == GFX6 ||
864 sctx->family == CHIP_BONAIRE ||
865 sctx->family == CHIP_KABINI) &&
866 info->block[0] * info->block[1] * info->block[2] > 256;
867
868 if (cs_regalloc_hang)
869 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
870 SI_CONTEXT_CS_PARTIAL_FLUSH;
871
872 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
873 program->shader.compilation_failed)
874 return;
875
876 if (sctx->has_graphics) {
877 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
878 si_update_fb_dirtiness_after_rendering(sctx);
879 sctx->last_num_draw_calls = sctx->num_draw_calls;
880 }
881
882 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
883 }
884
885 /* Add buffer sizes for memory checking in need_cs_space. */
886 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
887 /* TODO: add the scratch buffer */
888
889 if (info->indirect) {
890 si_context_add_resource_size(sctx, info->indirect);
891
892 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
893 if (sctx->chip_class <= GFX8 &&
894 si_resource(info->indirect)->TC_L2_dirty) {
895 sctx->flags |= SI_CONTEXT_WB_L2;
896 si_resource(info->indirect)->TC_L2_dirty = false;
897 }
898 }
899
900 si_need_gfx_cs_space(sctx);
901
902 if (sctx->bo_list_add_all_compute_resources)
903 si_compute_resources_add_all_to_bo_list(sctx);
904
905 if (!sctx->cs_shader_state.initialized) {
906 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
907
908 sctx->cs_shader_state.emitted_program = NULL;
909 sctx->cs_shader_state.initialized = true;
910 }
911
912 if (sctx->flags)
913 sctx->emit_cache_flush(sctx);
914
915 if (!si_switch_compute_shader(sctx, program, &program->shader,
916 code_object, info->pc))
917 return;
918
919 si_upload_compute_shader_descriptors(sctx);
920 si_emit_compute_shader_pointers(sctx);
921
922 if (sctx->has_graphics &&
923 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
924 sctx->atoms.s.render_cond.emit(sctx);
925 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
926 }
927
928 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
929 unlikely(!si_upload_compute_input(sctx, code_object, info)))
930 return;
931
932 /* Global buffers */
933 for (i = 0; i < program->max_global_buffers; i++) {
934 struct si_resource *buffer =
935 si_resource(program->global_buffers[i]);
936 if (!buffer) {
937 continue;
938 }
939 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
940 RADEON_USAGE_READWRITE,
941 RADEON_PRIO_COMPUTE_GLOBAL);
942 }
943
944 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
945 si_setup_tgsi_user_data(sctx, info);
946
947 si_emit_dispatch_packets(sctx, info);
948
949 if (unlikely(sctx->current_saved_cs)) {
950 si_trace_emit(sctx);
951 si_log_compute_state(sctx, sctx->log);
952 }
953
954 sctx->compute_is_busy = true;
955 sctx->num_compute_calls++;
956 if (sctx->cs_shader_state.uses_scratch)
957 sctx->num_spill_compute_calls++;
958
959 if (cs_regalloc_hang)
960 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
961 }
962
963 void si_destroy_compute(struct si_compute *program)
964 {
965 struct si_shader_selector *sel = &program->sel;
966
967 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
968 util_queue_drop_job(&sel->screen->shader_compiler_queue,
969 &sel->ready);
970 util_queue_fence_destroy(&sel->ready);
971 }
972
973 for (unsigned i = 0; i < program->max_global_buffers; i++)
974 pipe_resource_reference(&program->global_buffers[i], NULL);
975 FREE(program->global_buffers);
976
977 si_shader_destroy(&program->shader);
978 ralloc_free(program->sel.nir);
979 FREE(program);
980 }
981
982 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
983 struct si_compute *program = (struct si_compute *)state;
984 struct si_context *sctx = (struct si_context*)ctx;
985
986 if (!state)
987 return;
988
989 if (program == sctx->cs_shader_state.program)
990 sctx->cs_shader_state.program = NULL;
991
992 if (program == sctx->cs_shader_state.emitted_program)
993 sctx->cs_shader_state.emitted_program = NULL;
994
995 si_compute_reference(&program, NULL);
996 }
997
998 static void si_set_compute_resources(struct pipe_context * ctx_,
999 unsigned start, unsigned count,
1000 struct pipe_surface ** surfaces) { }
1001
1002 void si_init_compute_functions(struct si_context *sctx)
1003 {
1004 sctx->b.create_compute_state = si_create_compute_state;
1005 sctx->b.delete_compute_state = si_delete_compute_state;
1006 sctx->b.bind_compute_state = si_bind_compute_state;
1007 sctx->b.set_compute_resources = si_set_compute_resources;
1008 sctx->b.set_global_binding = si_set_global_binding;
1009 sctx->b.launch_grid = si_launch_grid;
1010 }