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radeonsi: simplify checking for monolithic compilation
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "radeon/radeon_elf_util.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 #define MAX_GLOBAL_BUFFERS 20
36
37 struct si_compute {
38 unsigned ir_type;
39 unsigned local_size;
40 unsigned private_size;
41 unsigned input_size;
42 struct si_shader shader;
43
44 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
45 unsigned use_code_object_v2 : 1;
46 unsigned variable_group_size : 1;
47 };
48
49 struct dispatch_packet {
50 uint16_t header;
51 uint16_t setup;
52 uint16_t workgroup_size_x;
53 uint16_t workgroup_size_y;
54 uint16_t workgroup_size_z;
55 uint16_t reserved0;
56 uint32_t grid_size_x;
57 uint32_t grid_size_y;
58 uint32_t grid_size_z;
59 uint32_t private_segment_size;
60 uint32_t group_segment_size;
61 uint64_t kernel_object;
62 uint64_t kernarg_address;
63 uint64_t reserved2;
64 };
65
66 static const amd_kernel_code_t *si_compute_get_code_object(
67 const struct si_compute *program,
68 uint64_t symbol_offset)
69 {
70 if (!program->use_code_object_v2) {
71 return NULL;
72 }
73 return (const amd_kernel_code_t*)
74 (program->shader.binary.code + symbol_offset);
75 }
76
77 static void code_object_to_config(const amd_kernel_code_t *code_object,
78 struct si_shader_config *out_config) {
79
80 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
81 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
82 out_config->num_sgprs = code_object->wavefront_sgpr_count;
83 out_config->num_vgprs = code_object->workitem_vgpr_count;
84 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
85 out_config->rsrc1 = rsrc1;
86 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
87 out_config->rsrc2 = rsrc2;
88 out_config->scratch_bytes_per_wave =
89 align(code_object->workitem_private_segment_byte_size * 64, 1024);
90 }
91
92 static void *si_create_compute_state(
93 struct pipe_context *ctx,
94 const struct pipe_compute_state *cso)
95 {
96 struct si_context *sctx = (struct si_context *)ctx;
97 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
98 struct si_compute *program = CALLOC_STRUCT(si_compute);
99 struct si_shader *shader = &program->shader;
100
101
102 program->ir_type = cso->ir_type;
103 program->local_size = cso->req_local_mem;
104 program->private_size = cso->req_private_mem;
105 program->input_size = cso->req_input_mem;
106 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
107 cso->ir_type == PIPE_SHADER_IR_NATIVE;
108
109
110 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
111 struct si_shader_selector sel;
112 bool scratch_enabled;
113
114 memset(&sel, 0, sizeof(sel));
115
116 sel.tokens = tgsi_dup_tokens(cso->prog);
117 if (!sel.tokens) {
118 FREE(program);
119 return NULL;
120 }
121
122 tgsi_scan_shader(cso->prog, &sel.info);
123 sel.type = PIPE_SHADER_COMPUTE;
124 sel.local_size = cso->req_local_mem;
125
126 p_atomic_inc(&sscreen->b.num_shaders_created);
127
128 program->shader.selector = &sel;
129 program->shader.is_monolithic = true;
130
131 if (si_shader_create(sscreen, sctx->tm, &program->shader,
132 &sctx->b.debug)) {
133 FREE(sel.tokens);
134 FREE(program);
135 return NULL;
136 }
137
138 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
139
140 shader->config.rsrc1 =
141 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
142 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
143 S_00B848_DX10_CLAMP(1) |
144 S_00B848_FLOAT_MODE(shader->config.float_mode);
145
146 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
147 S_00B84C_SCRATCH_EN(scratch_enabled) |
148 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
149 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
150 S_00B84C_LDS_SIZE(shader->config.lds_size);
151
152 program->variable_group_size =
153 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
154
155 FREE(sel.tokens);
156 program->shader.selector = NULL;
157 } else {
158 const struct pipe_llvm_program_header *header;
159 const char *code;
160 header = cso->prog;
161 code = cso->prog + sizeof(struct pipe_llvm_program_header);
162
163 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
164 if (program->use_code_object_v2) {
165 const amd_kernel_code_t *code_object =
166 si_compute_get_code_object(program, 0);
167 code_object_to_config(code_object, &program->shader.config);
168 } else {
169 si_shader_binary_read_config(&program->shader.binary,
170 &program->shader.config, 0);
171 }
172 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
173 PIPE_SHADER_COMPUTE, stderr);
174 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
175 fprintf(stderr, "LLVM failed to upload shader\n");
176 FREE(program);
177 return NULL;
178 }
179 }
180
181 return program;
182 }
183
184 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
185 {
186 struct si_context *sctx = (struct si_context*)ctx;
187 sctx->cs_shader_state.program = (struct si_compute*)state;
188 }
189
190 static void si_set_global_binding(
191 struct pipe_context *ctx, unsigned first, unsigned n,
192 struct pipe_resource **resources,
193 uint32_t **handles)
194 {
195 unsigned i;
196 struct si_context *sctx = (struct si_context*)ctx;
197 struct si_compute *program = sctx->cs_shader_state.program;
198
199 if (!resources) {
200 for (i = first; i < first + n; i++) {
201 pipe_resource_reference(&program->global_buffers[i], NULL);
202 }
203 return;
204 }
205
206 for (i = first; i < first + n; i++) {
207 uint64_t va;
208 uint32_t offset;
209 pipe_resource_reference(&program->global_buffers[i], resources[i]);
210 va = r600_resource(resources[i])->gpu_address;
211 offset = util_le32_to_cpu(*handles[i]);
212 va += offset;
213 va = util_cpu_to_le64(va);
214 memcpy(handles[i], &va, sizeof(va));
215 }
216 }
217
218 static void si_initialize_compute(struct si_context *sctx)
219 {
220 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
221 uint64_t bc_va;
222
223 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
224 radeon_emit(cs, 0);
225 radeon_emit(cs, 0);
226 radeon_emit(cs, 0);
227
228 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
229 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
230 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
231 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
232
233 if (sctx->b.chip_class >= CIK) {
234 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
235 radeon_set_sh_reg_seq(cs,
236 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
237 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
238 S_00B864_SH1_CU_EN(0xffff));
239 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
240 S_00B868_SH1_CU_EN(0xffff));
241 }
242
243 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
244 * and is now per pipe, so it should be handled in the
245 * kernel if we want to use something other than the default value,
246 * which is now 0x22f.
247 */
248 if (sctx->b.chip_class <= SI) {
249 /* XXX: This should be:
250 * (number of compute units) * 4 * (waves per simd) - 1 */
251
252 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
253 0x190 /* Default value */);
254 }
255
256 /* Set the pointer to border colors. */
257 bc_va = sctx->border_color_buffer->gpu_address;
258
259 if (sctx->b.chip_class >= CIK) {
260 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
261 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
262 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
263 } else {
264 if (sctx->screen->b.info.drm_major == 3 ||
265 (sctx->screen->b.info.drm_major == 2 &&
266 sctx->screen->b.info.drm_minor >= 48)) {
267 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
268 bc_va >> 8);
269 }
270 }
271
272 sctx->cs_shader_state.emitted_program = NULL;
273 sctx->cs_shader_state.initialized = true;
274 }
275
276 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
277 struct si_shader *shader,
278 struct si_shader_config *config)
279 {
280 uint64_t scratch_bo_size, scratch_needed;
281 scratch_bo_size = 0;
282 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
283 if (sctx->compute_scratch_buffer)
284 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
285
286 if (scratch_bo_size < scratch_needed) {
287 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
288
289 sctx->compute_scratch_buffer = (struct r600_resource*)
290 pipe_buffer_create(&sctx->screen->b.b, 0,
291 PIPE_USAGE_DEFAULT, scratch_needed);
292
293 if (!sctx->compute_scratch_buffer)
294 return false;
295 }
296
297 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
298 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
299
300 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
301
302 if (si_shader_binary_upload(sctx->screen, shader))
303 return false;
304
305 r600_resource_reference(&shader->scratch_bo,
306 sctx->compute_scratch_buffer);
307 }
308
309 return true;
310 }
311
312 static bool si_switch_compute_shader(struct si_context *sctx,
313 struct si_compute *program,
314 struct si_shader *shader,
315 const amd_kernel_code_t *code_object,
316 unsigned offset)
317 {
318 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
319 struct si_shader_config inline_config = {0};
320 struct si_shader_config *config;
321 uint64_t shader_va;
322
323 if (sctx->cs_shader_state.emitted_program == program &&
324 sctx->cs_shader_state.offset == offset)
325 return true;
326
327 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
328 config = &shader->config;
329 } else {
330 unsigned lds_blocks;
331
332 config = &inline_config;
333 if (code_object) {
334 code_object_to_config(code_object, config);
335 } else {
336 si_shader_binary_read_config(&shader->binary, config, offset);
337 }
338
339 lds_blocks = config->lds_size;
340 /* XXX: We are over allocating LDS. For SI, the shader reports
341 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
342 * allocated in the shader and 4 bytes allocated by the state
343 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
344 */
345 if (sctx->b.chip_class <= SI) {
346 lds_blocks += align(program->local_size, 256) >> 8;
347 } else {
348 lds_blocks += align(program->local_size, 512) >> 9;
349 }
350
351 assert(lds_blocks <= 0xFF);
352
353 config->rsrc2 &= C_00B84C_LDS_SIZE;
354 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
355 }
356
357 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
358 return false;
359
360 if (shader->scratch_bo) {
361 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
362 "Total Scratch: %u bytes\n", sctx->scratch_waves,
363 config->scratch_bytes_per_wave,
364 config->scratch_bytes_per_wave *
365 sctx->scratch_waves);
366
367 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
368 shader->scratch_bo, RADEON_USAGE_READWRITE,
369 RADEON_PRIO_SCRATCH_BUFFER);
370 }
371
372 shader_va = shader->bo->gpu_address + offset;
373 if (program->use_code_object_v2) {
374 /* Shader code is placed after the amd_kernel_code_t
375 * struct. */
376 shader_va += sizeof(amd_kernel_code_t);
377 }
378
379 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
380 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
381
382 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
383 radeon_emit(cs, shader_va >> 8);
384 radeon_emit(cs, shader_va >> 40);
385
386 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
387 radeon_emit(cs, config->rsrc1);
388 radeon_emit(cs, config->rsrc2);
389
390 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
391 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
392
393 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
394 S_00B860_WAVES(sctx->scratch_waves)
395 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
396
397 sctx->cs_shader_state.emitted_program = program;
398 sctx->cs_shader_state.offset = offset;
399 sctx->cs_shader_state.uses_scratch =
400 config->scratch_bytes_per_wave != 0;
401
402 return true;
403 }
404
405 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
406 const amd_kernel_code_t *code_object,
407 unsigned user_sgpr)
408 {
409 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
410 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
411
412 unsigned max_private_element_size = AMD_HSA_BITS_GET(
413 code_object->code_properties,
414 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
415
416 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
417 uint32_t scratch_dword1 =
418 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
419 S_008F04_SWIZZLE_ENABLE(1);
420
421 /* Disable address clamping */
422 uint32_t scratch_dword2 = 0xffffffff;
423 uint32_t scratch_dword3 =
424 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
425 S_008F0C_INDEX_STRIDE(3) |
426 S_008F0C_ADD_TID_ENABLE(1);
427
428
429 if (sctx->screen->b.chip_class < VI) {
430 /* BUF_DATA_FORMAT is ignored, but it cannot be
431 BUF_DATA_FORMAT_INVALID. */
432 scratch_dword3 |=
433 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
434 }
435
436 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
437 (user_sgpr * 4), 4);
438 radeon_emit(cs, scratch_dword0);
439 radeon_emit(cs, scratch_dword1);
440 radeon_emit(cs, scratch_dword2);
441 radeon_emit(cs, scratch_dword3);
442 }
443
444 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
445 const amd_kernel_code_t *code_object,
446 const struct pipe_grid_info *info,
447 uint64_t kernel_args_va)
448 {
449 struct si_compute *program = sctx->cs_shader_state.program;
450 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
451
452 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
453 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
454 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
455 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
456 };
457
458 unsigned i, user_sgpr = 0;
459 if (AMD_HSA_BITS_GET(code_object->code_properties,
460 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
461 if (code_object->workitem_private_segment_byte_size > 0) {
462 setup_scratch_rsrc_user_sgprs(sctx, code_object,
463 user_sgpr);
464 }
465 user_sgpr += 4;
466 }
467
468 if (AMD_HSA_BITS_GET(code_object->code_properties,
469 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
470 struct dispatch_packet dispatch;
471 unsigned dispatch_offset;
472 struct r600_resource *dispatch_buf = NULL;
473 uint64_t dispatch_va;
474
475 /* Upload dispatch ptr */
476 memset(&dispatch, 0, sizeof(dispatch));
477
478 dispatch.workgroup_size_x = info->block[0];
479 dispatch.workgroup_size_y = info->block[1];
480 dispatch.workgroup_size_z = info->block[2];
481
482 dispatch.grid_size_x = info->grid[0] * info->block[0];
483 dispatch.grid_size_y = info->grid[1] * info->block[1];
484 dispatch.grid_size_z = info->grid[2] * info->block[2];
485
486 dispatch.private_segment_size = program->private_size;
487 dispatch.group_segment_size = program->local_size;
488
489 dispatch.kernarg_address = kernel_args_va;
490
491 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
492 &dispatch, &dispatch_offset,
493 (struct pipe_resource**)&dispatch_buf);
494
495 if (!dispatch_buf) {
496 fprintf(stderr, "Error: Failed to allocate dispatch "
497 "packet.");
498 }
499 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
500 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
501
502 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
503
504 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
505 (user_sgpr * 4), 2);
506 radeon_emit(cs, dispatch_va);
507 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
508 S_008F04_STRIDE(0));
509
510 r600_resource_reference(&dispatch_buf, NULL);
511 user_sgpr += 2;
512 }
513
514 if (AMD_HSA_BITS_GET(code_object->code_properties,
515 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
516 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
517 (user_sgpr * 4), 2);
518 radeon_emit(cs, kernel_args_va);
519 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
520 S_008F04_STRIDE(0));
521 user_sgpr += 2;
522 }
523
524 for (i = 0; i < 3 && user_sgpr < 16; i++) {
525 if (code_object->code_properties & workgroup_count_masks[i]) {
526 radeon_set_sh_reg_seq(cs,
527 R_00B900_COMPUTE_USER_DATA_0 +
528 (user_sgpr * 4), 1);
529 radeon_emit(cs, info->grid[i]);
530 user_sgpr += 1;
531 }
532 }
533 }
534
535 static void si_upload_compute_input(struct si_context *sctx,
536 const amd_kernel_code_t *code_object,
537 const struct pipe_grid_info *info)
538 {
539 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
540 struct si_compute *program = sctx->cs_shader_state.program;
541 struct r600_resource *input_buffer = NULL;
542 unsigned kernel_args_size;
543 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
544 uint32_t kernel_args_offset = 0;
545 uint32_t *kernel_args;
546 void *kernel_args_ptr;
547 uint64_t kernel_args_va;
548 unsigned i;
549
550 /* The extra num_work_size_bytes are for work group / work item size information */
551 kernel_args_size = program->input_size + num_work_size_bytes;
552
553 u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
554 &kernel_args_offset,
555 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
556
557 kernel_args = (uint32_t*)kernel_args_ptr;
558 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
559
560 if (!code_object) {
561 for (i = 0; i < 3; i++) {
562 kernel_args[i] = info->grid[i];
563 kernel_args[i + 3] = info->grid[i] * info->block[i];
564 kernel_args[i + 6] = info->block[i];
565 }
566 }
567
568 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
569 program->input_size);
570
571
572 for (i = 0; i < (kernel_args_size / 4); i++) {
573 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
574 kernel_args[i]);
575 }
576
577
578 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
579 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
580
581 if (code_object) {
582 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
583 } else {
584 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
585 radeon_emit(cs, kernel_args_va);
586 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
587 S_008F04_STRIDE(0));
588 }
589
590 r600_resource_reference(&input_buffer, NULL);
591 }
592
593 static void si_setup_tgsi_grid(struct si_context *sctx,
594 const struct pipe_grid_info *info)
595 {
596 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
597 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
598 4 * SI_SGPR_GRID_SIZE;
599
600 if (info->indirect) {
601 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
602 uint64_t va = base_va + info->indirect_offset;
603 int i;
604
605 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
606 (struct r600_resource *)info->indirect,
607 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
608
609 for (i = 0; i < 3; ++i) {
610 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
611 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
612 COPY_DATA_DST_SEL(COPY_DATA_REG));
613 radeon_emit(cs, (va + 4 * i));
614 radeon_emit(cs, (va + 4 * i) >> 32);
615 radeon_emit(cs, (grid_size_reg >> 2) + i);
616 radeon_emit(cs, 0);
617 }
618 } else {
619 struct si_compute *program = sctx->cs_shader_state.program;
620
621 radeon_set_sh_reg_seq(cs, grid_size_reg, program->variable_group_size ? 6 : 3);
622 radeon_emit(cs, info->grid[0]);
623 radeon_emit(cs, info->grid[1]);
624 radeon_emit(cs, info->grid[2]);
625 if (program->variable_group_size) {
626 radeon_emit(cs, info->block[0]);
627 radeon_emit(cs, info->block[1]);
628 radeon_emit(cs, info->block[2]);
629 }
630 }
631 }
632
633 static void si_emit_dispatch_packets(struct si_context *sctx,
634 const struct pipe_grid_info *info)
635 {
636 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
637 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
638 unsigned waves_per_threadgroup =
639 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
640
641 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
642 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
643
644 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
645 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
646 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
647 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
648
649 if (info->indirect) {
650 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
651
652 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
653 (struct r600_resource *)info->indirect,
654 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
655
656 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
657 PKT3_SHADER_TYPE_S(1));
658 radeon_emit(cs, 1);
659 radeon_emit(cs, base_va);
660 radeon_emit(cs, base_va >> 32);
661
662 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
663 PKT3_SHADER_TYPE_S(1));
664 radeon_emit(cs, info->indirect_offset);
665 radeon_emit(cs, 1);
666 } else {
667 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
668 PKT3_SHADER_TYPE_S(1));
669 radeon_emit(cs, info->grid[0]);
670 radeon_emit(cs, info->grid[1]);
671 radeon_emit(cs, info->grid[2]);
672 radeon_emit(cs, 1);
673 }
674 }
675
676
677 static void si_launch_grid(
678 struct pipe_context *ctx, const struct pipe_grid_info *info)
679 {
680 struct si_context *sctx = (struct si_context*)ctx;
681 struct si_compute *program = sctx->cs_shader_state.program;
682 const amd_kernel_code_t *code_object =
683 si_compute_get_code_object(program, info->pc);
684 int i;
685 /* HW bug workaround when CS threadgroups > 256 threads and async
686 * compute isn't used, i.e. only one compute job can run at a time.
687 * If async compute is possible, the threadgroup size must be limited
688 * to 256 threads on all queues to avoid the bug.
689 * Only SI and certain CIK chips are affected.
690 */
691 bool cs_regalloc_hang =
692 (sctx->b.chip_class == SI ||
693 sctx->b.family == CHIP_BONAIRE ||
694 sctx->b.family == CHIP_KABINI) &&
695 info->block[0] * info->block[1] * info->block[2] > 256;
696
697 if (cs_regalloc_hang)
698 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
699 SI_CONTEXT_CS_PARTIAL_FLUSH;
700
701 si_decompress_compute_textures(sctx);
702
703 /* Add buffer sizes for memory checking in need_cs_space. */
704 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
705 /* TODO: add the scratch buffer */
706
707 if (info->indirect) {
708 r600_context_add_resource_size(ctx, info->indirect);
709
710 /* The hw doesn't read the indirect buffer via TC L2. */
711 if (r600_resource(info->indirect)->TC_L2_dirty) {
712 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
713 r600_resource(info->indirect)->TC_L2_dirty = false;
714 }
715 }
716
717 si_need_cs_space(sctx);
718
719 if (!sctx->cs_shader_state.initialized)
720 si_initialize_compute(sctx);
721
722 if (sctx->b.flags)
723 si_emit_cache_flush(sctx);
724
725 if (!si_switch_compute_shader(sctx, program, &program->shader,
726 code_object, info->pc))
727 return;
728
729 si_upload_compute_shader_descriptors(sctx);
730 si_emit_compute_shader_userdata(sctx);
731
732 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
733 sctx->atoms.s.render_cond->emit(&sctx->b,
734 sctx->atoms.s.render_cond);
735 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
736 }
737
738 if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
739 si_upload_compute_input(sctx, code_object, info);
740
741 /* Global buffers */
742 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
743 struct r600_resource *buffer =
744 (struct r600_resource*)program->global_buffers[i];
745 if (!buffer) {
746 continue;
747 }
748 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
749 RADEON_USAGE_READWRITE,
750 RADEON_PRIO_COMPUTE_GLOBAL);
751 }
752
753 if (program->ir_type == PIPE_SHADER_IR_TGSI)
754 si_setup_tgsi_grid(sctx, info);
755
756 si_ce_pre_draw_synchronization(sctx);
757
758 si_emit_dispatch_packets(sctx, info);
759
760 si_ce_post_draw_synchronization(sctx);
761
762 sctx->compute_is_busy = true;
763 sctx->b.num_compute_calls++;
764 if (sctx->cs_shader_state.uses_scratch)
765 sctx->b.num_spill_compute_calls++;
766
767 if (cs_regalloc_hang)
768 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
769 }
770
771
772 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
773 struct si_compute *program = (struct si_compute *)state;
774 struct si_context *sctx = (struct si_context*)ctx;
775
776 if (!state) {
777 return;
778 }
779
780 if (program == sctx->cs_shader_state.program)
781 sctx->cs_shader_state.program = NULL;
782
783 if (program == sctx->cs_shader_state.emitted_program)
784 sctx->cs_shader_state.emitted_program = NULL;
785
786 si_shader_destroy(&program->shader);
787 FREE(program);
788 }
789
790 static void si_set_compute_resources(struct pipe_context * ctx_,
791 unsigned start, unsigned count,
792 struct pipe_surface ** surfaces) { }
793
794 void si_init_compute_functions(struct si_context *sctx)
795 {
796 sctx->b.b.create_compute_state = si_create_compute_state;
797 sctx->b.b.delete_compute_state = si_delete_compute_state;
798 sctx->b.b.bind_compute_state = si_bind_compute_state;
799 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
800 sctx->b.b.set_compute_resources = si_set_compute_resources;
801 sctx->b.b.set_global_binding = si_set_global_binding;
802 sctx->b.b.launch_grid = si_launch_grid;
803 }