2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 /* Recommended maximum sizes for optimal performance.
29 * Fall back to compute or SDMA if the size is greater.
31 #define CP_DMA_COPY_PERF_THRESHOLD (64 * 1024) /* copied from Vulkan */
32 #define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */
34 /* Set this if you want the ME to wait until CP DMA is done.
35 * It should be set on the last CP DMA packet. */
36 #define CP_DMA_SYNC (1 << 0)
38 /* Set this if the source data was used as a destination in a previous CP DMA
39 * packet. It's for preventing a read-after-write (RAW) hazard between two
41 #define CP_DMA_RAW_WAIT (1 << 1)
42 #define CP_DMA_CLEAR (1 << 3)
43 #define CP_DMA_PFP_SYNC_ME (1 << 4)
45 /* The max number of bytes that can be copied per packet. */
46 static inline unsigned cp_dma_max_byte_count(struct si_context
*sctx
)
48 unsigned max
= sctx
->chip_class
>= GFX9
?
49 S_414_BYTE_COUNT_GFX9(~0u) :
50 S_414_BYTE_COUNT_GFX6(~0u);
52 /* make it aligned for optimal performance */
53 return max
& ~(SI_CPDMA_ALIGNMENT
- 1);
57 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
58 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
61 static void si_emit_cp_dma(struct si_context
*sctx
, uint64_t dst_va
,
62 uint64_t src_va
, unsigned size
, unsigned flags
,
63 enum si_cache_policy cache_policy
)
65 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
66 uint32_t header
= 0, command
= 0;
68 assert(size
<= cp_dma_max_byte_count(sctx
));
69 assert(sctx
->chip_class
!= SI
|| cache_policy
== L2_BYPASS
);
71 if (sctx
->chip_class
>= GFX9
)
72 command
|= S_414_BYTE_COUNT_GFX9(size
);
74 command
|= S_414_BYTE_COUNT_GFX6(size
);
77 if (flags
& CP_DMA_SYNC
)
78 header
|= S_411_CP_SYNC(1);
80 if (sctx
->chip_class
>= GFX9
)
81 command
|= S_414_DISABLE_WR_CONFIRM_GFX9(1);
83 command
|= S_414_DISABLE_WR_CONFIRM_GFX6(1);
86 if (flags
& CP_DMA_RAW_WAIT
)
87 command
|= S_414_RAW_WAIT(1);
89 /* Src and dst flags. */
90 if (sctx
->chip_class
>= GFX9
&& !(flags
& CP_DMA_CLEAR
) &&
92 header
|= S_411_DST_SEL(V_411_NOWHERE
); /* prefetch only */
93 } else if (sctx
->chip_class
>= CIK
&& cache_policy
!= L2_BYPASS
) {
94 header
|= S_411_DST_SEL(V_411_DST_ADDR_TC_L2
) |
95 S_500_DST_CACHE_POLICY(cache_policy
== L2_STREAM
);
98 if (flags
& CP_DMA_CLEAR
) {
99 header
|= S_411_SRC_SEL(V_411_DATA
);
100 } else if (sctx
->chip_class
>= CIK
&& cache_policy
!= L2_BYPASS
) {
101 header
|= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2
) |
102 S_500_SRC_CACHE_POLICY(cache_policy
== L2_STREAM
);
105 if (sctx
->chip_class
>= CIK
) {
106 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
107 radeon_emit(cs
, header
);
108 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
109 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
110 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
111 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
112 radeon_emit(cs
, command
);
114 header
|= S_411_SRC_ADDR_HI(src_va
>> 32);
116 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
117 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
118 radeon_emit(cs
, header
); /* SRC_ADDR_HI [15:0] + flags. */
119 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
120 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
121 radeon_emit(cs
, command
);
124 /* CP DMA is executed in ME, but index buffers are read by PFP.
125 * This ensures that ME (CP DMA) is idle before PFP starts fetching
126 * indices. If we wanted to execute CP DMA in PFP, this packet
129 if (flags
& CP_DMA_PFP_SYNC_ME
) {
130 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
135 void si_cp_dma_wait_for_idle(struct si_context
*sctx
)
137 /* Issue a dummy DMA that copies zero bytes.
139 * The DMA engine will see that there's no work to do and skip this
140 * DMA request, however, the CP will see the sync flag and still wait
141 * for all DMAs to complete.
143 si_emit_cp_dma(sctx
, 0, 0, 0, CP_DMA_SYNC
, L2_BYPASS
);
146 static unsigned get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
147 enum si_cache_policy cache_policy
)
151 case SI_COHERENCY_NONE
:
153 case SI_COHERENCY_SHADER
:
154 assert(sctx
->chip_class
!= SI
|| cache_policy
== L2_BYPASS
);
155 return SI_CONTEXT_INV_SMEM_L1
|
156 SI_CONTEXT_INV_VMEM_L1
|
157 (cache_policy
== L2_BYPASS
? SI_CONTEXT_INV_GLOBAL_L2
: 0);
158 case SI_COHERENCY_CB_META
:
159 assert(sctx
->chip_class
>= GFX9
? cache_policy
!= L2_BYPASS
:
160 cache_policy
== L2_BYPASS
);
161 return SI_CONTEXT_FLUSH_AND_INV_CB
;
165 static enum si_cache_policy
get_cache_policy(struct si_context
*sctx
,
166 enum si_coherency coher
)
168 if ((sctx
->chip_class
>= GFX9
&& coher
== SI_COHERENCY_CB_META
) ||
169 (sctx
->chip_class
>= CIK
&& coher
== SI_COHERENCY_SHADER
))
175 static void si_cp_dma_prepare(struct si_context
*sctx
, struct pipe_resource
*dst
,
176 struct pipe_resource
*src
, unsigned byte_count
,
177 uint64_t remaining_size
, unsigned user_flags
,
178 enum si_coherency coher
, bool *is_first
,
179 unsigned *packet_flags
)
181 /* Fast exit for a CPDMA prefetch. */
182 if ((user_flags
& SI_CPDMA_SKIP_ALL
) == SI_CPDMA_SKIP_ALL
) {
187 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
188 /* Count memory usage in so that need_cs_space can take it into account. */
189 si_context_add_resource_size(sctx
, dst
);
191 si_context_add_resource_size(sctx
, src
);
194 if (!(user_flags
& SI_CPDMA_SKIP_CHECK_CS_SPACE
))
195 si_need_gfx_cs_space(sctx
);
197 /* This must be done after need_cs_space. */
198 if (!(user_flags
& SI_CPDMA_SKIP_BO_LIST_UPDATE
)) {
199 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
201 RADEON_USAGE_WRITE
, RADEON_PRIO_CP_DMA
);
203 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
205 RADEON_USAGE_READ
, RADEON_PRIO_CP_DMA
);
208 /* Flush the caches for the first copy only.
209 * Also wait for the previous CP DMA operations.
211 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
) && sctx
->flags
)
212 si_emit_cache_flush(sctx
);
214 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_BEFORE
) && *is_first
)
215 *packet_flags
|= CP_DMA_RAW_WAIT
;
219 /* Do the synchronization after the last dma, so that all data
220 * is written to memory.
222 if (!(user_flags
& SI_CPDMA_SKIP_SYNC_AFTER
) &&
223 byte_count
== remaining_size
) {
224 *packet_flags
|= CP_DMA_SYNC
;
226 if (coher
== SI_COHERENCY_SHADER
)
227 *packet_flags
|= CP_DMA_PFP_SYNC_ME
;
231 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
232 uint64_t offset
, uint64_t size
, unsigned value
,
233 enum si_coherency coher
,
234 enum si_cache_policy cache_policy
)
236 struct r600_resource
*rdst
= r600_resource(dst
);
237 uint64_t va
= rdst
->gpu_address
+ offset
;
238 bool is_first
= true;
240 assert(size
&& size
% 4 == 0);
242 /* Mark the buffer range of destination as valid (initialized),
243 * so that transfer_map knows it should wait for the GPU when mapping
245 util_range_add(&rdst
->valid_buffer_range
, offset
, offset
+ size
);
247 /* Flush the caches. */
248 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
249 SI_CONTEXT_CS_PARTIAL_FLUSH
|
250 get_flush_flags(sctx
, coher
, cache_policy
);
253 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(sctx
));
254 unsigned dma_flags
= CP_DMA_CLEAR
;
256 si_cp_dma_prepare(sctx
, dst
, NULL
, byte_count
, size
, 0, coher
,
257 &is_first
, &dma_flags
);
259 /* Emit the clear packet. */
260 si_emit_cp_dma(sctx
, va
, value
, byte_count
, dma_flags
, cache_policy
);
266 if (cache_policy
!= L2_BYPASS
)
267 rdst
->TC_L2_dirty
= true;
269 /* If it's not a framebuffer fast clear... */
270 if (coher
== SI_COHERENCY_SHADER
)
271 sctx
->num_cp_dma_calls
++;
274 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
275 uint64_t offset
, uint64_t size
, unsigned value
,
276 enum si_coherency coher
)
278 struct radeon_winsys
*ws
= sctx
->ws
;
279 struct r600_resource
*rdst
= r600_resource(dst
);
280 enum si_cache_policy cache_policy
= get_cache_policy(sctx
, coher
);
281 uint64_t dma_clear_size
;
286 dma_clear_size
= size
& ~3ull;
288 /* dma_clear_buffer can use clear_buffer on failure. Make sure that
289 * doesn't happen. We don't want an infinite recursion: */
291 !(dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
) &&
293 /* CP DMA is very slow. Always use SDMA for big clears. This
294 * alone improves DeusEx:MD performance by 70%. */
295 (size
> CP_DMA_CLEAR_PERF_THRESHOLD
||
296 /* Buffers not used by the GFX IB yet will be cleared by SDMA.
297 * This happens to move most buffer clears to SDMA, including
298 * DCC and CMASK clears, because pipe->clear clears them before
299 * si_emit_framebuffer_state (in a draw call) adds them.
300 * For example, DeusEx:MD has 21 buffer clears per frame and all
301 * of them are moved to SDMA thanks to this. */
302 !ws
->cs_is_buffer_referenced(sctx
->gfx_cs
, rdst
->buf
,
303 RADEON_USAGE_READWRITE
))) {
304 si_sdma_clear_buffer(sctx
, dst
, offset
, dma_clear_size
, value
);
306 offset
+= dma_clear_size
;
307 size
-= dma_clear_size
;
308 } else if (dma_clear_size
>= 4) {
309 si_cp_dma_clear_buffer(sctx
, dst
, offset
, dma_clear_size
, value
,
310 coher
, cache_policy
);
312 offset
+= dma_clear_size
;
313 size
-= dma_clear_size
;
317 /* Handle non-dword alignment.
319 * This function is called for embedded texture metadata clears,
320 * but those should always be properly aligned. */
321 assert(dst
->target
== PIPE_BUFFER
);
324 pipe_buffer_write(&sctx
->b
, dst
, offset
, size
, &value
);
328 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
329 struct pipe_resource
*dst
,
330 unsigned offset
, unsigned size
,
331 const void *clear_value_ptr
,
332 int clear_value_size
)
334 struct si_context
*sctx
= (struct si_context
*)ctx
;
335 uint32_t dword_value
;
338 assert(offset
% clear_value_size
== 0);
339 assert(size
% clear_value_size
== 0);
341 if (clear_value_size
> 4) {
342 const uint32_t *u32
= clear_value_ptr
;
343 bool clear_dword_duplicated
= true;
345 /* See if we can lower large fills to dword fills. */
346 for (i
= 1; i
< clear_value_size
/ 4; i
++)
347 if (u32
[0] != u32
[i
]) {
348 clear_dword_duplicated
= false;
352 if (!clear_dword_duplicated
) {
353 /* Use transform feedback for 64-bit, 96-bit, and
356 union pipe_color_union clear_value
;
358 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
359 si_blitter_begin(sctx
, SI_DISABLE_RENDER_COND
);
360 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
361 size
, clear_value_size
/ 4,
363 si_blitter_end(sctx
);
368 /* Expand the clear value to a dword. */
369 switch (clear_value_size
) {
371 dword_value
= *(uint8_t*)clear_value_ptr
;
372 dword_value
|= (dword_value
<< 8) |
373 (dword_value
<< 16) |
377 dword_value
= *(uint16_t*)clear_value_ptr
;
378 dword_value
|= dword_value
<< 16;
381 dword_value
= *(uint32_t*)clear_value_ptr
;
384 si_clear_buffer(sctx
, dst
, offset
, size
, dword_value
,
385 SI_COHERENCY_SHADER
);
389 * Realign the CP DMA engine. This must be done after a copy with an unaligned
392 * \param size Remaining size to the CP DMA alignment.
394 static void si_cp_dma_realign_engine(struct si_context
*sctx
, unsigned size
,
395 unsigned user_flags
, enum si_coherency coher
,
396 enum si_cache_policy cache_policy
,
400 unsigned dma_flags
= 0;
401 unsigned scratch_size
= SI_CPDMA_ALIGNMENT
* 2;
403 assert(size
< SI_CPDMA_ALIGNMENT
);
405 /* Use the scratch buffer as the dummy buffer. The 3D engine should be
406 * idle at this point.
408 if (!sctx
->scratch_buffer
||
409 sctx
->scratch_buffer
->b
.b
.width0
< scratch_size
) {
410 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
411 sctx
->scratch_buffer
=
412 si_aligned_buffer_create(&sctx
->screen
->b
,
413 SI_RESOURCE_FLAG_UNMAPPABLE
,
416 if (!sctx
->scratch_buffer
)
419 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
422 si_cp_dma_prepare(sctx
, &sctx
->scratch_buffer
->b
.b
,
423 &sctx
->scratch_buffer
->b
.b
, size
, size
, user_flags
,
424 coher
, is_first
, &dma_flags
);
426 va
= sctx
->scratch_buffer
->gpu_address
;
427 si_emit_cp_dma(sctx
, va
, va
+ SI_CPDMA_ALIGNMENT
, size
, dma_flags
,
432 * Do memcpy between buffers using CP DMA.
434 * \param user_flags bitmask of SI_CPDMA_*
436 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
437 struct pipe_resource
*dst
, struct pipe_resource
*src
,
438 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
439 unsigned user_flags
, enum si_coherency coher
,
440 enum si_cache_policy cache_policy
)
442 uint64_t main_dst_offset
, main_src_offset
;
443 unsigned skipped_size
= 0;
444 unsigned realign_size
= 0;
445 bool is_first
= true;
449 if (dst
!= src
|| dst_offset
!= src_offset
) {
450 /* Mark the buffer range of destination as valid (initialized),
451 * so that transfer_map knows it should wait for the GPU when mapping
453 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
457 dst_offset
+= r600_resource(dst
)->gpu_address
;
458 src_offset
+= r600_resource(src
)->gpu_address
;
460 /* The workarounds aren't needed on Fiji and beyond. */
461 if (sctx
->family
<= CHIP_CARRIZO
||
462 sctx
->family
== CHIP_STONEY
) {
463 /* If the size is not aligned, we must add a dummy copy at the end
464 * just to align the internal counter. Otherwise, the DMA engine
465 * would slow down by an order of magnitude for following copies.
467 if (size
% SI_CPDMA_ALIGNMENT
)
468 realign_size
= SI_CPDMA_ALIGNMENT
- (size
% SI_CPDMA_ALIGNMENT
);
470 /* If the copy begins unaligned, we must start copying from the next
471 * aligned block and the skipped part should be copied after everything
472 * else has been copied. Only the src alignment matters, not dst.
474 if (src_offset
% SI_CPDMA_ALIGNMENT
) {
475 skipped_size
= SI_CPDMA_ALIGNMENT
- (src_offset
% SI_CPDMA_ALIGNMENT
);
476 /* The main part will be skipped if the size is too small. */
477 skipped_size
= MIN2(skipped_size
, size
);
478 size
-= skipped_size
;
482 /* Flush the caches. */
483 if (!(user_flags
& SI_CPDMA_SKIP_GFX_SYNC
)) {
484 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
485 SI_CONTEXT_CS_PARTIAL_FLUSH
|
486 get_flush_flags(sctx
, coher
, cache_policy
);
489 /* This is the main part doing the copying. Src is always aligned. */
490 main_dst_offset
= dst_offset
+ skipped_size
;
491 main_src_offset
= src_offset
+ skipped_size
;
494 unsigned byte_count
= MIN2(size
, cp_dma_max_byte_count(sctx
));
495 unsigned dma_flags
= 0;
497 si_cp_dma_prepare(sctx
, dst
, src
, byte_count
,
498 size
+ skipped_size
+ realign_size
,
499 user_flags
, coher
, &is_first
, &dma_flags
);
501 si_emit_cp_dma(sctx
, main_dst_offset
, main_src_offset
,
502 byte_count
, dma_flags
, cache_policy
);
505 main_src_offset
+= byte_count
;
506 main_dst_offset
+= byte_count
;
509 /* Copy the part we skipped because src wasn't aligned. */
511 unsigned dma_flags
= 0;
513 si_cp_dma_prepare(sctx
, dst
, src
, skipped_size
,
514 skipped_size
+ realign_size
, user_flags
,
515 coher
, &is_first
, &dma_flags
);
517 si_emit_cp_dma(sctx
, dst_offset
, src_offset
, skipped_size
,
518 dma_flags
, cache_policy
);
521 /* Finally, realign the engine if the size wasn't aligned. */
523 si_cp_dma_realign_engine(sctx
, realign_size
, user_flags
, coher
,
524 cache_policy
, &is_first
);
528 void si_copy_buffer(struct si_context
*sctx
,
529 struct pipe_resource
*dst
, struct pipe_resource
*src
,
530 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
)
532 enum si_coherency coher
= SI_COHERENCY_SHADER
;
533 enum si_cache_policy cache_policy
= get_cache_policy(sctx
, coher
);
538 si_cp_dma_copy_buffer(sctx
, dst
, src
, dst_offset
, src_offset
, size
,
539 0, coher
, cache_policy
);
541 if (cache_policy
!= L2_BYPASS
)
542 r600_resource(dst
)->TC_L2_dirty
= true;
544 /* If it's not a prefetch... */
545 if (dst_offset
!= src_offset
)
546 sctx
->num_cp_dma_calls
++;
549 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
550 uint64_t offset
, unsigned size
)
552 assert(sctx
->chip_class
>= CIK
);
554 si_cp_dma_copy_buffer(sctx
, buf
, buf
, offset
, offset
, size
,
555 SI_CPDMA_SKIP_ALL
, SI_COHERENCY_SHADER
, L2_LRU
);
558 static void cik_prefetch_shader_async(struct si_context
*sctx
,
559 struct si_pm4_state
*state
)
561 struct pipe_resource
*bo
= &state
->bo
[0]->b
.b
;
562 assert(state
->nbo
== 1);
564 cik_prefetch_TC_L2_async(sctx
, bo
, 0, bo
->width0
);
567 static void cik_prefetch_VBO_descriptors(struct si_context
*sctx
)
569 if (!sctx
->vertex_elements
|| !sctx
->vertex_elements
->desc_list_byte_size
)
572 cik_prefetch_TC_L2_async(sctx
, &sctx
->vb_descriptors_buffer
->b
.b
,
573 sctx
->vb_descriptors_offset
,
574 sctx
->vertex_elements
->desc_list_byte_size
);
578 * Prefetch shaders and VBO descriptors.
580 * \param vertex_stage_only Whether only the the API VS and VBO descriptors
581 * should be prefetched.
583 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
)
585 unsigned mask
= sctx
->prefetch_L2_mask
;
588 /* Prefetch shaders and VBO descriptors to TC L2. */
589 if (sctx
->chip_class
>= GFX9
) {
590 /* Choose the right spot for the VBO prefetch. */
591 if (sctx
->tes_shader
.cso
) {
592 if (mask
& SI_PREFETCH_HS
)
593 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.hs
);
594 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
595 cik_prefetch_VBO_descriptors(sctx
);
596 if (vertex_stage_only
) {
597 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_HS
|
598 SI_PREFETCH_VBO_DESCRIPTORS
);
602 if (mask
& SI_PREFETCH_GS
)
603 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
604 if (mask
& SI_PREFETCH_VS
)
605 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
606 } else if (sctx
->gs_shader
.cso
) {
607 if (mask
& SI_PREFETCH_GS
)
608 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
609 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
610 cik_prefetch_VBO_descriptors(sctx
);
611 if (vertex_stage_only
) {
612 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_GS
|
613 SI_PREFETCH_VBO_DESCRIPTORS
);
617 if (mask
& SI_PREFETCH_VS
)
618 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
620 if (mask
& SI_PREFETCH_VS
)
621 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
622 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
623 cik_prefetch_VBO_descriptors(sctx
);
624 if (vertex_stage_only
) {
625 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_VS
|
626 SI_PREFETCH_VBO_DESCRIPTORS
);
632 /* Choose the right spot for the VBO prefetch. */
633 if (sctx
->tes_shader
.cso
) {
634 if (mask
& SI_PREFETCH_LS
)
635 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ls
);
636 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
637 cik_prefetch_VBO_descriptors(sctx
);
638 if (vertex_stage_only
) {
639 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_LS
|
640 SI_PREFETCH_VBO_DESCRIPTORS
);
644 if (mask
& SI_PREFETCH_HS
)
645 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.hs
);
646 if (mask
& SI_PREFETCH_ES
)
647 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.es
);
648 if (mask
& SI_PREFETCH_GS
)
649 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
650 if (mask
& SI_PREFETCH_VS
)
651 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
652 } else if (sctx
->gs_shader
.cso
) {
653 if (mask
& SI_PREFETCH_ES
)
654 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.es
);
655 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
656 cik_prefetch_VBO_descriptors(sctx
);
657 if (vertex_stage_only
) {
658 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_ES
|
659 SI_PREFETCH_VBO_DESCRIPTORS
);
663 if (mask
& SI_PREFETCH_GS
)
664 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.gs
);
665 if (mask
& SI_PREFETCH_VS
)
666 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
668 if (mask
& SI_PREFETCH_VS
)
669 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.vs
);
670 if (mask
& SI_PREFETCH_VBO_DESCRIPTORS
)
671 cik_prefetch_VBO_descriptors(sctx
);
672 if (vertex_stage_only
) {
673 sctx
->prefetch_L2_mask
&= ~(SI_PREFETCH_VS
|
674 SI_PREFETCH_VBO_DESCRIPTORS
);
680 if (mask
& SI_PREFETCH_PS
)
681 cik_prefetch_shader_async(sctx
, sctx
->queued
.named
.ps
);
683 sctx
->prefetch_L2_mask
= 0;
686 void si_init_cp_dma_functions(struct si_context
*sctx
)
688 sctx
->b
.clear_buffer
= si_pipe_clear_buffer
;