src/gallium/drivers/radeonsi/si_cp_dma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "sid.h"
  27
  28 /* Recommended maximum sizes for optimal performance.
  29  * Fall back to compute or SDMA if the size is greater.
  30  */
  31 #define CP_DMA_COPY_PERF_THRESHOLD      (64 * 1024) /* copied from Vulkan */
  32 #define CP_DMA_CLEAR_PERF_THRESHOLD     (32 * 1024) /* guess (clear is much slower) */
  33
  34 /* Set this if you want the ME to wait until CP DMA is done.
  35  * It should be set on the last CP DMA packet. */
  36 #define CP_DMA_SYNC             (1 << 0)
  37
  38 /* Set this if the source data was used as a destination in a previous CP DMA
  39  * packet. It's for preventing a read-after-write (RAW) hazard between two
  40  * CP DMA packets. */
  41 #define CP_DMA_RAW_WAIT         (1 << 1)
  42 #define CP_DMA_CLEAR            (1 << 3)
  43 #define CP_DMA_PFP_SYNC_ME      (1 << 4)
  44
  45 /* The max number of bytes that can be copied per packet. */
  46 static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
  47 {
  48         unsigned max = sctx->chip_class >= GFX9 ?
  49                                S_414_BYTE_COUNT_GFX9(~0u) :
  50                                S_414_BYTE_COUNT_GFX6(~0u);
  51
  52         /* make it aligned for optimal performance */
  53         return max & ~(SI_CPDMA_ALIGNMENT - 1);
  54 }
  55
  56
  57 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
  58  * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
  59  * clear value.
  60  */
  61 static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
  62                            uint64_t src_va, unsigned size, unsigned flags,
  63                            enum si_cache_policy cache_policy)
  64 {
  65         struct radeon_cmdbuf *cs = sctx->gfx_cs;
  66         uint32_t header = 0, command = 0;
  67
  68         assert(size <= cp_dma_max_byte_count(sctx));
  69         assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
  70
  71         if (sctx->chip_class >= GFX9)
  72                 command |= S_414_BYTE_COUNT_GFX9(size);
  73         else
  74                 command |= S_414_BYTE_COUNT_GFX6(size);
  75
  76         /* Sync flags. */
  77         if (flags & CP_DMA_SYNC)
  78                 header |= S_411_CP_SYNC(1);
  79         else {
  80                 if (sctx->chip_class >= GFX9)
  81                         command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
  82                 else
  83                         command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
  84         }
  85
  86         if (flags & CP_DMA_RAW_WAIT)
  87                 command |= S_414_RAW_WAIT(1);
  88
  89         /* Src and dst flags. */
  90         if (sctx->chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
  91             src_va == dst_va)
  92                 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
  93         else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS)
  94                 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
  95
  96         if (flags & CP_DMA_CLEAR)
  97                 header |= S_411_SRC_SEL(V_411_DATA);
  98         else if (sctx->chip_class >= CIK && cache_policy != L2_BYPASS)
  99                 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
 100
 101         if (sctx->chip_class >= CIK) {
 102                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
 103                 radeon_emit(cs, header);
 104                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 105                 radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
 106                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 107                 radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
 108                 radeon_emit(cs, command);
 109         } else {
 110                 header |= S_411_SRC_ADDR_HI(src_va >> 32);
 111
 112                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 113                 radeon_emit(cs, src_va);        /* SRC_ADDR_LO [31:0] */
 114                 radeon_emit(cs, header);        /* SRC_ADDR_HI [15:0] + flags. */
 115                 radeon_emit(cs, dst_va);        /* DST_ADDR_LO [31:0] */
 116                 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
 117                 radeon_emit(cs, command);
 118         }
 119
 120         /* CP DMA is executed in ME, but index buffers are read by PFP.
 121          * This ensures that ME (CP DMA) is idle before PFP starts fetching
 122          * indices. If we wanted to execute CP DMA in PFP, this packet
 123          * should precede it.
 124          */
 125         if (flags & CP_DMA_PFP_SYNC_ME) {
 126                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 127                 radeon_emit(cs, 0);
 128         }
 129 }
 130
 131 void si_cp_dma_wait_for_idle(struct si_context *sctx)
 132 {
 133         /* Issue a dummy DMA that copies zero bytes.
 134          *
 135          * The DMA engine will see that there's no work to do and skip this
 136          * DMA request, however, the CP will see the sync flag and still wait
 137          * for all DMAs to complete.
 138          */
 139         si_emit_cp_dma(sctx, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS);
 140 }
 141
 142 static unsigned get_flush_flags(struct si_context *sctx, enum si_coherency coher,
 143                                 enum si_cache_policy cache_policy)
 144 {
 145         switch (coher) {
 146         default:
 147         case SI_COHERENCY_NONE:
 148                 return 0;
 149         case SI_COHERENCY_SHADER:
 150                 assert(sctx->chip_class != SI || cache_policy == L2_BYPASS);
 151                 return SI_CONTEXT_INV_SMEM_L1 |
 152                        SI_CONTEXT_INV_VMEM_L1 |
 153                        (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_GLOBAL_L2 : 0);
 154         case SI_COHERENCY_CB_META:
 155                 assert(sctx->chip_class >= GFX9 ? cache_policy != L2_BYPASS :
 156                                                   cache_policy == L2_BYPASS);
 157                 return SI_CONTEXT_FLUSH_AND_INV_CB;
 158         }
 159 }
 160
 161 static enum si_cache_policy get_cache_policy(struct si_context *sctx,
 162                                              enum si_coherency coher)
 163 {
 164         if ((sctx->chip_class >= GFX9 && coher == SI_COHERENCY_CB_META) ||
 165             (sctx->chip_class >= CIK && coher == SI_COHERENCY_SHADER))
 166                 return L2_LRU;
 167
 168         return L2_BYPASS;
 169 }
 170
 171 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 172                               struct pipe_resource *src, unsigned byte_count,
 173                               uint64_t remaining_size, unsigned user_flags,
 174                               enum si_coherency coher, bool *is_first,
 175                               unsigned *packet_flags)
 176 {
 177         /* Fast exit for a CPDMA prefetch. */
 178         if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
 179                 *is_first = false;
 180                 return;
 181         }
 182
 183         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 184                 /* Count memory usage in so that need_cs_space can take it into account. */
 185                 si_context_add_resource_size(sctx, dst);
 186                 if (src)
 187                         si_context_add_resource_size(sctx, src);
 188         }
 189
 190         if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
 191                 si_need_gfx_cs_space(sctx);
 192
 193         /* This must be done after need_cs_space. */
 194         if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 195                 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
 196                                           r600_resource(dst),
 197                                           RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
 198                 if (src)
 199                         radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
 200                                                   r600_resource(src),
 201                                                   RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
 202         }
 203
 204         /* Flush the caches for the first copy only.
 205          * Also wait for the previous CP DMA operations.
 206          */
 207         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->flags)
 208                 si_emit_cache_flush(sctx);
 209
 210         if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
 211                 *packet_flags |= CP_DMA_RAW_WAIT;
 212
 213         *is_first = false;
 214
 215         /* Do the synchronization after the last dma, so that all data
 216          * is written to memory.
 217          */
 218         if (!(user_flags & SI_CPDMA_SKIP_SYNC_AFTER) &&
 219             byte_count == remaining_size) {
 220                 *packet_flags |= CP_DMA_SYNC;
 221
 222                 if (coher == SI_COHERENCY_SHADER)
 223                         *packet_flags |= CP_DMA_PFP_SYNC_ME;
 224         }
 225 }
 226
 227 void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 228                             uint64_t offset, uint64_t size, unsigned value,
 229                             enum si_coherency coher,
 230                             enum si_cache_policy cache_policy)
 231 {
 232         struct r600_resource *rdst = r600_resource(dst);
 233         uint64_t va = rdst->gpu_address + offset;
 234         bool is_first = true;
 235
 236         assert(size && size % 4 == 0);
 237
 238         /* Mark the buffer range of destination as valid (initialized),
 239          * so that transfer_map knows it should wait for the GPU when mapping
 240          * that range. */
 241         util_range_add(&rdst->valid_buffer_range, offset, offset + size);
 242
 243         /* Flush the caches. */
 244         sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 245                        SI_CONTEXT_CS_PARTIAL_FLUSH |
 246                        get_flush_flags(sctx, coher, cache_policy);
 247
 248         while (size) {
 249                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 250                 unsigned dma_flags = CP_DMA_CLEAR;
 251
 252                 si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0, coher,
 253                                   &is_first, &dma_flags);
 254
 255                 /* Emit the clear packet. */
 256                 si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, cache_policy);
 257
 258                 size -= byte_count;
 259                 va += byte_count;
 260         }
 261
 262         if (cache_policy != L2_BYPASS)
 263                 rdst->TC_L2_dirty = true;
 264
 265         /* If it's not a framebuffer fast clear... */
 266         if (coher == SI_COHERENCY_SHADER)
 267                 sctx->num_cp_dma_calls++;
 268 }
 269
 270 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 271                      uint64_t offset, uint64_t size, unsigned value,
 272                      enum si_coherency coher)
 273 {
 274         struct radeon_winsys *ws = sctx->ws;
 275         struct r600_resource *rdst = r600_resource(dst);
 276         enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
 277         uint64_t dma_clear_size;
 278
 279         if (!size)
 280                 return;
 281
 282         dma_clear_size = size & ~3ull;
 283
 284         /* dma_clear_buffer can use clear_buffer on failure. Make sure that
 285          * doesn't happen. We don't want an infinite recursion: */
 286         if (sctx->dma_cs &&
 287             !(dst->flags & PIPE_RESOURCE_FLAG_SPARSE) &&
 288             (offset % 4 == 0) &&
 289             /* CP DMA is very slow. Always use SDMA for big clears. This
 290              * alone improves DeusEx:MD performance by 70%. */
 291             (size > CP_DMA_CLEAR_PERF_THRESHOLD ||
 292              /* Buffers not used by the GFX IB yet will be cleared by SDMA.
 293               * This happens to move most buffer clears to SDMA, including
 294               * DCC and CMASK clears, because pipe->clear clears them before
 295               * si_emit_framebuffer_state (in a draw call) adds them.
 296               * For example, DeusEx:MD has 21 buffer clears per frame and all
 297               * of them are moved to SDMA thanks to this. */
 298              !ws->cs_is_buffer_referenced(sctx->gfx_cs, rdst->buf,
 299                                           RADEON_USAGE_READWRITE))) {
 300                 sctx->dma_clear_buffer(sctx, dst, offset, dma_clear_size, value);
 301
 302                 offset += dma_clear_size;
 303                 size -= dma_clear_size;
 304         } else if (dma_clear_size >= 4) {
 305                 si_cp_dma_clear_buffer(sctx, dst, offset, dma_clear_size, value,
 306                                        coher, cache_policy);
 307
 308                 offset += dma_clear_size;
 309                 size -= dma_clear_size;
 310         }
 311
 312         if (size) {
 313                 /* Handle non-dword alignment.
 314                  *
 315                  * This function is called for embedded texture metadata clears,
 316                  * but those should always be properly aligned. */
 317                 assert(dst->target == PIPE_BUFFER);
 318                 assert(size < 4);
 319
 320                 pipe_buffer_write(&sctx->b, dst, offset, size, &value);
 321         }
 322 }
 323
 324 static void si_pipe_clear_buffer(struct pipe_context *ctx,
 325                                  struct pipe_resource *dst,
 326                                  unsigned offset, unsigned size,
 327                                  const void *clear_value_ptr,
 328                                  int clear_value_size)
 329 {
 330         struct si_context *sctx = (struct si_context*)ctx;
 331         uint32_t dword_value;
 332         unsigned i;
 333
 334         assert(offset % clear_value_size == 0);
 335         assert(size % clear_value_size == 0);
 336
 337         if (clear_value_size > 4) {
 338                 const uint32_t *u32 = clear_value_ptr;
 339                 bool clear_dword_duplicated = true;
 340
 341                 /* See if we can lower large fills to dword fills. */
 342                 for (i = 1; i < clear_value_size / 4; i++)
 343                         if (u32[0] != u32[i]) {
 344                                 clear_dword_duplicated = false;
 345                                 break;
 346                         }
 347
 348                 if (!clear_dword_duplicated) {
 349                         /* Use transform feedback for 64-bit, 96-bit, and
 350                          * 128-bit fills.
 351                          */
 352                         union pipe_color_union clear_value;
 353
 354                         memcpy(&clear_value, clear_value_ptr, clear_value_size);
 355                         si_blitter_begin(sctx, SI_DISABLE_RENDER_COND);
 356                         util_blitter_clear_buffer(sctx->blitter, dst, offset,
 357                                                   size, clear_value_size / 4,
 358                                                   &clear_value);
 359                         si_blitter_end(sctx);
 360                         return;
 361                 }
 362         }
 363
 364         /* Expand the clear value to a dword. */
 365         switch (clear_value_size) {
 366         case 1:
 367                 dword_value = *(uint8_t*)clear_value_ptr;
 368                 dword_value |= (dword_value << 8) |
 369                                (dword_value << 16) |
 370                                (dword_value << 24);
 371                 break;
 372         case 2:
 373                 dword_value = *(uint16_t*)clear_value_ptr;
 374                 dword_value |= dword_value << 16;
 375                 break;
 376         default:
 377                 dword_value = *(uint32_t*)clear_value_ptr;
 378         }
 379
 380         si_clear_buffer(sctx, dst, offset, size, dword_value,
 381                         SI_COHERENCY_SHADER);
 382 }
 383
 384 /**
 385  * Realign the CP DMA engine. This must be done after a copy with an unaligned
 386  * size.
 387  *
 388  * \param size  Remaining size to the CP DMA alignment.
 389  */
 390 static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size,
 391                                      unsigned user_flags, enum si_coherency coher,
 392                                      enum si_cache_policy cache_policy,
 393                                      bool *is_first)
 394 {
 395         uint64_t va;
 396         unsigned dma_flags = 0;
 397         unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2;
 398
 399         assert(size < SI_CPDMA_ALIGNMENT);
 400
 401         /* Use the scratch buffer as the dummy buffer. The 3D engine should be
 402          * idle at this point.
 403          */
 404         if (!sctx->scratch_buffer ||
 405             sctx->scratch_buffer->b.b.width0 < scratch_size) {
 406                 r600_resource_reference(&sctx->scratch_buffer, NULL);
 407                 sctx->scratch_buffer =
 408                         si_aligned_buffer_create(&sctx->screen->b,
 409                                                    SI_RESOURCE_FLAG_UNMAPPABLE,
 410                                                    PIPE_USAGE_DEFAULT,
 411                                                    scratch_size, 256);
 412                 if (!sctx->scratch_buffer)
 413                         return;
 414
 415                 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
 416         }
 417
 418         si_cp_dma_prepare(sctx, &sctx->scratch_buffer->b.b,
 419                           &sctx->scratch_buffer->b.b, size, size, user_flags,
 420                           coher, is_first, &dma_flags);
 421
 422         va = sctx->scratch_buffer->gpu_address;
 423         si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
 424                        cache_policy);
 425 }
 426
 427 /**
 428  * Do memcpy between buffers using CP DMA.
 429  *
 430  * \param user_flags    bitmask of SI_CPDMA_*
 431  */
 432 void si_copy_buffer(struct si_context *sctx,
 433                     struct pipe_resource *dst, struct pipe_resource *src,
 434                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 435                     unsigned user_flags)
 436 {
 437         uint64_t main_dst_offset, main_src_offset;
 438         unsigned skipped_size = 0;
 439         unsigned realign_size = 0;
 440         enum si_coherency coher = SI_COHERENCY_SHADER;
 441         enum si_cache_policy cache_policy = get_cache_policy(sctx, coher);
 442         bool is_first = true;
 443
 444         if (!size)
 445                 return;
 446
 447         if (dst != src || dst_offset != src_offset) {
 448                 /* Mark the buffer range of destination as valid (initialized),
 449                  * so that transfer_map knows it should wait for the GPU when mapping
 450                  * that range. */
 451                 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
 452                                dst_offset + size);
 453         }
 454
 455         dst_offset += r600_resource(dst)->gpu_address;
 456         src_offset += r600_resource(src)->gpu_address;
 457
 458         /* The workarounds aren't needed on Fiji and beyond. */
 459         if (sctx->family <= CHIP_CARRIZO ||
 460             sctx->family == CHIP_STONEY) {
 461                 /* If the size is not aligned, we must add a dummy copy at the end
 462                  * just to align the internal counter. Otherwise, the DMA engine
 463                  * would slow down by an order of magnitude for following copies.
 464                  */
 465                 if (size % SI_CPDMA_ALIGNMENT)
 466                         realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
 467
 468                 /* If the copy begins unaligned, we must start copying from the next
 469                  * aligned block and the skipped part should be copied after everything
 470                  * else has been copied. Only the src alignment matters, not dst.
 471                  */
 472                 if (src_offset % SI_CPDMA_ALIGNMENT) {
 473                         skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT);
 474                         /* The main part will be skipped if the size is too small. */
 475                         skipped_size = MIN2(skipped_size, size);
 476                         size -= skipped_size;
 477                 }
 478         }
 479
 480         /* Flush the caches. */
 481         if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) {
 482                 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 483                                SI_CONTEXT_CS_PARTIAL_FLUSH |
 484                                get_flush_flags(sctx, coher, cache_policy);
 485         }
 486
 487         /* This is the main part doing the copying. Src is always aligned. */
 488         main_dst_offset = dst_offset + skipped_size;
 489         main_src_offset = src_offset + skipped_size;
 490
 491         while (size) {
 492                 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
 493                 unsigned dma_flags = 0;
 494
 495                 si_cp_dma_prepare(sctx, dst, src, byte_count,
 496                                   size + skipped_size + realign_size,
 497                                   user_flags, coher, &is_first, &dma_flags);
 498
 499                 si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
 500                                byte_count, dma_flags, cache_policy);
 501
 502                 size -= byte_count;
 503                 main_src_offset += byte_count;
 504                 main_dst_offset += byte_count;
 505         }
 506
 507         /* Copy the part we skipped because src wasn't aligned. */
 508         if (skipped_size) {
 509                 unsigned dma_flags = 0;
 510
 511                 si_cp_dma_prepare(sctx, dst, src, skipped_size,
 512                                   skipped_size + realign_size, user_flags,
 513                                   coher, &is_first, &dma_flags);
 514
 515                 si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size,
 516                                dma_flags, cache_policy);
 517         }
 518
 519         /* Finally, realign the engine if the size wasn't aligned. */
 520         if (realign_size) {
 521                 si_cp_dma_realign_engine(sctx, realign_size, user_flags, coher,
 522                                          cache_policy, &is_first);
 523         }
 524
 525         if (cache_policy != L2_BYPASS)
 526                 r600_resource(dst)->TC_L2_dirty = true;
 527
 528         /* If it's not a prefetch... */
 529         if (dst_offset != src_offset)
 530                 sctx->num_cp_dma_calls++;
 531 }
 532
 533 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 534                               uint64_t offset, unsigned size)
 535 {
 536         assert(sctx->chip_class >= CIK);
 537
 538         si_copy_buffer(sctx, buf, buf, offset, offset, size, SI_CPDMA_SKIP_ALL);
 539 }
 540
 541 static void cik_prefetch_shader_async(struct si_context *sctx,
 542                                       struct si_pm4_state *state)
 543 {
 544         struct pipe_resource *bo = &state->bo[0]->b.b;
 545         assert(state->nbo == 1);
 546
 547         cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
 548 }
 549
 550 static void cik_prefetch_VBO_descriptors(struct si_context *sctx)
 551 {
 552         if (!sctx->vertex_elements)
 553                 return;
 554
 555         cik_prefetch_TC_L2_async(sctx, &sctx->vb_descriptors_buffer->b.b,
 556                                  sctx->vb_descriptors_offset,
 557                                  sctx->vertex_elements->desc_list_byte_size);
 558 }
 559
 560 /**
 561  * Prefetch shaders and VBO descriptors.
 562  *
 563  * \param vertex_stage_only  Whether only the the API VS and VBO descriptors
 564  *                           should be prefetched.
 565  */
 566 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only)
 567 {
 568         unsigned mask = sctx->prefetch_L2_mask;
 569         assert(mask);
 570
 571         /* Prefetch shaders and VBO descriptors to TC L2. */
 572         if (sctx->chip_class >= GFX9) {
 573                 /* Choose the right spot for the VBO prefetch. */
 574                 if (sctx->tes_shader.cso) {
 575                         if (mask & SI_PREFETCH_HS)
 576                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 577                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 578                                 cik_prefetch_VBO_descriptors(sctx);
 579                         if (vertex_stage_only) {
 580                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_HS |
 581                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 582                                 return;
 583                         }
 584
 585                         if (mask & SI_PREFETCH_GS)
 586                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 587                         if (mask & SI_PREFETCH_VS)
 588                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 589                 } else if (sctx->gs_shader.cso) {
 590                         if (mask & SI_PREFETCH_GS)
 591                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 592                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 593                                 cik_prefetch_VBO_descriptors(sctx);
 594                         if (vertex_stage_only) {
 595                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_GS |
 596                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 597                                 return;
 598                         }
 599
 600                         if (mask & SI_PREFETCH_VS)
 601                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 602                 } else {
 603                         if (mask & SI_PREFETCH_VS)
 604                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 605                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 606                                 cik_prefetch_VBO_descriptors(sctx);
 607                         if (vertex_stage_only) {
 608                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_VS |
 609                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 610                                 return;
 611                         }
 612                 }
 613         } else {
 614                 /* SI-CI-VI */
 615                 /* Choose the right spot for the VBO prefetch. */
 616                 if (sctx->tes_shader.cso) {
 617                         if (mask & SI_PREFETCH_LS)
 618                                 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
 619                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 620                                 cik_prefetch_VBO_descriptors(sctx);
 621                         if (vertex_stage_only) {
 622                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_LS |
 623                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 624                                 return;
 625                         }
 626
 627                         if (mask & SI_PREFETCH_HS)
 628                                 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
 629                         if (mask & SI_PREFETCH_ES)
 630                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 631                         if (mask & SI_PREFETCH_GS)
 632                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 633                         if (mask & SI_PREFETCH_VS)
 634                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 635                 } else if (sctx->gs_shader.cso) {
 636                         if (mask & SI_PREFETCH_ES)
 637                                 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
 638                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 639                                 cik_prefetch_VBO_descriptors(sctx);
 640                         if (vertex_stage_only) {
 641                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_ES |
 642                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 643                                 return;
 644                         }
 645
 646                         if (mask & SI_PREFETCH_GS)
 647                                 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
 648                         if (mask & SI_PREFETCH_VS)
 649                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 650                 } else {
 651                         if (mask & SI_PREFETCH_VS)
 652                                 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
 653                         if (mask & SI_PREFETCH_VBO_DESCRIPTORS)
 654                                 cik_prefetch_VBO_descriptors(sctx);
 655                         if (vertex_stage_only) {
 656                                 sctx->prefetch_L2_mask &= ~(SI_PREFETCH_VS |
 657                                                             SI_PREFETCH_VBO_DESCRIPTORS);
 658                                 return;
 659                         }
 660                 }
 661         }
 662
 663         if (mask & SI_PREFETCH_PS)
 664                 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
 665
 666         sctx->prefetch_L2_mask = 0;
 667 }
 668
 669 void si_init_cp_dma_functions(struct si_context *sctx)
 670 {
 671         sctx->b.clear_buffer = si_pipe_clear_buffer;
 672 }