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[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "sid.h"
61 #include "gfx9d.h"
62
63 #include "util/u_format.h"
64 #include "util/u_memory.h"
65 #include "util/u_upload_mgr.h"
66
67
68 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * (alpha = 0).
70 *
71 * For images, all fields must be zero except for the swizzle, which
72 * supports arbitrary combinations of 0s and 1s. The texture type must be
73 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 *
75 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 *
77 * This is the only reason why the buffer descriptor must be in words [4:7].
78 */
79 static uint32_t null_texture_descriptor[8] = {
80 0,
81 0,
82 0,
83 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
84 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
85 /* the rest must contain zeros, which is also used by the buffer
86 * descriptor */
87 };
88
89 static uint32_t null_image_descriptor[8] = {
90 0,
91 0,
92 0,
93 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
94 /* the rest must contain zeros, which is also used by the buffer
95 * descriptor */
96 };
97
98 static void si_init_descriptors(struct si_descriptors *desc,
99 unsigned shader_userdata_index,
100 unsigned element_dw_size,
101 unsigned num_elements,
102 const uint32_t *null_descriptor,
103 unsigned *ce_offset)
104 {
105 int i;
106
107 assert(num_elements <= sizeof(desc->dirty_mask)*8);
108
109 desc->list = CALLOC(num_elements, element_dw_size * 4);
110 desc->element_dw_size = element_dw_size;
111 desc->num_elements = num_elements;
112 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
113 desc->shader_userdata_offset = shader_userdata_index * 4;
114
115 if (ce_offset) {
116 desc->uses_ce = true;
117 desc->ce_offset = *ce_offset;
118
119 /* make sure that ce_offset stays 32 byte aligned */
120 *ce_offset += align(element_dw_size * num_elements * 4, 32);
121 }
122
123 /* Initialize the array to NULL descriptors if the element size is 8. */
124 if (null_descriptor) {
125 assert(element_dw_size % 8 == 0);
126 for (i = 0; i < num_elements * element_dw_size / 8; i++)
127 memcpy(desc->list + i * 8, null_descriptor,
128 8 * 4);
129 }
130 }
131
132 static void si_release_descriptors(struct si_descriptors *desc)
133 {
134 r600_resource_reference(&desc->buffer, NULL);
135 FREE(desc->list);
136 }
137
138 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
139 unsigned *out_offset, struct r600_resource **out_buf) {
140 uint64_t va;
141
142 u_suballocator_alloc(sctx->ce_suballocator, size,
143 sctx->screen->b.info.tcc_cache_line_size,
144 out_offset, (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib && desc->uses_ce) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.b.const_uploader, 0, list_size,
241 sctx->screen->b.info.tcc_cache_line_size,
242 &desc->buffer_offset,
243 (struct pipe_resource**)&desc->buffer, &ptr);
244 if (!desc->buffer)
245 return false; /* skip the draw call */
246
247 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
248 desc->gpu_list = ptr;
249
250 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
251 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
252 }
253 desc->dirty_mask = 0;
254
255 if (atom)
256 si_mark_atom_dirty(sctx, atom);
257
258 return true;
259 }
260
261 static void
262 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
263 {
264 desc->ce_ram_dirty = true;
265
266 if (!desc->buffer)
267 return;
268
269 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
270 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
271 }
272
273 /* SAMPLER VIEWS */
274
275 static unsigned
276 si_sampler_descriptors_idx(unsigned shader)
277 {
278 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
279 SI_SHADER_DESCS_SAMPLERS;
280 }
281
282 static struct si_descriptors *
283 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
284 {
285 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
286 }
287
288 static void si_release_sampler_views(struct si_sampler_views *views)
289 {
290 int i;
291
292 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
293 pipe_sampler_view_reference(&views->views[i], NULL);
294 }
295 }
296
297 static void si_sampler_view_add_buffer(struct si_context *sctx,
298 struct pipe_resource *resource,
299 enum radeon_bo_usage usage,
300 bool is_stencil_sampler,
301 bool check_mem)
302 {
303 struct r600_resource *rres;
304 struct r600_texture *rtex;
305 enum radeon_bo_priority priority;
306
307 if (!resource)
308 return;
309
310 if (resource->target != PIPE_BUFFER) {
311 struct r600_texture *tex = (struct r600_texture*)resource;
312
313 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
314 resource = &tex->flushed_depth_texture->resource.b.b;
315 }
316
317 rres = (struct r600_resource*)resource;
318 priority = r600_get_sampler_view_priority(rres);
319
320 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
321 rres, usage, priority,
322 check_mem);
323
324 if (resource->target == PIPE_BUFFER)
325 return;
326
327 /* Now add separate DCC or HTILE. */
328 rtex = (struct r600_texture*)resource;
329 if (rtex->dcc_separate_buffer) {
330 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
331 rtex->dcc_separate_buffer, usage,
332 RADEON_PRIO_DCC, check_mem);
333 }
334
335 if (rtex->htile_buffer &&
336 rtex->tc_compatible_htile &&
337 !is_stencil_sampler) {
338 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
339 rtex->htile_buffer, usage,
340 RADEON_PRIO_HTILE, check_mem);
341 }
342 }
343
344 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
345 struct si_sampler_views *views)
346 {
347 unsigned mask = views->enabled_mask;
348
349 /* Add buffers to the CS. */
350 while (mask) {
351 int i = u_bit_scan(&mask);
352 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
353
354 si_sampler_view_add_buffer(sctx, sview->base.texture,
355 RADEON_USAGE_READ,
356 sview->is_stencil_sampler, false);
357 }
358 }
359
360 /* Set buffer descriptor fields that can be changed by reallocations. */
361 static void si_set_buf_desc_address(struct r600_resource *buf,
362 uint64_t offset, uint32_t *state)
363 {
364 uint64_t va = buf->gpu_address + offset;
365
366 state[0] = va;
367 state[1] &= C_008F04_BASE_ADDRESS_HI;
368 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
369 }
370
371 /* Set texture descriptor fields that can be changed by reallocations.
372 *
373 * \param tex texture
374 * \param base_level_info information of the level of BASE_ADDRESS
375 * \param base_level the level of BASE_ADDRESS
376 * \param first_level pipe_sampler_view.u.tex.first_level
377 * \param block_width util_format_get_blockwidth()
378 * \param is_stencil select between separate Z & Stencil
379 * \param state descriptor to update
380 */
381 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
382 struct r600_texture *tex,
383 const struct legacy_surf_level *base_level_info,
384 unsigned base_level, unsigned first_level,
385 unsigned block_width, bool is_stencil,
386 uint32_t *state)
387 {
388 uint64_t va, meta_va = 0;
389
390 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
391 tex = tex->flushed_depth_texture;
392 is_stencil = false;
393 }
394
395 va = tex->resource.gpu_address;
396
397 if (sscreen->b.chip_class >= GFX9) {
398 /* Only stencil_offset needs to be added here. */
399 if (is_stencil)
400 va += tex->surface.u.gfx9.stencil_offset;
401 else
402 va += tex->surface.u.gfx9.surf_offset;
403 } else {
404 va += base_level_info->offset;
405 }
406
407 state[0] = va >> 8;
408 state[1] &= C_008F14_BASE_ADDRESS_HI;
409 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
410
411 if (sscreen->b.chip_class >= VI) {
412 state[6] &= C_008F28_COMPRESSION_EN;
413 state[7] = 0;
414
415 if (vi_dcc_enabled(tex, first_level)) {
416 meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
417 tex->dcc_offset;
418
419 if (sscreen->b.chip_class <= VI)
420 meta_va += base_level_info->dcc_offset;
421 } else if (tex->tc_compatible_htile && !is_stencil) {
422 meta_va = tex->htile_buffer->gpu_address;
423 }
424
425 if (meta_va) {
426 state[6] |= S_008F28_COMPRESSION_EN(1);
427 state[7] = meta_va >> 8;
428 }
429 }
430
431 if (sscreen->b.chip_class >= GFX9) {
432 state[3] &= C_008F1C_SW_MODE;
433 state[4] &= C_008F20_PITCH_GFX9;
434
435 if (is_stencil) {
436 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
437 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
438 } else {
439 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
440 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch);
441 }
442
443 state[5] &= C_008F24_META_DATA_ADDRESS &
444 C_008F24_META_PIPE_ALIGNED &
445 C_008F24_META_RB_ALIGNED;
446 if (meta_va) {
447 struct gfx9_surf_meta_flags meta;
448
449 if (tex->dcc_offset)
450 meta = tex->surface.u.gfx9.dcc;
451 else
452 meta = tex->surface.u.gfx9.htile;
453
454 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
455 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
456 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
457 }
458 } else {
459 /* SI-CI-VI */
460 unsigned pitch = base_level_info->nblk_x * block_width;
461 unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
462
463 state[3] &= C_008F1C_TILING_INDEX;
464 state[3] |= S_008F1C_TILING_INDEX(index);
465 state[4] &= C_008F20_PITCH_GFX6;
466 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
467 }
468 }
469
470 static void si_set_sampler_view(struct si_context *sctx,
471 unsigned shader,
472 unsigned slot, struct pipe_sampler_view *view,
473 bool disallow_early_out)
474 {
475 struct si_sampler_views *views = &sctx->samplers[shader].views;
476 struct si_sampler_view *rview = (struct si_sampler_view*)view;
477 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
478 uint32_t *desc = descs->list + slot * 16;
479
480 if (views->views[slot] == view && !disallow_early_out)
481 return;
482
483 if (view) {
484 struct r600_texture *rtex = (struct r600_texture *)view->texture;
485 bool is_buffer = rtex->resource.b.b.target == PIPE_BUFFER;
486
487 if (unlikely(!is_buffer && rview->dcc_incompatible)) {
488 if (vi_dcc_enabled(rtex, view->u.tex.first_level))
489 if (!r600_texture_disable_dcc(&sctx->b, rtex))
490 sctx->b.decompress_dcc(&sctx->b.b, rtex);
491
492 rview->dcc_incompatible = false;
493 }
494
495 assert(rtex); /* views with texture == NULL aren't supported */
496 pipe_sampler_view_reference(&views->views[slot], view);
497 memcpy(desc, rview->state, 8*4);
498
499 if (is_buffer) {
500 rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
501
502 si_set_buf_desc_address(&rtex->resource,
503 view->u.buf.offset,
504 desc + 4);
505 } else {
506 bool is_separate_stencil =
507 rtex->db_compatible &&
508 rview->is_stencil_sampler;
509
510 si_set_mutable_tex_desc_fields(sctx->screen, rtex,
511 rview->base_level_info,
512 rview->base_level,
513 rview->base.u.tex.first_level,
514 rview->block_width,
515 is_separate_stencil,
516 desc);
517 }
518
519 if (!is_buffer && rtex->fmask.size) {
520 memcpy(desc + 8,
521 rview->fmask_state, 8*4);
522 } else {
523 /* Disable FMASK and bind sampler state in [12:15]. */
524 memcpy(desc + 8,
525 null_texture_descriptor, 4*4);
526
527 if (views->sampler_states[slot])
528 memcpy(desc + 12,
529 views->sampler_states[slot]->val, 4*4);
530 }
531
532 views->enabled_mask |= 1u << slot;
533
534 /* Since this can flush, it must be done after enabled_mask is
535 * updated. */
536 si_sampler_view_add_buffer(sctx, view->texture,
537 RADEON_USAGE_READ,
538 rview->is_stencil_sampler, true);
539 } else {
540 pipe_sampler_view_reference(&views->views[slot], NULL);
541 memcpy(desc, null_texture_descriptor, 8*4);
542 /* Only clear the lower dwords of FMASK. */
543 memcpy(desc + 8, null_texture_descriptor, 4*4);
544 /* Re-set the sampler state if we are transitioning from FMASK. */
545 if (views->sampler_states[slot])
546 memcpy(desc + 12,
547 views->sampler_states[slot]->val, 4*4);
548
549 views->enabled_mask &= ~(1u << slot);
550 }
551
552 descs->dirty_mask |= 1u << slot;
553 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
554 }
555
556 static bool is_compressed_colortex(struct r600_texture *rtex)
557 {
558 return rtex->cmask.size || rtex->fmask.size ||
559 (rtex->dcc_offset && rtex->dirty_level_mask);
560 }
561
562 static bool depth_needs_decompression(struct r600_texture *rtex,
563 struct si_sampler_view *sview)
564 {
565 return rtex->db_compatible &&
566 (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
567 }
568
569 static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
570 unsigned shader)
571 {
572 struct si_textures_info *samplers = &sctx->samplers[shader];
573 unsigned shader_bit = 1 << shader;
574
575 if (samplers->depth_texture_mask ||
576 samplers->compressed_colortex_mask ||
577 sctx->images[shader].compressed_colortex_mask)
578 sctx->compressed_tex_shader_mask |= shader_bit;
579 else
580 sctx->compressed_tex_shader_mask &= ~shader_bit;
581 }
582
583 static void si_set_sampler_views(struct pipe_context *ctx,
584 enum pipe_shader_type shader, unsigned start,
585 unsigned count,
586 struct pipe_sampler_view **views)
587 {
588 struct si_context *sctx = (struct si_context *)ctx;
589 struct si_textures_info *samplers = &sctx->samplers[shader];
590 int i;
591
592 if (!count || shader >= SI_NUM_SHADERS)
593 return;
594
595 for (i = 0; i < count; i++) {
596 unsigned slot = start + i;
597
598 if (!views || !views[i]) {
599 samplers->depth_texture_mask &= ~(1u << slot);
600 samplers->compressed_colortex_mask &= ~(1u << slot);
601 si_set_sampler_view(sctx, shader, slot, NULL, false);
602 continue;
603 }
604
605 si_set_sampler_view(sctx, shader, slot, views[i], false);
606
607 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
608 struct r600_texture *rtex =
609 (struct r600_texture*)views[i]->texture;
610 struct si_sampler_view *rview = (struct si_sampler_view *)views[i];
611
612 if (depth_needs_decompression(rtex, rview)) {
613 samplers->depth_texture_mask |= 1u << slot;
614 } else {
615 samplers->depth_texture_mask &= ~(1u << slot);
616 }
617 if (is_compressed_colortex(rtex)) {
618 samplers->compressed_colortex_mask |= 1u << slot;
619 } else {
620 samplers->compressed_colortex_mask &= ~(1u << slot);
621 }
622
623 if (rtex->dcc_offset &&
624 p_atomic_read(&rtex->framebuffers_bound))
625 sctx->need_check_render_feedback = true;
626 } else {
627 samplers->depth_texture_mask &= ~(1u << slot);
628 samplers->compressed_colortex_mask &= ~(1u << slot);
629 }
630 }
631
632 si_update_compressed_tex_shader_mask(sctx, shader);
633 }
634
635 static void
636 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
637 {
638 unsigned mask = samplers->views.enabled_mask;
639
640 while (mask) {
641 int i = u_bit_scan(&mask);
642 struct pipe_resource *res = samplers->views.views[i]->texture;
643
644 if (res && res->target != PIPE_BUFFER) {
645 struct r600_texture *rtex = (struct r600_texture *)res;
646
647 if (is_compressed_colortex(rtex)) {
648 samplers->compressed_colortex_mask |= 1u << i;
649 } else {
650 samplers->compressed_colortex_mask &= ~(1u << i);
651 }
652 }
653 }
654 }
655
656 /* IMAGE VIEWS */
657
658 static unsigned
659 si_image_descriptors_idx(unsigned shader)
660 {
661 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
662 SI_SHADER_DESCS_IMAGES;
663 }
664
665 static struct si_descriptors*
666 si_image_descriptors(struct si_context *sctx, unsigned shader)
667 {
668 return &sctx->descriptors[si_image_descriptors_idx(shader)];
669 }
670
671 static void
672 si_release_image_views(struct si_images_info *images)
673 {
674 unsigned i;
675
676 for (i = 0; i < SI_NUM_IMAGES; ++i) {
677 struct pipe_image_view *view = &images->views[i];
678
679 pipe_resource_reference(&view->resource, NULL);
680 }
681 }
682
683 static void
684 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
685 {
686 uint mask = images->enabled_mask;
687
688 /* Add buffers to the CS. */
689 while (mask) {
690 int i = u_bit_scan(&mask);
691 struct pipe_image_view *view = &images->views[i];
692
693 assert(view->resource);
694
695 si_sampler_view_add_buffer(sctx, view->resource,
696 RADEON_USAGE_READWRITE, false, false);
697 }
698 }
699
700 static void
701 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
702 {
703 struct si_images_info *images = &ctx->images[shader];
704
705 if (images->enabled_mask & (1u << slot)) {
706 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
707
708 pipe_resource_reference(&images->views[slot].resource, NULL);
709 images->compressed_colortex_mask &= ~(1 << slot);
710
711 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
712 images->enabled_mask &= ~(1u << slot);
713 descs->dirty_mask |= 1u << slot;
714 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
715 }
716 }
717
718 static void
719 si_mark_image_range_valid(const struct pipe_image_view *view)
720 {
721 struct r600_resource *res = (struct r600_resource *)view->resource;
722
723 assert(res && res->b.b.target == PIPE_BUFFER);
724
725 util_range_add(&res->valid_buffer_range,
726 view->u.buf.offset,
727 view->u.buf.offset + view->u.buf.size);
728 }
729
730 static void si_set_shader_image(struct si_context *ctx,
731 unsigned shader,
732 unsigned slot, const struct pipe_image_view *view,
733 bool skip_decompress)
734 {
735 struct si_screen *screen = ctx->screen;
736 struct si_images_info *images = &ctx->images[shader];
737 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
738 struct r600_resource *res;
739 uint32_t *desc = descs->list + slot * 8;
740
741 if (!view || !view->resource) {
742 si_disable_shader_image(ctx, shader, slot);
743 return;
744 }
745
746 res = (struct r600_resource *)view->resource;
747
748 if (&images->views[slot] != view)
749 util_copy_image_view(&images->views[slot], view);
750
751 if (res->b.b.target == PIPE_BUFFER) {
752 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
753 si_mark_image_range_valid(view);
754
755 si_make_buffer_descriptor(screen, res,
756 view->format,
757 view->u.buf.offset,
758 view->u.buf.size, desc);
759 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
760
761 images->compressed_colortex_mask &= ~(1 << slot);
762 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
763 } else {
764 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
765 struct r600_texture *tex = (struct r600_texture *)res;
766 unsigned level = view->u.tex.level;
767 unsigned width, height, depth;
768 bool uses_dcc = vi_dcc_enabled(tex, level);
769
770 assert(!tex->is_depth);
771 assert(tex->fmask.size == 0);
772
773 if (uses_dcc && !skip_decompress &&
774 (view->access & PIPE_IMAGE_ACCESS_WRITE ||
775 !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
776 /* If DCC can't be disabled, at least decompress it.
777 * The decompression is relatively cheap if the surface
778 * has been decompressed already.
779 */
780 if (r600_texture_disable_dcc(&ctx->b, tex))
781 uses_dcc = false;
782 else
783 ctx->b.decompress_dcc(&ctx->b.b, tex);
784 }
785
786 if (is_compressed_colortex(tex)) {
787 images->compressed_colortex_mask |= 1 << slot;
788 } else {
789 images->compressed_colortex_mask &= ~(1 << slot);
790 }
791
792 if (uses_dcc &&
793 p_atomic_read(&tex->framebuffers_bound))
794 ctx->need_check_render_feedback = true;
795
796 /* Always force the base level to the selected level.
797 *
798 * This is required for 3D textures, where otherwise
799 * selecting a single slice for non-layered bindings
800 * fails. It doesn't hurt the other targets.
801 */
802 width = u_minify(res->b.b.width0, level);
803 height = u_minify(res->b.b.height0, level);
804 depth = u_minify(res->b.b.depth0, level);
805
806 si_make_texture_descriptor(screen, tex,
807 false, res->b.b.target,
808 view->format, swizzle,
809 0, 0,
810 view->u.tex.first_layer,
811 view->u.tex.last_layer,
812 width, height, depth,
813 desc, NULL);
814 si_set_mutable_tex_desc_fields(screen, tex,
815 &tex->surface.u.legacy.level[level],
816 level, level,
817 util_format_get_blockwidth(view->format),
818 false, desc);
819 }
820
821 images->enabled_mask |= 1u << slot;
822 descs->dirty_mask |= 1u << slot;
823 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
824
825 /* Since this can flush, it must be done after enabled_mask is updated. */
826 si_sampler_view_add_buffer(ctx, &res->b.b,
827 RADEON_USAGE_READWRITE, false, true);
828 }
829
830 static void
831 si_set_shader_images(struct pipe_context *pipe,
832 enum pipe_shader_type shader,
833 unsigned start_slot, unsigned count,
834 const struct pipe_image_view *views)
835 {
836 struct si_context *ctx = (struct si_context *)pipe;
837 unsigned i, slot;
838
839 assert(shader < SI_NUM_SHADERS);
840
841 if (!count)
842 return;
843
844 assert(start_slot + count <= SI_NUM_IMAGES);
845
846 if (views) {
847 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
848 si_set_shader_image(ctx, shader, slot, &views[i], false);
849 } else {
850 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
851 si_set_shader_image(ctx, shader, slot, NULL, false);
852 }
853
854 si_update_compressed_tex_shader_mask(ctx, shader);
855 }
856
857 static void
858 si_images_update_compressed_colortex_mask(struct si_images_info *images)
859 {
860 unsigned mask = images->enabled_mask;
861
862 while (mask) {
863 int i = u_bit_scan(&mask);
864 struct pipe_resource *res = images->views[i].resource;
865
866 if (res && res->target != PIPE_BUFFER) {
867 struct r600_texture *rtex = (struct r600_texture *)res;
868
869 if (is_compressed_colortex(rtex)) {
870 images->compressed_colortex_mask |= 1 << i;
871 } else {
872 images->compressed_colortex_mask &= ~(1 << i);
873 }
874 }
875 }
876 }
877
878 /* SAMPLER STATES */
879
880 static void si_bind_sampler_states(struct pipe_context *ctx,
881 enum pipe_shader_type shader,
882 unsigned start, unsigned count, void **states)
883 {
884 struct si_context *sctx = (struct si_context *)ctx;
885 struct si_textures_info *samplers = &sctx->samplers[shader];
886 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
887 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
888 int i;
889
890 if (!count || shader >= SI_NUM_SHADERS)
891 return;
892
893 for (i = 0; i < count; i++) {
894 unsigned slot = start + i;
895
896 if (!sstates[i] ||
897 sstates[i] == samplers->views.sampler_states[slot])
898 continue;
899
900 #ifdef DEBUG
901 assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
902 #endif
903 samplers->views.sampler_states[slot] = sstates[i];
904
905 /* If FMASK is bound, don't overwrite it.
906 * The sampler state will be set after FMASK is unbound.
907 */
908 if (samplers->views.views[slot] &&
909 samplers->views.views[slot]->texture &&
910 samplers->views.views[slot]->texture->target != PIPE_BUFFER &&
911 ((struct r600_texture*)samplers->views.views[slot]->texture)->fmask.size)
912 continue;
913
914 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
915 desc->dirty_mask |= 1u << slot;
916 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
917 }
918 }
919
920 /* BUFFER RESOURCES */
921
922 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
923 struct si_descriptors *descs,
924 unsigned num_buffers,
925 unsigned shader_userdata_index,
926 enum radeon_bo_usage shader_usage,
927 enum radeon_bo_priority priority,
928 unsigned *ce_offset)
929 {
930 buffers->shader_usage = shader_usage;
931 buffers->priority = priority;
932 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
933
934 si_init_descriptors(descs, shader_userdata_index, 4,
935 num_buffers, NULL, ce_offset);
936 }
937
938 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
939 struct si_descriptors *descs)
940 {
941 int i;
942
943 for (i = 0; i < descs->num_elements; i++) {
944 pipe_resource_reference(&buffers->buffers[i], NULL);
945 }
946
947 FREE(buffers->buffers);
948 }
949
950 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
951 struct si_buffer_resources *buffers)
952 {
953 unsigned mask = buffers->enabled_mask;
954
955 /* Add buffers to the CS. */
956 while (mask) {
957 int i = u_bit_scan(&mask);
958
959 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
960 (struct r600_resource*)buffers->buffers[i],
961 buffers->shader_usage, buffers->priority);
962 }
963 }
964
965 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
966 struct si_descriptors *descs,
967 unsigned idx, struct pipe_resource **buf,
968 unsigned *offset, unsigned *size)
969 {
970 pipe_resource_reference(buf, buffers->buffers[idx]);
971 if (*buf) {
972 struct r600_resource *res = r600_resource(*buf);
973 const uint32_t *desc = descs->list + idx * 4;
974 uint64_t va;
975
976 *size = desc[2];
977
978 assert(G_008F04_STRIDE(desc[1]) == 0);
979 va = ((uint64_t)desc[1] << 32) | desc[0];
980
981 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
982 *offset = va - res->gpu_address;
983 }
984 }
985
986 /* VERTEX BUFFERS */
987
988 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
989 {
990 struct si_descriptors *desc = &sctx->vertex_buffers;
991 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
992 int i;
993
994 for (i = 0; i < count; i++) {
995 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
996
997 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
998 continue;
999 if (!sctx->vertex_buffer[vb].buffer)
1000 continue;
1001
1002 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1003 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
1004 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1005 }
1006
1007 if (!desc->buffer)
1008 return;
1009 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1010 desc->buffer, RADEON_USAGE_READ,
1011 RADEON_PRIO_DESCRIPTORS);
1012 }
1013
1014 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
1015 {
1016 struct si_vertex_element *velems = sctx->vertex_elements;
1017 struct si_descriptors *desc = &sctx->vertex_buffers;
1018 unsigned i, count;
1019 unsigned desc_list_byte_size;
1020 unsigned first_vb_use_mask;
1021 uint64_t va;
1022 uint32_t *ptr;
1023
1024 if (!sctx->vertex_buffers_dirty || !velems)
1025 return true;
1026
1027 count = velems->count;
1028
1029 if (!count)
1030 return true;
1031
1032 desc_list_byte_size = velems->desc_list_byte_size;
1033 first_vb_use_mask = velems->first_vb_use_mask;
1034
1035 /* Vertex buffer descriptors are the only ones which are uploaded
1036 * directly through a staging buffer and don't go through
1037 * the fine-grained upload path.
1038 */
1039 u_upload_alloc(sctx->b.b.const_uploader, 0,
1040 desc_list_byte_size,
1041 si_optimal_tcc_alignment(sctx, desc_list_byte_size),
1042 &desc->buffer_offset,
1043 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
1044 if (!desc->buffer)
1045 return false;
1046
1047 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1048 desc->buffer, RADEON_USAGE_READ,
1049 RADEON_PRIO_DESCRIPTORS);
1050
1051 assert(count <= SI_MAX_ATTRIBS);
1052
1053 for (i = 0; i < count; i++) {
1054 struct pipe_vertex_element *ve = &velems->elements[i];
1055 struct pipe_vertex_buffer *vb;
1056 struct r600_resource *rbuffer;
1057 unsigned offset;
1058 unsigned vbo_index = ve->vertex_buffer_index;
1059 uint32_t *desc = &ptr[i*4];
1060
1061 vb = &sctx->vertex_buffer[vbo_index];
1062 rbuffer = (struct r600_resource*)vb->buffer;
1063 if (!rbuffer) {
1064 memset(desc, 0, 16);
1065 continue;
1066 }
1067
1068 offset = vb->buffer_offset + ve->src_offset;
1069 va = rbuffer->gpu_address + offset;
1070
1071 /* Fill in T# buffer resource description */
1072 desc[0] = va;
1073 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1074 S_008F04_STRIDE(vb->stride);
1075
1076 if (sctx->b.chip_class != VI && vb->stride) {
1077 /* Round up by rounding down and adding 1 */
1078 desc[2] = (vb->buffer->width0 - offset -
1079 velems->format_size[i]) /
1080 vb->stride + 1;
1081 } else {
1082 desc[2] = vb->buffer->width0 - offset;
1083 }
1084
1085 desc[3] = velems->rsrc_word3[i];
1086
1087 if (first_vb_use_mask & (1 << i)) {
1088 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1089 (struct r600_resource*)vb->buffer,
1090 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
1091 }
1092 }
1093
1094 /* Don't flush the const cache. It would have a very negative effect
1095 * on performance (confirmed by testing). New descriptors are always
1096 * uploaded to a fresh new buffer, so I don't think flushing the const
1097 * cache is needed. */
1098 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1099 if (sctx->b.chip_class >= CIK)
1100 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
1101 sctx->vertex_buffers_dirty = false;
1102 sctx->vertex_buffer_pointer_dirty = true;
1103 return true;
1104 }
1105
1106
1107 /* CONSTANT BUFFERS */
1108
1109 static unsigned
1110 si_const_buffer_descriptors_idx(unsigned shader)
1111 {
1112 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1113 SI_SHADER_DESCS_CONST_BUFFERS;
1114 }
1115
1116 static struct si_descriptors *
1117 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
1118 {
1119 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
1120 }
1121
1122 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
1123 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
1124 {
1125 void *tmp;
1126
1127 u_upload_alloc(sctx->b.b.const_uploader, 0, size,
1128 si_optimal_tcc_alignment(sctx, size),
1129 const_offset,
1130 (struct pipe_resource**)rbuffer, &tmp);
1131 if (*rbuffer)
1132 util_memcpy_cpu_to_le32(tmp, ptr, size);
1133 }
1134
1135 static void si_set_constant_buffer(struct si_context *sctx,
1136 struct si_buffer_resources *buffers,
1137 unsigned descriptors_idx,
1138 uint slot, const struct pipe_constant_buffer *input)
1139 {
1140 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1141 assert(slot < descs->num_elements);
1142 pipe_resource_reference(&buffers->buffers[slot], NULL);
1143
1144 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1145 * with a NULL buffer). We need to use a dummy buffer instead. */
1146 if (sctx->b.chip_class == CIK &&
1147 (!input || (!input->buffer && !input->user_buffer)))
1148 input = &sctx->null_const_buf;
1149
1150 if (input && (input->buffer || input->user_buffer)) {
1151 struct pipe_resource *buffer = NULL;
1152 uint64_t va;
1153
1154 /* Upload the user buffer if needed. */
1155 if (input->user_buffer) {
1156 unsigned buffer_offset;
1157
1158 si_upload_const_buffer(sctx,
1159 (struct r600_resource**)&buffer, input->user_buffer,
1160 input->buffer_size, &buffer_offset);
1161 if (!buffer) {
1162 /* Just unbind on failure. */
1163 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1164 return;
1165 }
1166 va = r600_resource(buffer)->gpu_address + buffer_offset;
1167 } else {
1168 pipe_resource_reference(&buffer, input->buffer);
1169 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1170 /* Only track usage for non-user buffers. */
1171 r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1172 }
1173
1174 /* Set the descriptor. */
1175 uint32_t *desc = descs->list + slot*4;
1176 desc[0] = va;
1177 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1178 S_008F04_STRIDE(0);
1179 desc[2] = input->buffer_size;
1180 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1181 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1182 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1183 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1184 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1185 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1186
1187 buffers->buffers[slot] = buffer;
1188 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1189 (struct r600_resource*)buffer,
1190 buffers->shader_usage,
1191 buffers->priority, true);
1192 buffers->enabled_mask |= 1u << slot;
1193 } else {
1194 /* Clear the descriptor. */
1195 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1196 buffers->enabled_mask &= ~(1u << slot);
1197 }
1198
1199 descs->dirty_mask |= 1u << slot;
1200 sctx->descriptors_dirty |= 1u << descriptors_idx;
1201 }
1202
1203 void si_set_rw_buffer(struct si_context *sctx,
1204 uint slot, const struct pipe_constant_buffer *input)
1205 {
1206 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1207 SI_DESCS_RW_BUFFERS, slot, input);
1208 }
1209
1210 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1211 enum pipe_shader_type shader, uint slot,
1212 const struct pipe_constant_buffer *input)
1213 {
1214 struct si_context *sctx = (struct si_context *)ctx;
1215
1216 if (shader >= SI_NUM_SHADERS)
1217 return;
1218
1219 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1220 si_const_buffer_descriptors_idx(shader),
1221 slot, input);
1222 }
1223
1224 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
1225 uint slot, struct pipe_constant_buffer *cbuf)
1226 {
1227 cbuf->user_buffer = NULL;
1228 si_get_buffer_from_descriptors(
1229 &sctx->const_buffers[shader],
1230 si_const_buffer_descriptors(sctx, shader),
1231 slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1232 }
1233
1234 /* SHADER BUFFERS */
1235
1236 static unsigned
1237 si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
1238 {
1239 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1240 SI_SHADER_DESCS_SHADER_BUFFERS;
1241 }
1242
1243 static struct si_descriptors *
1244 si_shader_buffer_descriptors(struct si_context *sctx,
1245 enum pipe_shader_type shader)
1246 {
1247 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1248 }
1249
1250 static void si_set_shader_buffers(struct pipe_context *ctx,
1251 enum pipe_shader_type shader,
1252 unsigned start_slot, unsigned count,
1253 const struct pipe_shader_buffer *sbuffers)
1254 {
1255 struct si_context *sctx = (struct si_context *)ctx;
1256 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1257 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1258 unsigned i;
1259
1260 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1261
1262 for (i = 0; i < count; ++i) {
1263 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1264 struct r600_resource *buf;
1265 unsigned slot = start_slot + i;
1266 uint32_t *desc = descs->list + slot * 4;
1267 uint64_t va;
1268
1269 if (!sbuffer || !sbuffer->buffer) {
1270 pipe_resource_reference(&buffers->buffers[slot], NULL);
1271 memset(desc, 0, sizeof(uint32_t) * 4);
1272 buffers->enabled_mask &= ~(1u << slot);
1273 descs->dirty_mask |= 1u << slot;
1274 sctx->descriptors_dirty |=
1275 1u << si_shader_buffer_descriptors_idx(shader);
1276 continue;
1277 }
1278
1279 buf = (struct r600_resource *)sbuffer->buffer;
1280 va = buf->gpu_address + sbuffer->buffer_offset;
1281
1282 desc[0] = va;
1283 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1284 S_008F04_STRIDE(0);
1285 desc[2] = sbuffer->buffer_size;
1286 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1287 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1288 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1289 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1290 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1291 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1292
1293 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1294 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1295 buffers->shader_usage,
1296 buffers->priority, true);
1297 buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
1298
1299 buffers->enabled_mask |= 1u << slot;
1300 descs->dirty_mask |= 1u << slot;
1301 sctx->descriptors_dirty |=
1302 1u << si_shader_buffer_descriptors_idx(shader);
1303
1304 util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
1305 sbuffer->buffer_offset + sbuffer->buffer_size);
1306 }
1307 }
1308
1309 void si_get_shader_buffers(struct si_context *sctx,
1310 enum pipe_shader_type shader,
1311 uint start_slot, uint count,
1312 struct pipe_shader_buffer *sbuf)
1313 {
1314 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1315 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1316
1317 for (unsigned i = 0; i < count; ++i) {
1318 si_get_buffer_from_descriptors(
1319 buffers, descs, start_slot + i,
1320 &sbuf[i].buffer, &sbuf[i].buffer_offset,
1321 &sbuf[i].buffer_size);
1322 }
1323 }
1324
1325 /* RING BUFFERS */
1326
1327 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1328 struct pipe_resource *buffer,
1329 unsigned stride, unsigned num_records,
1330 bool add_tid, bool swizzle,
1331 unsigned element_size, unsigned index_stride, uint64_t offset)
1332 {
1333 struct si_context *sctx = (struct si_context *)ctx;
1334 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1335 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1336
1337 /* The stride field in the resource descriptor has 14 bits */
1338 assert(stride < (1 << 14));
1339
1340 assert(slot < descs->num_elements);
1341 pipe_resource_reference(&buffers->buffers[slot], NULL);
1342
1343 if (buffer) {
1344 uint64_t va;
1345
1346 va = r600_resource(buffer)->gpu_address + offset;
1347
1348 switch (element_size) {
1349 default:
1350 assert(!"Unsupported ring buffer element size");
1351 case 0:
1352 case 2:
1353 element_size = 0;
1354 break;
1355 case 4:
1356 element_size = 1;
1357 break;
1358 case 8:
1359 element_size = 2;
1360 break;
1361 case 16:
1362 element_size = 3;
1363 break;
1364 }
1365
1366 switch (index_stride) {
1367 default:
1368 assert(!"Unsupported ring buffer index stride");
1369 case 0:
1370 case 8:
1371 index_stride = 0;
1372 break;
1373 case 16:
1374 index_stride = 1;
1375 break;
1376 case 32:
1377 index_stride = 2;
1378 break;
1379 case 64:
1380 index_stride = 3;
1381 break;
1382 }
1383
1384 if (sctx->b.chip_class >= VI && stride)
1385 num_records *= stride;
1386
1387 /* Set the descriptor. */
1388 uint32_t *desc = descs->list + slot*4;
1389 desc[0] = va;
1390 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1391 S_008F04_STRIDE(stride) |
1392 S_008F04_SWIZZLE_ENABLE(swizzle);
1393 desc[2] = num_records;
1394 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1395 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1396 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1397 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1398 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1399 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1400 S_008F0C_INDEX_STRIDE(index_stride) |
1401 S_008F0C_ADD_TID_ENABLE(add_tid);
1402
1403 if (sctx->b.chip_class >= GFX9)
1404 assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
1405 else
1406 desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
1407
1408 pipe_resource_reference(&buffers->buffers[slot], buffer);
1409 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1410 (struct r600_resource*)buffer,
1411 buffers->shader_usage, buffers->priority);
1412 buffers->enabled_mask |= 1u << slot;
1413 } else {
1414 /* Clear the descriptor. */
1415 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1416 buffers->enabled_mask &= ~(1u << slot);
1417 }
1418
1419 descs->dirty_mask |= 1u << slot;
1420 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1421 }
1422
1423 /* STREAMOUT BUFFERS */
1424
1425 static void si_set_streamout_targets(struct pipe_context *ctx,
1426 unsigned num_targets,
1427 struct pipe_stream_output_target **targets,
1428 const unsigned *offsets)
1429 {
1430 struct si_context *sctx = (struct si_context *)ctx;
1431 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1432 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1433 unsigned old_num_targets = sctx->b.streamout.num_targets;
1434 unsigned i, bufidx;
1435
1436 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1437 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1438 /* Since streamout uses vector writes which go through TC L2
1439 * and most other clients can use TC L2 as well, we don't need
1440 * to flush it.
1441 *
1442 * The only cases which requires flushing it is VGT DMA index
1443 * fetching (on <= CIK) and indirect draw data, which are rare
1444 * cases. Thus, flag the TC L2 dirtiness in the resource and
1445 * handle it at draw call time.
1446 */
1447 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1448 if (sctx->b.streamout.targets[i])
1449 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1450
1451 /* Invalidate the scalar cache in case a streamout buffer is
1452 * going to be used as a constant buffer.
1453 *
1454 * Invalidate TC L1, because streamout bypasses it (done by
1455 * setting GLC=1 in the store instruction), but it can contain
1456 * outdated data of streamout buffers.
1457 *
1458 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1459 * used as an input immediately.
1460 */
1461 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1462 SI_CONTEXT_INV_VMEM_L1 |
1463 SI_CONTEXT_VS_PARTIAL_FLUSH;
1464 }
1465
1466 /* All readers of the streamout targets need to be finished before we can
1467 * start writing to the targets.
1468 */
1469 if (num_targets)
1470 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1471 SI_CONTEXT_CS_PARTIAL_FLUSH;
1472
1473 /* Streamout buffers must be bound in 2 places:
1474 * 1) in VGT by setting the VGT_STRMOUT registers
1475 * 2) as shader resources
1476 */
1477
1478 /* Set the VGT regs. */
1479 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1480
1481 /* Set the shader resources.*/
1482 for (i = 0; i < num_targets; i++) {
1483 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1484
1485 if (targets[i]) {
1486 struct pipe_resource *buffer = targets[i]->buffer;
1487 uint64_t va = r600_resource(buffer)->gpu_address;
1488
1489 /* Set the descriptor.
1490 *
1491 * On VI, the format must be non-INVALID, otherwise
1492 * the buffer will be considered not bound and store
1493 * instructions will be no-ops.
1494 */
1495 uint32_t *desc = descs->list + bufidx*4;
1496 desc[0] = va;
1497 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1498 desc[2] = 0xffffffff;
1499 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1500 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1501 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1502 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1503 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1504
1505 /* Set the resource. */
1506 pipe_resource_reference(&buffers->buffers[bufidx],
1507 buffer);
1508 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1509 (struct r600_resource*)buffer,
1510 buffers->shader_usage,
1511 RADEON_PRIO_SHADER_RW_BUFFER,
1512 true);
1513 r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
1514
1515 buffers->enabled_mask |= 1u << bufidx;
1516 } else {
1517 /* Clear the descriptor and unset the resource. */
1518 memset(descs->list + bufidx*4, 0,
1519 sizeof(uint32_t) * 4);
1520 pipe_resource_reference(&buffers->buffers[bufidx],
1521 NULL);
1522 buffers->enabled_mask &= ~(1u << bufidx);
1523 }
1524 descs->dirty_mask |= 1u << bufidx;
1525 }
1526 for (; i < old_num_targets; i++) {
1527 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1528 /* Clear the descriptor and unset the resource. */
1529 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1530 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1531 buffers->enabled_mask &= ~(1u << bufidx);
1532 descs->dirty_mask |= 1u << bufidx;
1533 }
1534
1535 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1536 }
1537
1538 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1539 uint32_t *desc, uint64_t old_buf_va,
1540 struct pipe_resource *new_buf)
1541 {
1542 /* Retrieve the buffer offset from the descriptor. */
1543 uint64_t old_desc_va =
1544 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1545
1546 assert(old_buf_va <= old_desc_va);
1547 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1548
1549 /* Update the descriptor. */
1550 si_set_buf_desc_address(r600_resource(new_buf), offset_within_buffer,
1551 desc);
1552 }
1553
1554 /* INTERNAL CONST BUFFERS */
1555
1556 static void si_set_polygon_stipple(struct pipe_context *ctx,
1557 const struct pipe_poly_stipple *state)
1558 {
1559 struct si_context *sctx = (struct si_context *)ctx;
1560 struct pipe_constant_buffer cb = {};
1561 unsigned stipple[32];
1562 int i;
1563
1564 for (i = 0; i < 32; i++)
1565 stipple[i] = util_bitreverse(state->stipple[i]);
1566
1567 cb.user_buffer = stipple;
1568 cb.buffer_size = sizeof(stipple);
1569
1570 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1571 }
1572
1573 /* TEXTURE METADATA ENABLE/DISABLE */
1574
1575 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1576 * while the texture is bound, possibly by a different context. In that case,
1577 * call this function to update compressed_colortex_masks.
1578 */
1579 void si_update_compressed_colortex_masks(struct si_context *sctx)
1580 {
1581 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1582 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1583 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1584 si_update_compressed_tex_shader_mask(sctx, i);
1585 }
1586 }
1587
1588 /* BUFFER DISCARD/INVALIDATION */
1589
1590 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1591 static void si_reset_buffer_resources(struct si_context *sctx,
1592 struct si_buffer_resources *buffers,
1593 unsigned descriptors_idx,
1594 struct pipe_resource *buf,
1595 uint64_t old_va)
1596 {
1597 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1598 unsigned mask = buffers->enabled_mask;
1599
1600 while (mask) {
1601 unsigned i = u_bit_scan(&mask);
1602 if (buffers->buffers[i] == buf) {
1603 si_desc_reset_buffer_offset(&sctx->b.b,
1604 descs->list + i*4,
1605 old_va, buf);
1606 descs->dirty_mask |= 1u << i;
1607 sctx->descriptors_dirty |= 1u << descriptors_idx;
1608
1609 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1610 (struct r600_resource *)buf,
1611 buffers->shader_usage,
1612 buffers->priority, true);
1613 }
1614 }
1615 }
1616
1617 /* Reallocate a buffer a update all resource bindings where the buffer is
1618 * bound.
1619 *
1620 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1621 * idle by discarding its contents. Apps usually tell us when to do this using
1622 * map_buffer flags, for example.
1623 */
1624 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1625 {
1626 struct si_context *sctx = (struct si_context*)ctx;
1627 struct r600_resource *rbuffer = r600_resource(buf);
1628 unsigned i, shader;
1629 uint64_t old_va = rbuffer->gpu_address;
1630 unsigned num_elems = sctx->vertex_elements ?
1631 sctx->vertex_elements->count : 0;
1632
1633 /* Reallocate the buffer in the same pipe_resource. */
1634 r600_alloc_resource(&sctx->screen->b, rbuffer);
1635
1636 /* We changed the buffer, now we need to bind it where the old one
1637 * was bound. This consists of 2 things:
1638 * 1) Updating the resource descriptor and dirtying it.
1639 * 2) Adding a relocation to the CS, so that it's usable.
1640 */
1641
1642 /* Vertex buffers. */
1643 if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1644 for (i = 0; i < num_elems; i++) {
1645 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1646
1647 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1648 continue;
1649 if (!sctx->vertex_buffer[vb].buffer)
1650 continue;
1651
1652 if (sctx->vertex_buffer[vb].buffer == buf) {
1653 sctx->vertex_buffers_dirty = true;
1654 break;
1655 }
1656 }
1657 }
1658
1659 /* Streamout buffers. (other internal buffers can't be invalidated) */
1660 if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1661 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1662 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1663 struct si_descriptors *descs =
1664 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1665
1666 if (buffers->buffers[i] != buf)
1667 continue;
1668
1669 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1670 old_va, buf);
1671 descs->dirty_mask |= 1u << i;
1672 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1673
1674 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1675 rbuffer, buffers->shader_usage,
1676 RADEON_PRIO_SHADER_RW_BUFFER,
1677 true);
1678
1679 /* Update the streamout state. */
1680 if (sctx->b.streamout.begin_emitted)
1681 r600_emit_streamout_end(&sctx->b);
1682 sctx->b.streamout.append_bitmask =
1683 sctx->b.streamout.enabled_mask;
1684 r600_streamout_buffers_dirty(&sctx->b);
1685 }
1686 }
1687
1688 /* Constant and shader buffers. */
1689 if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1690 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1691 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1692 si_const_buffer_descriptors_idx(shader),
1693 buf, old_va);
1694 }
1695
1696 if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1697 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1698 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1699 si_shader_buffer_descriptors_idx(shader),
1700 buf, old_va);
1701 }
1702
1703 if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1704 /* Texture buffers - update bindings. */
1705 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1706 struct si_sampler_views *views = &sctx->samplers[shader].views;
1707 struct si_descriptors *descs =
1708 si_sampler_descriptors(sctx, shader);
1709 unsigned mask = views->enabled_mask;
1710
1711 while (mask) {
1712 unsigned i = u_bit_scan(&mask);
1713 if (views->views[i]->texture == buf) {
1714 si_desc_reset_buffer_offset(ctx,
1715 descs->list +
1716 i * 16 + 4,
1717 old_va, buf);
1718 descs->dirty_mask |= 1u << i;
1719 sctx->descriptors_dirty |=
1720 1u << si_sampler_descriptors_idx(shader);
1721
1722 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1723 rbuffer, RADEON_USAGE_READ,
1724 RADEON_PRIO_SAMPLER_BUFFER,
1725 true);
1726 }
1727 }
1728 }
1729 }
1730
1731 /* Shader images */
1732 if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1733 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1734 struct si_images_info *images = &sctx->images[shader];
1735 struct si_descriptors *descs =
1736 si_image_descriptors(sctx, shader);
1737 unsigned mask = images->enabled_mask;
1738
1739 while (mask) {
1740 unsigned i = u_bit_scan(&mask);
1741
1742 if (images->views[i].resource == buf) {
1743 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1744 si_mark_image_range_valid(&images->views[i]);
1745
1746 si_desc_reset_buffer_offset(
1747 ctx, descs->list + i * 8 + 4,
1748 old_va, buf);
1749 descs->dirty_mask |= 1u << i;
1750 sctx->descriptors_dirty |=
1751 1u << si_image_descriptors_idx(shader);
1752
1753 radeon_add_to_buffer_list_check_mem(
1754 &sctx->b, &sctx->b.gfx, rbuffer,
1755 RADEON_USAGE_READWRITE,
1756 RADEON_PRIO_SAMPLER_BUFFER, true);
1757 }
1758 }
1759 }
1760 }
1761 }
1762
1763 /* Update mutable image descriptor fields of all bound textures. */
1764 void si_update_all_texture_descriptors(struct si_context *sctx)
1765 {
1766 unsigned shader;
1767
1768 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1769 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1770 struct si_images_info *images = &sctx->images[shader];
1771 unsigned mask;
1772
1773 /* Images. */
1774 mask = images->enabled_mask;
1775 while (mask) {
1776 unsigned i = u_bit_scan(&mask);
1777 struct pipe_image_view *view = &images->views[i];
1778
1779 if (!view->resource ||
1780 view->resource->target == PIPE_BUFFER)
1781 continue;
1782
1783 si_set_shader_image(sctx, shader, i, view, true);
1784 }
1785
1786 /* Sampler views. */
1787 mask = samplers->enabled_mask;
1788 while (mask) {
1789 unsigned i = u_bit_scan(&mask);
1790 struct pipe_sampler_view *view = samplers->views[i];
1791
1792 if (!view ||
1793 !view->texture ||
1794 view->texture->target == PIPE_BUFFER)
1795 continue;
1796
1797 si_set_sampler_view(sctx, shader, i,
1798 samplers->views[i], true);
1799 }
1800
1801 si_update_compressed_tex_shader_mask(sctx, shader);
1802 }
1803 }
1804
1805 /* SHADER USER DATA */
1806
1807 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1808 unsigned shader)
1809 {
1810 sctx->shader_pointers_dirty |=
1811 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS,
1812 SI_NUM_SHADER_DESCS);
1813
1814 if (shader == PIPE_SHADER_VERTEX)
1815 sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL;
1816
1817 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1818 }
1819
1820 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1821 {
1822 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1823 sctx->vertex_buffer_pointer_dirty = sctx->vertex_buffers.buffer != NULL;
1824 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1825 }
1826
1827 /* Set a base register address for user data constants in the given shader.
1828 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1829 */
1830 static void si_set_user_data_base(struct si_context *sctx,
1831 unsigned shader, uint32_t new_base)
1832 {
1833 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1834
1835 if (*base != new_base) {
1836 *base = new_base;
1837
1838 if (new_base)
1839 si_mark_shader_pointers_dirty(sctx, shader);
1840 }
1841 }
1842
1843 /* This must be called when these shaders are changed from non-NULL to NULL
1844 * and vice versa:
1845 * - geometry shader
1846 * - tessellation control shader
1847 * - tessellation evaluation shader
1848 */
1849 void si_shader_change_notify(struct si_context *sctx)
1850 {
1851 /* VS can be bound as VS, ES, or LS. */
1852 if (sctx->tes_shader.cso) {
1853 if (sctx->b.chip_class >= GFX9) {
1854 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1855 R_00B430_SPI_SHADER_USER_DATA_LS_0);
1856 } else {
1857 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1858 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1859 }
1860 } else if (sctx->gs_shader.cso) {
1861 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1862 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1863 } else {
1864 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1865 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1866 }
1867
1868 /* TES can be bound as ES, VS, or not bound. */
1869 if (sctx->tes_shader.cso) {
1870 if (sctx->gs_shader.cso)
1871 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1872 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1873 else
1874 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1875 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1876 } else {
1877 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1878 }
1879 }
1880
1881 static void si_emit_shader_pointer(struct si_context *sctx,
1882 struct si_descriptors *desc,
1883 unsigned sh_base)
1884 {
1885 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1886 uint64_t va;
1887
1888 assert(desc->buffer);
1889
1890 va = desc->buffer->gpu_address +
1891 desc->buffer_offset;
1892
1893 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1894 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1895 radeon_emit(cs, va);
1896 radeon_emit(cs, va >> 32);
1897 }
1898
1899 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1900 struct r600_atom *atom)
1901 {
1902 unsigned mask;
1903 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1904 struct si_descriptors *descs;
1905
1906 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1907
1908 if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
1909 si_emit_shader_pointer(sctx, descs,
1910 R_00B030_SPI_SHADER_USER_DATA_PS_0);
1911 si_emit_shader_pointer(sctx, descs,
1912 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1913 si_emit_shader_pointer(sctx, descs,
1914 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1915
1916 /* GFX9 merged LS-HS and ES-GS. Only set RW_BUFFERS for ES and LS. */
1917 if (sctx->b.chip_class >= GFX9) {
1918 si_emit_shader_pointer(sctx, descs,
1919 R_00B430_SPI_SHADER_USER_DATA_LS_0);
1920 } else {
1921 si_emit_shader_pointer(sctx, descs,
1922 R_00B230_SPI_SHADER_USER_DATA_GS_0);
1923 si_emit_shader_pointer(sctx, descs,
1924 R_00B430_SPI_SHADER_USER_DATA_HS_0);
1925 }
1926 }
1927
1928 mask = sctx->shader_pointers_dirty &
1929 u_bit_consecutive(SI_DESCS_FIRST_SHADER,
1930 SI_DESCS_FIRST_COMPUTE - SI_DESCS_FIRST_SHADER);
1931
1932 while (mask) {
1933 unsigned i = u_bit_scan(&mask);
1934 unsigned shader = (i - SI_DESCS_FIRST_SHADER) / SI_NUM_SHADER_DESCS;
1935 unsigned base = sh_base[shader];
1936
1937 if (base)
1938 si_emit_shader_pointer(sctx, descs + i, base);
1939 }
1940 sctx->shader_pointers_dirty &=
1941 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
1942
1943 if (sctx->vertex_buffer_pointer_dirty) {
1944 si_emit_shader_pointer(sctx, &sctx->vertex_buffers,
1945 sh_base[PIPE_SHADER_VERTEX]);
1946 sctx->vertex_buffer_pointer_dirty = false;
1947 }
1948 }
1949
1950 void si_emit_compute_shader_userdata(struct si_context *sctx)
1951 {
1952 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1953 struct si_descriptors *descs = sctx->descriptors;
1954 unsigned compute_mask =
1955 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_SHADER_DESCS);
1956 unsigned mask = sctx->shader_pointers_dirty & compute_mask;
1957
1958 while (mask) {
1959 unsigned i = u_bit_scan(&mask);
1960
1961 si_emit_shader_pointer(sctx, descs + i, base);
1962 }
1963 sctx->shader_pointers_dirty &= ~compute_mask;
1964 }
1965
1966 /* INIT/DEINIT/UPLOAD */
1967
1968 void si_init_all_descriptors(struct si_context *sctx)
1969 {
1970 int i;
1971 unsigned ce_offset = 0;
1972
1973 for (i = 0; i < SI_NUM_SHADERS; i++) {
1974 /* GFX9 has only 4KB of CE, while previous chips had 32KB.
1975 * Rarely used descriptors don't use CE RAM.
1976 */
1977 bool big_ce = sctx->b.chip_class <= VI;
1978 bool images_use_ce = big_ce;
1979 bool shaderbufs_use_ce = big_ce ||
1980 i == PIPE_SHADER_COMPUTE;
1981 bool samplers_use_ce = big_ce ||
1982 i == PIPE_SHADER_FRAGMENT;
1983
1984 si_init_buffer_resources(&sctx->const_buffers[i],
1985 si_const_buffer_descriptors(sctx, i),
1986 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1987 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1988 &ce_offset);
1989 si_init_buffer_resources(&sctx->shader_buffers[i],
1990 si_shader_buffer_descriptors(sctx, i),
1991 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1992 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1993 shaderbufs_use_ce ? &ce_offset : NULL);
1994
1995 si_init_descriptors(si_sampler_descriptors(sctx, i),
1996 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1997 null_texture_descriptor,
1998 samplers_use_ce ? &ce_offset : NULL);
1999
2000 si_init_descriptors(si_image_descriptors(sctx, i),
2001 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
2002 null_image_descriptor,
2003 images_use_ce ? &ce_offset : NULL);
2004 }
2005
2006 si_init_buffer_resources(&sctx->rw_buffers,
2007 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
2008 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
2009 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
2010 &ce_offset);
2011 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
2012 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
2013
2014 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
2015
2016 if (sctx->b.chip_class >= GFX9)
2017 assert(ce_offset <= 4096);
2018 else
2019 assert(ce_offset <= 32768);
2020
2021 /* Set pipe_context functions. */
2022 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2023 sctx->b.b.set_shader_images = si_set_shader_images;
2024 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
2025 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2026 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
2027 sctx->b.b.set_sampler_views = si_set_sampler_views;
2028 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
2029 sctx->b.invalidate_buffer = si_invalidate_buffer;
2030
2031 /* Shader user data. */
2032 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
2033 si_emit_graphics_shader_userdata);
2034
2035 /* Set default and immutable mappings. */
2036 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
2037
2038 if (sctx->b.chip_class >= GFX9) {
2039 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
2040 R_00B430_SPI_SHADER_USER_DATA_LS_0);
2041 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
2042 R_00B330_SPI_SHADER_USER_DATA_ES_0);
2043 } else {
2044 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
2045 R_00B430_SPI_SHADER_USER_DATA_HS_0);
2046 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
2047 R_00B230_SPI_SHADER_USER_DATA_GS_0);
2048 }
2049 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
2050 }
2051
2052 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
2053 {
2054 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
2055 unsigned dirty = sctx->descriptors_dirty & mask;
2056
2057 /* Assume nothing will go wrong: */
2058 sctx->shader_pointers_dirty |= dirty;
2059
2060 while (dirty) {
2061 unsigned i = u_bit_scan(&dirty);
2062
2063 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
2064 &sctx->shader_userdata.atom))
2065 return false;
2066 }
2067
2068 sctx->descriptors_dirty &= ~mask;
2069 return true;
2070 }
2071
2072 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
2073 {
2074 /* Does not update rw_buffers as that is not needed for compute shaders
2075 * and the input buffer is using the same SGPR's anyway.
2076 */
2077 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
2078 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
2079 unsigned dirty = sctx->descriptors_dirty & mask;
2080
2081 /* Assume nothing will go wrong: */
2082 sctx->shader_pointers_dirty |= dirty;
2083
2084 while (dirty) {
2085 unsigned i = u_bit_scan(&dirty);
2086
2087 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
2088 return false;
2089 }
2090
2091 sctx->descriptors_dirty &= ~mask;
2092
2093 return true;
2094 }
2095
2096 void si_release_all_descriptors(struct si_context *sctx)
2097 {
2098 int i;
2099
2100 for (i = 0; i < SI_NUM_SHADERS; i++) {
2101 si_release_buffer_resources(&sctx->const_buffers[i],
2102 si_const_buffer_descriptors(sctx, i));
2103 si_release_buffer_resources(&sctx->shader_buffers[i],
2104 si_shader_buffer_descriptors(sctx, i));
2105 si_release_sampler_views(&sctx->samplers[i].views);
2106 si_release_image_views(&sctx->images[i]);
2107 }
2108 si_release_buffer_resources(&sctx->rw_buffers,
2109 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
2110
2111 for (i = 0; i < SI_NUM_DESCS; ++i)
2112 si_release_descriptors(&sctx->descriptors[i]);
2113 si_release_descriptors(&sctx->vertex_buffers);
2114 }
2115
2116 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
2117 {
2118 int i;
2119
2120 for (i = 0; i < SI_NUM_SHADERS; i++) {
2121 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
2122 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
2123 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
2124 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
2125 }
2126 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
2127 si_vertex_buffers_begin_new_cs(sctx);
2128
2129 for (i = 0; i < SI_NUM_DESCS; ++i)
2130 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
2131
2132 si_shader_userdata_begin_new_cs(sctx);
2133 }