2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
58 #include "util/format/u_format.h"
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/u_memory.h"
62 #include "util/u_upload_mgr.h"
64 /* NULL image and buffer descriptor for textures (alpha = 1) and images
67 * For images, all fields must be zero except for the swizzle, which
68 * supports arbitrary combinations of 0s and 1s. The texture type must be
69 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
71 * For buffers, all fields must be zero. If they are not, the hw hangs.
73 * This is the only reason why the buffer descriptor must be in words [4:7].
75 static uint32_t null_texture_descriptor
[8] = {
76 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
77 /* the rest must contain zeros, which is also used by the buffer
81 static uint32_t null_image_descriptor
[8] = {
82 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
89 uint64_t va
= desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
91 /* Sign-extend the 48-bit address. */
93 va
= (int64_t)va
>> 16;
97 static void si_init_descriptor_list(uint32_t *desc_list
, unsigned element_dw_size
,
98 unsigned num_elements
, const uint32_t *null_descriptor
)
102 /* Initialize the array to NULL descriptors if the element size is 8. */
103 if (null_descriptor
) {
104 assert(element_dw_size
% 8 == 0);
105 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
106 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
110 static void si_init_descriptors(struct si_descriptors
*desc
, short shader_userdata_rel_index
,
111 unsigned element_dw_size
, unsigned num_elements
)
113 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
114 desc
->element_dw_size
= element_dw_size
;
115 desc
->num_elements
= num_elements
;
116 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
117 desc
->slot_index_to_bind_directly
= -1;
120 static void si_release_descriptors(struct si_descriptors
*desc
)
122 si_resource_reference(&desc
->buffer
, NULL
);
126 static bool si_upload_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
)
128 unsigned slot_size
= desc
->element_dw_size
* 4;
129 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
130 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
132 /* Skip the upload if no shader is using the descriptors. dirty_mask
133 * will stay dirty and the descriptors will be uploaded when there is
134 * a shader using them.
139 /* If there is just one active descriptor, bind it directly. */
140 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
141 desc
->num_active_slots
== 1) {
142 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
* desc
->element_dw_size
];
144 /* The buffer is already in the buffer list. */
145 si_resource_reference(&desc
->buffer
, NULL
);
146 desc
->gpu_list
= NULL
;
147 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
148 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
153 unsigned buffer_offset
;
154 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
155 si_optimal_tcc_alignment(sctx
, upload_size
), &buffer_offset
,
156 (struct pipe_resource
**)&desc
->buffer
, (void **)&ptr
);
158 desc
->gpu_address
= 0;
159 return false; /* skip the draw call */
162 util_memcpy_cpu_to_le32(ptr
, (char *)desc
->list
+ first_slot_offset
, upload_size
);
163 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
165 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
166 RADEON_PRIO_DESCRIPTORS
);
168 /* The shader pointer should point to slot 0. */
169 buffer_offset
-= first_slot_offset
;
170 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
172 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
173 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
174 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
176 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
180 static void si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
185 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
186 RADEON_PRIO_DESCRIPTORS
);
191 static inline enum radeon_bo_priority
si_get_sampler_view_priority(struct si_resource
*res
)
193 if (res
->b
.b
.target
== PIPE_BUFFER
)
194 return RADEON_PRIO_SAMPLER_BUFFER
;
196 if (res
->b
.b
.nr_samples
> 1)
197 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
199 return RADEON_PRIO_SAMPLER_TEXTURE
;
202 static struct si_descriptors
*si_sampler_and_image_descriptors(struct si_context
*sctx
,
205 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
208 static void si_release_sampler_views(struct si_samplers
*samplers
)
212 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
213 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
217 static void si_sampler_view_add_buffer(struct si_context
*sctx
, struct pipe_resource
*resource
,
218 enum radeon_bo_usage usage
, bool is_stencil_sampler
,
221 struct si_texture
*tex
= (struct si_texture
*)resource
;
222 enum radeon_bo_priority priority
;
227 /* Use the flushed depth texture if direct sampling is unsupported. */
228 if (resource
->target
!= PIPE_BUFFER
&& tex
->is_depth
&&
229 !si_can_sample_zs(tex
, is_stencil_sampler
))
230 tex
= tex
->flushed_depth_texture
;
232 priority
= si_get_sampler_view_priority(&tex
->buffer
);
233 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
, check_mem
);
235 if (resource
->target
== PIPE_BUFFER
)
238 /* Add separate DCC. */
239 if (tex
->dcc_separate_buffer
) {
240 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
, usage
,
241 RADEON_PRIO_SEPARATE_META
, check_mem
);
245 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
, struct si_samplers
*samplers
)
247 unsigned mask
= samplers
->enabled_mask
;
249 /* Add buffers to the CS. */
251 int i
= u_bit_scan(&mask
);
252 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
254 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
255 sview
->is_stencil_sampler
, false);
259 /* Set buffer descriptor fields that can be changed by reallocations. */
260 static void si_set_buf_desc_address(struct si_resource
*buf
, uint64_t offset
, uint32_t *state
)
262 uint64_t va
= buf
->gpu_address
+ offset
;
265 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
266 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
269 /* Set texture descriptor fields that can be changed by reallocations.
272 * \param base_level_info information of the level of BASE_ADDRESS
273 * \param base_level the level of BASE_ADDRESS
274 * \param first_level pipe_sampler_view.u.tex.first_level
275 * \param block_width util_format_get_blockwidth()
276 * \param is_stencil select between separate Z & Stencil
277 * \param state descriptor to update
279 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
, struct si_texture
*tex
,
280 const struct legacy_surf_level
*base_level_info
,
281 unsigned base_level
, unsigned first_level
, unsigned block_width
,
282 bool is_stencil
, uint32_t *state
)
284 uint64_t va
, meta_va
= 0;
286 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
287 tex
= tex
->flushed_depth_texture
;
291 va
= tex
->buffer
.gpu_address
;
293 if (sscreen
->info
.chip_class
>= GFX9
) {
294 /* Only stencil_offset needs to be added here. */
296 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
298 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
300 va
+= base_level_info
->offset
;
304 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
305 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
307 /* Only macrotiled modes can set tile swizzle.
308 * GFX9 doesn't use (legacy) base_level_info.
310 if (sscreen
->info
.chip_class
>= GFX9
|| base_level_info
->mode
== RADEON_SURF_MODE_2D
)
311 state
[0] |= tex
->surface
.tile_swizzle
;
313 if (sscreen
->info
.chip_class
>= GFX8
) {
314 state
[6] &= C_008F28_COMPRESSION_EN
;
316 if (vi_dcc_enabled(tex
, first_level
)) {
318 (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
;
320 if (sscreen
->info
.chip_class
== GFX8
) {
321 meta_va
+= base_level_info
->dcc_offset
;
322 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
325 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
326 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
327 meta_va
|= dcc_tile_swizzle
;
328 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
329 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
330 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
334 state
[6] |= S_008F28_COMPRESSION_EN(1);
337 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
338 state
[7] = meta_va
>> 8;
340 if (sscreen
->info
.chip_class
>= GFX10
) {
341 state
[3] &= C_00A00C_SW_MODE
;
344 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
346 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
349 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
& C_00A018_META_PIPE_ALIGNED
;
352 struct gfx9_surf_meta_flags meta
;
354 if (tex
->surface
.dcc_offset
)
355 meta
= tex
->surface
.u
.gfx9
.dcc
;
357 meta
= tex
->surface
.u
.gfx9
.htile
;
359 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
360 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
363 state
[7] = meta_va
>> 16;
364 } else if (sscreen
->info
.chip_class
== GFX9
) {
365 state
[3] &= C_008F1C_SW_MODE
;
366 state
[4] &= C_008F20_PITCH
;
369 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
370 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
372 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
373 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
377 C_008F24_META_DATA_ADDRESS
& C_008F24_META_PIPE_ALIGNED
& C_008F24_META_RB_ALIGNED
;
379 struct gfx9_surf_meta_flags meta
;
381 if (tex
->surface
.dcc_offset
)
382 meta
= tex
->surface
.u
.gfx9
.dcc
;
384 meta
= tex
->surface
.u
.gfx9
.htile
;
386 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
387 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
388 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
392 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
393 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
395 state
[3] &= C_008F1C_TILING_INDEX
;
396 state
[3] |= S_008F1C_TILING_INDEX(index
);
397 state
[4] &= C_008F20_PITCH
;
398 state
[4] |= S_008F20_PITCH(pitch
- 1);
402 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
403 struct si_sampler_view
*sview
, struct si_texture
*tex
,
406 if (sview
&& sview
->is_integer
)
407 memcpy(desc
, sstate
->integer_val
, 4 * 4);
408 else if (tex
&& tex
->upgraded_depth
&& (!sview
|| !sview
->is_stencil_sampler
))
409 memcpy(desc
, sstate
->upgraded_depth_val
, 4 * 4);
411 memcpy(desc
, sstate
->val
, 4 * 4);
414 static void si_set_sampler_view_desc(struct si_context
*sctx
, struct si_sampler_view
*sview
,
415 struct si_sampler_state
*sstate
, uint32_t *desc
)
417 struct pipe_sampler_view
*view
= &sview
->base
;
418 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
419 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
421 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
422 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
423 if (!si_texture_disable_dcc(sctx
, tex
))
424 si_decompress_dcc(sctx
, tex
);
426 sview
->dcc_incompatible
= false;
429 assert(tex
); /* views with texture == NULL aren't supported */
430 memcpy(desc
, sview
->state
, 8 * 4);
433 si_set_buf_desc_address(&tex
->buffer
, sview
->base
.u
.buf
.offset
, desc
+ 4);
435 bool is_separate_stencil
= tex
->db_compatible
&& sview
->is_stencil_sampler
;
437 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
, sview
->base_level_info
, sview
->base_level
,
438 sview
->base
.u
.tex
.first_level
, sview
->block_width
,
439 is_separate_stencil
, desc
);
442 if (!is_buffer
&& tex
->surface
.fmask_size
) {
443 memcpy(desc
+ 8, sview
->fmask_state
, 8 * 4);
445 /* Disable FMASK and bind sampler state in [12:15]. */
446 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
449 si_set_sampler_state_desc(sstate
, sview
, is_buffer
? NULL
: tex
, desc
+ 12);
453 static bool color_needs_decompression(struct si_texture
*tex
)
455 return tex
->surface
.fmask_size
||
456 (tex
->dirty_level_mask
&& (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
459 static bool depth_needs_decompression(struct si_texture
*tex
)
461 /* If the depth/stencil texture is TC-compatible, no decompression
462 * will be done. The decompression function will only flush DB caches
463 * to make it coherent with shaders. That's necessary because the driver
464 * doesn't flush DB caches in any other case.
466 return tex
->db_compatible
;
469 static void si_set_sampler_view(struct si_context
*sctx
, unsigned shader
, unsigned slot
,
470 struct pipe_sampler_view
*view
, bool disallow_early_out
)
472 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
473 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
474 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
475 unsigned desc_slot
= si_get_sampler_slot(slot
);
476 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
478 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
482 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
484 si_set_sampler_view_desc(sctx
, sview
, samplers
->sampler_states
[slot
], desc
);
486 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
487 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
488 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
489 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
491 if (depth_needs_decompression(tex
)) {
492 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
494 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
496 if (color_needs_decompression(tex
)) {
497 samplers
->needs_color_decompress_mask
|= 1u << slot
;
499 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
502 if (tex
->surface
.dcc_offset
&& p_atomic_read(&tex
->framebuffers_bound
))
503 sctx
->need_check_render_feedback
= true;
506 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
507 samplers
->enabled_mask
|= 1u << slot
;
509 /* Since this can flush, it must be done after enabled_mask is
511 si_sampler_view_add_buffer(sctx
, view
->texture
, RADEON_USAGE_READ
, sview
->is_stencil_sampler
,
514 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
515 memcpy(desc
, null_texture_descriptor
, 8 * 4);
516 /* Only clear the lower dwords of FMASK. */
517 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
518 /* Re-set the sampler state if we are transitioning from FMASK. */
519 if (samplers
->sampler_states
[slot
])
520 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
, desc
+ 12);
522 samplers
->enabled_mask
&= ~(1u << slot
);
523 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
524 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
527 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
530 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
, unsigned shader
)
532 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
533 unsigned shader_bit
= 1 << shader
;
535 if (samplers
->needs_depth_decompress_mask
|| samplers
->needs_color_decompress_mask
||
536 sctx
->images
[shader
].needs_color_decompress_mask
)
537 sctx
->shader_needs_decompress_mask
|= shader_bit
;
539 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
542 static void si_set_sampler_views(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
543 unsigned start
, unsigned count
, struct pipe_sampler_view
**views
)
545 struct si_context
*sctx
= (struct si_context
*)ctx
;
548 if (!count
|| shader
>= SI_NUM_SHADERS
)
552 for (i
= 0; i
< count
; i
++)
553 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
555 for (i
= 0; i
< count
; i
++)
556 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
559 si_update_shader_needs_decompress_mask(sctx
, shader
);
562 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
564 unsigned mask
= samplers
->enabled_mask
;
567 int i
= u_bit_scan(&mask
);
568 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
570 if (res
&& res
->target
!= PIPE_BUFFER
) {
571 struct si_texture
*tex
= (struct si_texture
*)res
;
573 if (color_needs_decompression(tex
)) {
574 samplers
->needs_color_decompress_mask
|= 1u << i
;
576 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
584 static void si_release_image_views(struct si_images
*images
)
588 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
589 struct pipe_image_view
*view
= &images
->views
[i
];
591 pipe_resource_reference(&view
->resource
, NULL
);
595 static void si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
597 uint mask
= images
->enabled_mask
;
599 /* Add buffers to the CS. */
601 int i
= u_bit_scan(&mask
);
602 struct pipe_image_view
*view
= &images
->views
[i
];
604 assert(view
->resource
);
606 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
610 static void si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
612 struct si_images
*images
= &ctx
->images
[shader
];
614 if (images
->enabled_mask
& (1u << slot
)) {
615 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
616 unsigned desc_slot
= si_get_image_slot(slot
);
618 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
619 images
->needs_color_decompress_mask
&= ~(1 << slot
);
621 memcpy(descs
->list
+ desc_slot
* 8, null_image_descriptor
, 8 * 4);
622 images
->enabled_mask
&= ~(1u << slot
);
623 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
627 static void si_mark_image_range_valid(const struct pipe_image_view
*view
)
629 struct si_resource
*res
= si_resource(view
->resource
);
631 if (res
->b
.b
.target
!= PIPE_BUFFER
)
634 util_range_add(&res
->b
.b
, &res
->valid_buffer_range
, view
->u
.buf
.offset
,
635 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
638 static void si_set_shader_image_desc(struct si_context
*ctx
, const struct pipe_image_view
*view
,
639 bool skip_decompress
, uint32_t *desc
, uint32_t *fmask_desc
)
641 struct si_screen
*screen
= ctx
->screen
;
642 struct si_resource
*res
;
644 res
= si_resource(view
->resource
);
646 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
647 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
648 si_mark_image_range_valid(view
);
650 si_make_buffer_descriptor(screen
, res
, view
->format
, view
->u
.buf
.offset
, view
->u
.buf
.size
,
652 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
654 static const unsigned char swizzle
[4] = {0, 1, 2, 3};
655 struct si_texture
*tex
= (struct si_texture
*)res
;
656 unsigned level
= view
->u
.tex
.level
;
657 unsigned width
, height
, depth
, hw_level
;
658 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
659 unsigned access
= view
->access
;
661 assert(!tex
->is_depth
);
662 assert(fmask_desc
|| tex
->surface
.fmask_offset
== 0);
664 if (uses_dcc
&& !skip_decompress
&&
665 (access
& PIPE_IMAGE_ACCESS_WRITE
||
666 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
667 /* If DCC can't be disabled, at least decompress it.
668 * The decompression is relatively cheap if the surface
669 * has been decompressed already.
671 if (!si_texture_disable_dcc(ctx
, tex
))
672 si_decompress_dcc(ctx
, tex
);
675 if (ctx
->chip_class
>= GFX9
) {
676 /* Always set the base address. The swizzle modes don't
677 * allow setting mipmap level offsets as the base.
679 width
= res
->b
.b
.width0
;
680 height
= res
->b
.b
.height0
;
681 depth
= res
->b
.b
.depth0
;
684 /* Always force the base level to the selected level.
686 * This is required for 3D textures, where otherwise
687 * selecting a single slice for non-layered bindings
688 * fails. It doesn't hurt the other targets.
690 width
= u_minify(res
->b
.b
.width0
, level
);
691 height
= u_minify(res
->b
.b
.height0
, level
);
692 depth
= u_minify(res
->b
.b
.depth0
, level
);
696 screen
->make_texture_descriptor(
697 screen
, tex
, false, res
->b
.b
.target
, view
->format
, swizzle
, hw_level
, hw_level
,
698 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
, width
, height
, depth
, desc
, fmask_desc
);
699 si_set_mutable_tex_desc_fields(screen
, tex
, &tex
->surface
.u
.legacy
.level
[level
], level
, level
,
700 util_format_get_blockwidth(view
->format
), false, desc
);
704 static void si_set_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
,
705 const struct pipe_image_view
*view
, bool skip_decompress
)
707 struct si_images
*images
= &ctx
->images
[shader
];
708 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
709 struct si_resource
*res
;
711 if (!view
|| !view
->resource
) {
712 si_disable_shader_image(ctx
, shader
, slot
);
716 res
= si_resource(view
->resource
);
718 if (&images
->views
[slot
] != view
)
719 util_copy_image_view(&images
->views
[slot
], view
);
721 si_set_shader_image_desc(ctx
, view
, skip_decompress
, descs
->list
+ si_get_image_slot(slot
) * 8,
722 descs
->list
+ si_get_image_slot(slot
+ SI_NUM_IMAGES
) * 8);
724 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
725 images
->needs_color_decompress_mask
&= ~(1 << slot
);
726 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
728 struct si_texture
*tex
= (struct si_texture
*)res
;
729 unsigned level
= view
->u
.tex
.level
;
731 if (color_needs_decompression(tex
)) {
732 images
->needs_color_decompress_mask
|= 1 << slot
;
734 images
->needs_color_decompress_mask
&= ~(1 << slot
);
737 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
738 ctx
->need_check_render_feedback
= true;
741 images
->enabled_mask
|= 1u << slot
;
742 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
744 /* Since this can flush, it must be done after enabled_mask is updated. */
745 si_sampler_view_add_buffer(
747 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
751 static void si_set_shader_images(struct pipe_context
*pipe
, enum pipe_shader_type shader
,
752 unsigned start_slot
, unsigned count
,
753 const struct pipe_image_view
*views
)
755 struct si_context
*ctx
= (struct si_context
*)pipe
;
758 assert(shader
< SI_NUM_SHADERS
);
763 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
766 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
767 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
769 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
770 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
773 si_update_shader_needs_decompress_mask(ctx
, shader
);
776 static void si_images_update_needs_color_decompress_mask(struct si_images
*images
)
778 unsigned mask
= images
->enabled_mask
;
781 int i
= u_bit_scan(&mask
);
782 struct pipe_resource
*res
= images
->views
[i
].resource
;
784 if (res
&& res
->target
!= PIPE_BUFFER
) {
785 struct si_texture
*tex
= (struct si_texture
*)res
;
787 if (color_needs_decompression(tex
)) {
788 images
->needs_color_decompress_mask
|= 1 << i
;
790 images
->needs_color_decompress_mask
&= ~(1 << i
);
796 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
798 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
799 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
800 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
801 struct pipe_surface
*surf
= NULL
;
803 /* si_texture_disable_dcc can get us here again. */
804 if (sctx
->blitter
->running
)
807 /* See whether FBFETCH is used and color buffer 0 is set. */
808 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
809 sctx
->framebuffer
.state
.nr_cbufs
&& sctx
->framebuffer
.state
.cbufs
[0])
810 surf
= sctx
->framebuffer
.state
.cbufs
[0];
812 /* Return if FBFETCH transitions from disabled to disabled. */
813 if (!buffers
->buffers
[slot
] && !surf
)
816 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
817 si_update_ps_iter_samples(sctx
);
820 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
821 struct pipe_image_view view
= {0};
824 assert(!tex
->is_depth
);
826 /* Disable DCC, because the texture is used as both a sampler
829 si_texture_disable_dcc(sctx
, tex
);
831 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
833 assert(tex
->cmask_buffer
!= &tex
->buffer
);
834 si_eliminate_fast_color_clear(sctx
, tex
);
835 si_texture_discard_cmask(sctx
->screen
, tex
);
838 view
.resource
= surf
->texture
;
839 view
.format
= surf
->format
;
840 view
.access
= PIPE_IMAGE_ACCESS_READ
;
841 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
842 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
843 view
.u
.tex
.level
= surf
->u
.tex
.level
;
845 /* Set the descriptor. */
846 uint32_t *desc
= descs
->list
+ slot
* 4;
847 memset(desc
, 0, 16 * 4);
848 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
850 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
851 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READ
,
852 RADEON_PRIO_SHADER_RW_IMAGE
);
853 buffers
->enabled_mask
|= 1u << slot
;
855 /* Clear the descriptor. */
856 memset(descs
->list
+ slot
* 4, 0, 8 * 4);
857 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
858 buffers
->enabled_mask
&= ~(1u << slot
);
861 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
866 static void si_bind_sampler_states(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
867 unsigned start
, unsigned count
, void **states
)
869 struct si_context
*sctx
= (struct si_context
*)ctx
;
870 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
871 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
872 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
875 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
878 for (i
= 0; i
< count
; i
++) {
879 unsigned slot
= start
+ i
;
880 unsigned desc_slot
= si_get_sampler_slot(slot
);
882 if (!sstates
[i
] || sstates
[i
] == samplers
->sampler_states
[slot
])
886 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
888 samplers
->sampler_states
[slot
] = sstates
[i
];
890 /* If FMASK is bound, don't overwrite it.
891 * The sampler state will be set after FMASK is unbound.
893 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[slot
];
895 struct si_texture
*tex
= NULL
;
897 if (sview
&& sview
->base
.texture
&& sview
->base
.texture
->target
!= PIPE_BUFFER
)
898 tex
= (struct si_texture
*)sview
->base
.texture
;
900 if (tex
&& tex
->surface
.fmask_size
)
903 si_set_sampler_state_desc(sstates
[i
], sview
, tex
, desc
->list
+ desc_slot
* 16 + 12);
905 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
909 /* BUFFER RESOURCES */
911 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
912 struct si_descriptors
*descs
, unsigned num_buffers
,
913 short shader_userdata_rel_index
,
914 enum radeon_bo_priority priority
,
915 enum radeon_bo_priority priority_constbuf
)
917 buffers
->priority
= priority
;
918 buffers
->priority_constbuf
= priority_constbuf
;
919 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
920 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
922 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
925 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
926 struct si_descriptors
*descs
)
930 for (i
= 0; i
< descs
->num_elements
; i
++) {
931 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
934 FREE(buffers
->buffers
);
935 FREE(buffers
->offsets
);
938 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
939 struct si_buffer_resources
*buffers
)
941 unsigned mask
= buffers
->enabled_mask
;
943 /* Add buffers to the CS. */
945 int i
= u_bit_scan(&mask
);
947 radeon_add_to_buffer_list(
948 sctx
, sctx
->gfx_cs
, si_resource(buffers
->buffers
[i
]),
949 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
950 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
: buffers
->priority_constbuf
);
954 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
955 struct si_descriptors
*descs
, unsigned idx
,
956 struct pipe_resource
**buf
, unsigned *offset
,
959 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
961 struct si_resource
*res
= si_resource(*buf
);
962 const uint32_t *desc
= descs
->list
+ idx
* 4;
967 assert(G_008F04_STRIDE(desc
[1]) == 0);
968 va
= si_desc_extract_buffer_address(desc
);
970 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
971 *offset
= va
- res
->gpu_address
;
977 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
979 int count
= sctx
->num_vertex_elements
;
982 for (i
= 0; i
< count
; i
++) {
983 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
985 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
987 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
990 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
991 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
992 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
995 if (!sctx
->vb_descriptors_buffer
)
997 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
998 RADEON_PRIO_DESCRIPTORS
);
1001 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1003 unsigned i
, count
= sctx
->num_vertex_elements
;
1006 if (!sctx
->vertex_buffers_dirty
|| !count
)
1009 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1010 unsigned alloc_size
= velems
->vb_desc_list_alloc_size
;
1013 /* Vertex buffer descriptors are the only ones which are uploaded
1014 * directly through a staging buffer and don't go through
1015 * the fine-grained upload path.
1017 u_upload_alloc(sctx
->b
.const_uploader
, 0, alloc_size
,
1018 si_optimal_tcc_alignment(sctx
, alloc_size
), &sctx
->vb_descriptors_offset
,
1019 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
, (void **)&ptr
);
1020 if (!sctx
->vb_descriptors_buffer
) {
1021 sctx
->vb_descriptors_offset
= 0;
1022 sctx
->vb_descriptors_gpu_list
= NULL
;
1026 sctx
->vb_descriptors_gpu_list
= ptr
;
1027 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1028 RADEON_PRIO_DESCRIPTORS
);
1029 sctx
->vertex_buffer_pointer_dirty
= true;
1030 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1032 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
1033 sctx
->vertex_buffer_pointer_dirty
= false;
1034 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VBO_DESCRIPTORS
;
1037 assert(count
<= SI_MAX_ATTRIBS
);
1039 unsigned first_vb_use_mask
= velems
->first_vb_use_mask
;
1040 unsigned num_vbos_in_user_sgprs
= sctx
->screen
->num_vbos_in_user_sgprs
;
1042 for (i
= 0; i
< count
; i
++) {
1043 struct pipe_vertex_buffer
*vb
;
1044 struct si_resource
*buf
;
1045 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1046 uint32_t *desc
= i
< num_vbos_in_user_sgprs
? &sctx
->vb_descriptor_user_sgprs
[i
* 4]
1047 : &ptr
[(i
- num_vbos_in_user_sgprs
) * 4];
1049 vb
= &sctx
->vertex_buffer
[vbo_index
];
1050 buf
= si_resource(vb
->buffer
.resource
);
1052 memset(desc
, 0, 16);
1056 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) + velems
->src_offset
[i
];
1058 if (offset
>= buf
->b
.b
.width0
) {
1059 assert(offset
< buf
->b
.b
.width0
);
1060 memset(desc
, 0, 16);
1064 uint64_t va
= buf
->gpu_address
+ offset
;
1066 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1067 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1068 /* Round up by rounding down and adding 1 */
1069 num_records
= (num_records
- velems
->format_size
[i
]) / vb
->stride
+ 1;
1071 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1073 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1075 /* OOB_SELECT chooses the out-of-bounds check:
1076 * - 1: index >= NUM_RECORDS (Structured)
1077 * - 3: offset >= NUM_RECORDS (Raw)
1079 if (sctx
->chip_class
>= GFX10
)
1080 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? V_008F0C_OOB_SELECT_STRUCTURED
1081 : V_008F0C_OOB_SELECT_RAW
);
1084 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(vb
->stride
);
1085 desc
[2] = num_records
;
1086 desc
[3] = rsrc_word3
;
1088 if (first_vb_use_mask
& (1 << i
)) {
1089 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(vb
->buffer
.resource
),
1090 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1094 /* Don't flush the const cache. It would have a very negative effect
1095 * on performance (confirmed by testing). New descriptors are always
1096 * uploaded to a fresh new buffer, so I don't think flushing the const
1097 * cache is needed. */
1098 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1099 sctx
->vertex_buffer_user_sgprs_dirty
= num_vbos_in_user_sgprs
> 0;
1100 sctx
->vertex_buffers_dirty
= false;
1104 /* CONSTANT BUFFERS */
1106 static struct si_descriptors
*si_const_and_shader_buffer_descriptors(struct si_context
*sctx
,
1109 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1112 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
, const uint8_t *ptr
,
1113 unsigned size
, uint32_t *const_offset
)
1117 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
, si_optimal_tcc_alignment(sctx
, size
),
1118 const_offset
, (struct pipe_resource
**)buf
, &tmp
);
1120 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1123 static void si_set_constant_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1124 unsigned descriptors_idx
, uint slot
,
1125 const struct pipe_constant_buffer
*input
)
1127 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1128 assert(slot
< descs
->num_elements
);
1129 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1131 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1132 * with a NULL buffer). We need to use a dummy buffer instead. */
1133 if (sctx
->chip_class
== GFX7
&& (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1134 input
= &sctx
->null_const_buf
;
1136 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1137 struct pipe_resource
*buffer
= NULL
;
1139 unsigned buffer_offset
;
1141 /* Upload the user buffer if needed. */
1142 if (input
->user_buffer
) {
1143 si_upload_const_buffer(sctx
, (struct si_resource
**)&buffer
, input
->user_buffer
,
1144 input
->buffer_size
, &buffer_offset
);
1146 /* Just unbind on failure. */
1147 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1151 pipe_resource_reference(&buffer
, input
->buffer
);
1152 buffer_offset
= input
->buffer_offset
;
1155 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1157 /* Set the descriptor. */
1158 uint32_t *desc
= descs
->list
+ slot
* 4;
1160 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1161 desc
[2] = input
->buffer_size
;
1162 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1165 if (sctx
->chip_class
>= GFX10
) {
1166 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1167 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1169 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1170 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1173 buffers
->buffers
[slot
] = buffer
;
1174 buffers
->offsets
[slot
] = buffer_offset
;
1175 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1176 buffers
->priority_constbuf
, true);
1177 buffers
->enabled_mask
|= 1u << slot
;
1179 /* Clear the descriptor. */
1180 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1181 buffers
->enabled_mask
&= ~(1u << slot
);
1184 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1187 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1188 uint slot
, const struct pipe_constant_buffer
*input
)
1190 struct si_context
*sctx
= (struct si_context
*)ctx
;
1192 if (shader
>= SI_NUM_SHADERS
)
1195 if (slot
== 0 && input
&& input
->buffer
&&
1196 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1197 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1201 if (input
&& input
->buffer
)
1202 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1204 slot
= si_get_constbuf_slot(slot
);
1205 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1206 si_const_and_shader_buffer_descriptors_idx(shader
), slot
, input
);
1209 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
, uint slot
,
1210 struct pipe_constant_buffer
*cbuf
)
1212 cbuf
->user_buffer
= NULL
;
1213 si_get_buffer_from_descriptors(
1214 &sctx
->const_and_shader_buffers
[shader
], si_const_and_shader_buffer_descriptors(sctx
, shader
),
1215 si_get_constbuf_slot(slot
), &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1218 /* SHADER BUFFERS */
1220 static void si_set_shader_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1221 unsigned descriptors_idx
, uint slot
,
1222 const struct pipe_shader_buffer
*sbuffer
, bool writable
,
1223 enum radeon_bo_priority priority
)
1225 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1226 uint32_t *desc
= descs
->list
+ slot
* 4;
1228 if (!sbuffer
|| !sbuffer
->buffer
) {
1229 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1230 memset(desc
, 0, sizeof(uint32_t) * 4);
1231 buffers
->enabled_mask
&= ~(1u << slot
);
1232 buffers
->writable_mask
&= ~(1u << slot
);
1233 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1237 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1238 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1241 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1242 desc
[2] = sbuffer
->buffer_size
;
1243 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1246 if (sctx
->chip_class
>= GFX10
) {
1247 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1248 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1250 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1251 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1254 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1255 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1256 radeon_add_to_gfx_buffer_list_check_mem(
1257 sctx
, buf
, writable
? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, priority
, true);
1259 buffers
->writable_mask
|= 1u << slot
;
1261 buffers
->writable_mask
&= ~(1u << slot
);
1263 buffers
->enabled_mask
|= 1u << slot
;
1264 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1266 util_range_add(&buf
->b
.b
, &buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1267 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1270 static void si_set_shader_buffers(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1271 unsigned start_slot
, unsigned count
,
1272 const struct pipe_shader_buffer
*sbuffers
,
1273 unsigned writable_bitmask
)
1275 struct si_context
*sctx
= (struct si_context
*)ctx
;
1276 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1277 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1280 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1282 for (i
= 0; i
< count
; ++i
) {
1283 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1284 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1286 if (sbuffer
&& sbuffer
->buffer
)
1287 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1289 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1290 !!(writable_bitmask
& (1u << i
)), buffers
->priority
);
1294 void si_get_shader_buffers(struct si_context
*sctx
, enum pipe_shader_type shader
, uint start_slot
,
1295 uint count
, struct pipe_shader_buffer
*sbuf
)
1297 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1298 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1300 for (unsigned i
= 0; i
< count
; ++i
) {
1301 si_get_buffer_from_descriptors(buffers
, descs
, si_get_shaderbuf_slot(start_slot
+ i
),
1302 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
, &sbuf
[i
].buffer_size
);
1308 void si_set_rw_buffer(struct si_context
*sctx
, uint slot
, const struct pipe_constant_buffer
*input
)
1310 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, input
);
1313 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1314 const struct pipe_shader_buffer
*sbuffer
)
1316 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, sbuffer
, true,
1317 RADEON_PRIO_SHADER_RW_BUFFER
);
1320 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
, struct pipe_resource
*buffer
,
1321 unsigned stride
, unsigned num_records
, bool add_tid
, bool swizzle
,
1322 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1324 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1325 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1327 /* The stride field in the resource descriptor has 14 bits */
1328 assert(stride
< (1 << 14));
1330 assert(slot
< descs
->num_elements
);
1331 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1336 va
= si_resource(buffer
)->gpu_address
+ offset
;
1338 switch (element_size
) {
1340 assert(!"Unsupported ring buffer element size");
1356 switch (index_stride
) {
1358 assert(!"Unsupported ring buffer index stride");
1374 if (sctx
->chip_class
>= GFX8
&& stride
)
1375 num_records
*= stride
;
1377 /* Set the descriptor. */
1378 uint32_t *desc
= descs
->list
+ slot
* 4;
1380 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
) |
1381 S_008F04_SWIZZLE_ENABLE(swizzle
);
1382 desc
[2] = num_records
;
1383 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1384 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1385 S_008F0C_INDEX_STRIDE(index_stride
) | S_008F0C_ADD_TID_ENABLE(add_tid
);
1387 if (sctx
->chip_class
>= GFX9
)
1388 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1390 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1392 if (sctx
->chip_class
>= GFX10
) {
1393 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1394 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) | S_008F0C_RESOURCE_LEVEL(1);
1396 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1397 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1400 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1401 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(buffer
), RADEON_USAGE_READWRITE
,
1403 buffers
->enabled_mask
|= 1u << slot
;
1405 /* Clear the descriptor. */
1406 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1407 buffers
->enabled_mask
&= ~(1u << slot
);
1410 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1413 /* INTERNAL CONST BUFFERS */
1415 static void si_set_polygon_stipple(struct pipe_context
*ctx
, const struct pipe_poly_stipple
*state
)
1417 struct si_context
*sctx
= (struct si_context
*)ctx
;
1418 struct pipe_constant_buffer cb
= {};
1419 unsigned stipple
[32];
1422 for (i
= 0; i
< 32; i
++)
1423 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1425 cb
.user_buffer
= stipple
;
1426 cb
.buffer_size
= sizeof(stipple
);
1428 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1431 /* TEXTURE METADATA ENABLE/DISABLE */
1433 static void si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1435 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1436 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1438 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1439 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1440 struct si_texture
*tex
;
1442 if (!res
|| res
->target
== PIPE_BUFFER
)
1445 tex
= (struct si_texture
*)res
;
1446 if (!color_needs_decompression(tex
))
1449 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
, struct si_texture_handle
*,
1453 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1454 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1455 struct pipe_resource
*res
= view
->resource
;
1456 struct si_texture
*tex
;
1458 if (!res
|| res
->target
== PIPE_BUFFER
)
1461 tex
= (struct si_texture
*)res
;
1462 if (!color_needs_decompression(tex
))
1465 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
, struct si_image_handle
*,
1470 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1471 * while the texture is bound, possibly by a different context. In that case,
1472 * call this function to update needs_*_decompress_masks.
1474 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1476 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1477 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1478 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1479 si_update_shader_needs_decompress_mask(sctx
, i
);
1482 si_resident_handles_update_needs_color_decompress(sctx
);
1485 /* BUFFER DISCARD/INVALIDATION */
1487 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1488 * If buf == NULL, reset all descriptors.
1490 static void si_reset_buffer_resources(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1491 unsigned descriptors_idx
, unsigned slot_mask
,
1492 struct pipe_resource
*buf
, enum radeon_bo_priority priority
)
1494 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1495 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1498 unsigned i
= u_bit_scan(&mask
);
1499 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1501 if (buffer
&& (!buf
|| buffer
== buf
)) {
1502 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1503 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1505 radeon_add_to_gfx_buffer_list_check_mem(
1506 sctx
, si_resource(buffer
),
1507 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
1513 /* Update all buffer bindings where the buffer is bound, including
1514 * all resource descriptors. This is invalidate_buffer without
1517 * If buf == NULL, update all buffer bindings.
1519 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1521 struct si_resource
*buffer
= si_resource(buf
);
1523 unsigned num_elems
= sctx
->num_vertex_elements
;
1525 /* We changed the buffer, now we need to bind it where the old one
1526 * was bound. This consists of 2 things:
1527 * 1) Updating the resource descriptor and dirtying it.
1528 * 2) Adding a relocation to the CS, so that it's usable.
1531 /* Vertex buffers. */
1534 sctx
->vertex_buffers_dirty
= true;
1535 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1536 for (i
= 0; i
< num_elems
; i
++) {
1537 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1539 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1541 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1544 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1545 sctx
->vertex_buffers_dirty
= true;
1551 /* Streamout buffers. (other internal buffers can't be invalidated) */
1552 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1553 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1554 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1555 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1556 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1558 if (!buffer
|| (buf
&& buffer
!= buf
))
1561 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1562 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1564 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_WRITE
,
1565 RADEON_PRIO_SHADER_RW_BUFFER
, true);
1567 /* Update the streamout state. */
1568 if (sctx
->streamout
.begin_emitted
)
1569 si_emit_streamout_end(sctx
);
1570 sctx
->streamout
.append_bitmask
= sctx
->streamout
.enabled_mask
;
1571 si_streamout_buffers_dirty(sctx
);
1575 /* Constant and shader buffers. */
1576 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1577 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1578 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1579 si_const_and_shader_buffer_descriptors_idx(shader
),
1580 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1581 buf
, sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1584 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1585 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1586 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1587 si_const_and_shader_buffer_descriptors_idx(shader
),
1588 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
), buf
,
1589 sctx
->const_and_shader_buffers
[shader
].priority
);
1592 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1593 /* Texture buffers - update bindings. */
1594 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1595 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1596 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1597 unsigned mask
= samplers
->enabled_mask
;
1600 unsigned i
= u_bit_scan(&mask
);
1601 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1603 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1604 unsigned desc_slot
= si_get_sampler_slot(i
);
1606 si_set_buf_desc_address(si_resource(buffer
), samplers
->views
[i
]->u
.buf
.offset
,
1607 descs
->list
+ desc_slot
* 16 + 4);
1608 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1610 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1611 RADEON_PRIO_SAMPLER_BUFFER
, true);
1618 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1619 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1620 struct si_images
*images
= &sctx
->images
[shader
];
1621 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1622 unsigned mask
= images
->enabled_mask
;
1625 unsigned i
= u_bit_scan(&mask
);
1626 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1628 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1629 unsigned desc_slot
= si_get_image_slot(i
);
1631 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1632 si_mark_image_range_valid(&images
->views
[i
]);
1634 si_set_buf_desc_address(si_resource(buffer
), images
->views
[i
].u
.buf
.offset
,
1635 descs
->list
+ desc_slot
* 8 + 4);
1636 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1638 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
),
1639 RADEON_USAGE_READWRITE
,
1640 RADEON_PRIO_SAMPLER_BUFFER
, true);
1646 /* Bindless texture handles */
1647 if (!buffer
|| buffer
->texture_handle_allocated
) {
1648 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1650 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1651 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1652 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1653 struct pipe_resource
*buffer
= view
->texture
;
1655 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1656 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1657 descs
->list
+ desc_slot
* 16 + 4);
1659 (*tex_handle
)->desc_dirty
= true;
1660 sctx
->bindless_descriptors_dirty
= true;
1662 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1663 RADEON_PRIO_SAMPLER_BUFFER
, true);
1668 /* Bindless image handles */
1669 if (!buffer
|| buffer
->image_handle_allocated
) {
1670 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1672 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1673 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1674 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1675 struct pipe_resource
*buffer
= view
->resource
;
1677 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1678 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1679 si_mark_image_range_valid(view
);
1681 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1682 descs
->list
+ desc_slot
* 16 + 4);
1684 (*img_handle
)->desc_dirty
= true;
1685 sctx
->bindless_descriptors_dirty
= true;
1687 radeon_add_to_gfx_buffer_list_check_mem(
1688 sctx
, si_resource(buffer
), RADEON_USAGE_READWRITE
, RADEON_PRIO_SAMPLER_BUFFER
, true);
1694 /* Do the same for other contexts. They will invoke this function
1695 * with buffer == NULL.
1697 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1699 /* Skip the update for the current context, because we have already updated
1700 * the buffer bindings.
1702 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1703 sctx
->last_dirty_buf_counter
= new_counter
;
1707 static void si_upload_bindless_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
1708 unsigned num_dwords
)
1710 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1711 unsigned desc_slot_offset
= desc_slot
* 16;
1715 data
= desc
->list
+ desc_slot_offset
;
1716 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1718 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
, num_dwords
* 4, V_370_TC_L2
,
1722 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1724 if (!sctx
->bindless_descriptors_dirty
)
1727 /* Wait for graphics/compute to be idle before updating the resident
1728 * descriptors directly in memory, in case the GPU is using them.
1730 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
1731 sctx
->emit_cache_flush(sctx
);
1733 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1734 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1736 if (!(*tex_handle
)->desc_dirty
)
1739 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1740 (*tex_handle
)->desc_dirty
= false;
1743 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1744 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1746 if (!(*img_handle
)->desc_dirty
)
1749 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1750 (*img_handle
)->desc_dirty
= false;
1753 /* Invalidate L1 because it doesn't know that L2 changed. */
1754 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1755 sctx
->emit_cache_flush(sctx
);
1757 sctx
->bindless_descriptors_dirty
= false;
1760 /* Update mutable image descriptor fields of all resident textures. */
1761 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1762 struct si_texture_handle
*tex_handle
)
1764 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1765 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1766 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1767 uint32_t desc_list
[16];
1769 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1772 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1773 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
, desc
->list
+ desc_slot_offset
);
1775 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
))) {
1776 tex_handle
->desc_dirty
= true;
1777 sctx
->bindless_descriptors_dirty
= true;
1781 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1782 struct si_image_handle
*img_handle
)
1784 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1785 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1786 struct pipe_image_view
*view
= &img_handle
->view
;
1787 struct pipe_resource
*res
= view
->resource
;
1788 uint32_t image_desc
[16];
1789 unsigned desc_size
= (res
->nr_samples
>= 2 ? 16 : 8) * 4;
1791 if (res
->target
== PIPE_BUFFER
)
1794 memcpy(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
);
1795 si_set_shader_image_desc(sctx
, view
, true, desc
->list
+ desc_slot_offset
,
1796 desc
->list
+ desc_slot_offset
+ 8);
1798 if (memcmp(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
)) {
1799 img_handle
->desc_dirty
= true;
1800 sctx
->bindless_descriptors_dirty
= true;
1804 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1806 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1807 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1810 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1811 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1814 si_upload_bindless_descriptors(sctx
);
1817 /* Update mutable image descriptor fields of all bound textures. */
1818 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1822 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1823 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1824 struct si_images
*images
= &sctx
->images
[shader
];
1828 mask
= images
->enabled_mask
;
1830 unsigned i
= u_bit_scan(&mask
);
1831 struct pipe_image_view
*view
= &images
->views
[i
];
1833 if (!view
->resource
|| view
->resource
->target
== PIPE_BUFFER
)
1836 si_set_shader_image(sctx
, shader
, i
, view
, true);
1839 /* Sampler views. */
1840 mask
= samplers
->enabled_mask
;
1842 unsigned i
= u_bit_scan(&mask
);
1843 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1845 if (!view
|| !view
->texture
|| view
->texture
->target
== PIPE_BUFFER
)
1848 si_set_sampler_view(sctx
, shader
, i
, samplers
->views
[i
], true);
1851 si_update_shader_needs_decompress_mask(sctx
, shader
);
1854 si_update_all_resident_texture_descriptors(sctx
);
1855 si_update_ps_colorbuf0_slot(sctx
);
1858 /* SHADER USER DATA */
1860 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
, unsigned shader
)
1862 sctx
->shader_pointers_dirty
|=
1863 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
, SI_NUM_SHADER_DESCS
);
1865 if (shader
== PIPE_SHADER_VERTEX
) {
1866 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1867 sctx
->vertex_buffer_user_sgprs_dirty
=
1868 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1871 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1874 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1876 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1877 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1878 sctx
->vertex_buffer_user_sgprs_dirty
=
1879 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1880 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1881 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1882 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1885 /* Set a base register address for user data constants in the given shader.
1886 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1888 static void si_set_user_data_base(struct si_context
*sctx
, unsigned shader
, uint32_t new_base
)
1890 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1892 if (*base
!= new_base
) {
1896 si_mark_shader_pointers_dirty(sctx
, shader
);
1898 /* Any change in enabled shader stages requires re-emitting
1899 * the VS state SGPR, because it contains the clamp_vertex_color
1900 * state, which can be done in VS, TES, and GS.
1902 sctx
->last_vs_state
= ~0;
1906 /* This must be called when these are changed between enabled and disabled
1908 * - tessellation evaluation shader
1911 void si_shader_change_notify(struct si_context
*sctx
)
1913 /* VS can be bound as VS, ES, or LS. */
1914 if (sctx
->tes_shader
.cso
) {
1915 if (sctx
->chip_class
>= GFX10
) {
1916 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1917 } else if (sctx
->chip_class
== GFX9
) {
1918 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1920 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1922 } else if (sctx
->chip_class
>= GFX10
) {
1923 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1924 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1926 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1928 } else if (sctx
->gs_shader
.cso
) {
1929 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1931 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1934 /* TES can be bound as ES, VS, or not bound. */
1935 if (sctx
->tes_shader
.cso
) {
1936 if (sctx
->chip_class
>= GFX10
) {
1937 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1938 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1940 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1942 } else if (sctx
->gs_shader
.cso
) {
1943 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1945 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1948 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1952 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
, unsigned sh_offset
,
1953 unsigned pointer_count
)
1955 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
1956 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1959 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
, struct radeon_cmdbuf
*cs
,
1962 radeon_emit(cs
, va
);
1964 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
1967 static void si_emit_shader_pointer(struct si_context
*sctx
, struct si_descriptors
*desc
,
1970 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1971 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
1973 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
1974 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
1977 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
, unsigned pointer_mask
,
1983 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1984 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
1988 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
1990 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
1991 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
1993 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
1994 for (int i
= 0; i
< count
; i
++)
1995 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
[i
].gpu_address
);
1999 static void si_emit_global_shader_pointers(struct si_context
*sctx
, struct si_descriptors
*descs
)
2001 if (sctx
->chip_class
>= GFX10
) {
2002 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2003 /* HW VS stage only used in non-NGG mode. */
2004 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2005 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2006 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2008 } else if (sctx
->chip_class
== GFX9
) {
2009 /* Broadcast it to all shader stages. */
2010 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2014 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2015 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2016 si_emit_shader_pointer(sctx
, descs
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2017 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2018 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2019 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2022 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2024 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2026 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2027 si_emit_global_shader_pointers(sctx
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2030 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2031 sh_base
[PIPE_SHADER_VERTEX
]);
2032 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2033 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2034 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2035 sh_base
[PIPE_SHADER_FRAGMENT
]);
2036 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2037 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2038 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2039 sh_base
[PIPE_SHADER_GEOMETRY
]);
2041 sctx
->shader_pointers_dirty
&= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2043 if (sctx
->vertex_buffer_pointer_dirty
&& sctx
->num_vertex_elements
) {
2044 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2046 /* Find the location of the VB descriptor pointer. */
2047 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2048 if (sctx
->chip_class
>= GFX9
) {
2049 if (sctx
->tes_shader
.cso
)
2050 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2051 else if (sctx
->gs_shader
.cso
)
2052 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2055 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2056 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2057 si_emit_shader_pointer_body(
2058 sctx
->screen
, cs
, sctx
->vb_descriptors_buffer
->gpu_address
+ sctx
->vb_descriptors_offset
);
2059 sctx
->vertex_buffer_pointer_dirty
= false;
2062 if (sctx
->vertex_buffer_user_sgprs_dirty
&& sctx
->num_vertex_elements
&&
2063 sctx
->screen
->num_vbos_in_user_sgprs
) {
2064 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2065 unsigned num_desc
= MIN2(sctx
->num_vertex_elements
, sctx
->screen
->num_vbos_in_user_sgprs
);
2066 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST
* 4;
2068 si_emit_shader_pointer_head(cs
, sh_offset
, num_desc
* 4);
2069 radeon_emit_array(cs
, sctx
->vb_descriptor_user_sgprs
, num_desc
* 4);
2070 sctx
->vertex_buffer_user_sgprs_dirty
= false;
2073 if (sctx
->graphics_bindless_pointer_dirty
) {
2074 si_emit_global_shader_pointers(sctx
, &sctx
->bindless_descriptors
);
2075 sctx
->graphics_bindless_pointer_dirty
= false;
2079 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2081 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2083 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2084 R_00B900_COMPUTE_USER_DATA_0
);
2085 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2087 if (sctx
->compute_bindless_pointer_dirty
) {
2088 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2089 sctx
->compute_bindless_pointer_dirty
= false;
2095 static void si_init_bindless_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
,
2096 short shader_userdata_rel_index
, unsigned num_elements
)
2098 ASSERTED
unsigned desc_slot
;
2100 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2101 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2103 /* The first bindless descriptor is stored at slot 1, because 0 is not
2104 * considered to be a valid handle.
2106 sctx
->num_bindless_descriptors
= 1;
2108 /* Track which bindless slots are used (or not). */
2109 util_idalloc_init(&sctx
->bindless_used_slots
);
2110 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2112 /* Reserve slot 0 because it's an invalid handle for bindless. */
2113 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2114 assert(desc_slot
== 0);
2117 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2119 si_release_descriptors(&sctx
->bindless_descriptors
);
2120 util_idalloc_fini(&sctx
->bindless_used_slots
);
2123 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2125 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2128 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2129 if (desc_slot
>= desc
->num_elements
) {
2130 /* The array of bindless descriptors is full, resize it. */
2131 unsigned slot_size
= desc
->element_dw_size
* 4;
2132 unsigned new_num_elements
= desc
->num_elements
* 2;
2135 REALLOC(desc
->list
, desc
->num_elements
* slot_size
, new_num_elements
* slot_size
);
2136 desc
->num_elements
= new_num_elements
;
2137 desc
->num_active_slots
= new_num_elements
;
2144 static unsigned si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2147 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2148 unsigned desc_slot
, desc_slot_offset
;
2150 /* Find a free slot. */
2151 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2153 /* For simplicity, sampler and image bindless descriptors use fixed
2154 * 16-dword slots for now. Image descriptors only need 8-dword but this
2155 * doesn't really matter because no real apps use image handles.
2157 desc_slot_offset
= desc_slot
* 16;
2159 /* Copy the descriptor into the array. */
2160 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2162 /* Re-upload the whole array of bindless descriptors into a new buffer.
2164 if (!si_upload_descriptors(sctx
, desc
))
2167 /* Make sure to re-emit the shader pointers for all stages. */
2168 sctx
->graphics_bindless_pointer_dirty
= true;
2169 sctx
->compute_bindless_pointer_dirty
= true;
2174 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
2175 struct pipe_resource
*resource
, uint64_t offset
,
2178 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2179 struct si_resource
*buf
= si_resource(resource
);
2180 unsigned desc_slot_offset
= desc_slot
* 16;
2181 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2182 uint64_t old_desc_va
;
2184 assert(resource
->target
== PIPE_BUFFER
);
2186 /* Retrieve the old buffer addr from the descriptor. */
2187 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2189 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2190 /* The buffer has been invalidated when the handle wasn't
2191 * resident, update the descriptor and the dirty flag.
2193 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2199 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
, struct pipe_sampler_view
*view
,
2200 const struct pipe_sampler_state
*state
)
2202 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2203 struct si_context
*sctx
= (struct si_context
*)ctx
;
2204 struct si_texture_handle
*tex_handle
;
2205 struct si_sampler_state
*sstate
;
2206 uint32_t desc_list
[16];
2209 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2213 memset(desc_list
, 0, sizeof(desc_list
));
2214 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2216 sstate
= ctx
->create_sampler_state(ctx
, state
);
2222 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2223 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2224 ctx
->delete_sampler_state(ctx
, sstate
);
2226 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2227 if (!tex_handle
->desc_slot
) {
2232 handle
= tex_handle
->desc_slot
;
2234 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)(uintptr_t)handle
, tex_handle
)) {
2239 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2241 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2246 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2248 struct si_context
*sctx
= (struct si_context
*)ctx
;
2249 struct si_texture_handle
*tex_handle
;
2250 struct hash_entry
*entry
;
2252 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2256 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2258 /* Allow this descriptor slot to be re-used. */
2259 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2261 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2262 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2266 static void si_make_texture_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2269 struct si_context
*sctx
= (struct si_context
*)ctx
;
2270 struct si_texture_handle
*tex_handle
;
2271 struct si_sampler_view
*sview
;
2272 struct hash_entry
*entry
;
2274 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2278 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2279 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2282 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2283 struct si_texture
*tex
= (struct si_texture
*)sview
->base
.texture
;
2285 if (depth_needs_decompression(tex
)) {
2286 util_dynarray_append(&sctx
->resident_tex_needs_depth_decompress
,
2287 struct si_texture_handle
*, tex_handle
);
2290 if (color_needs_decompression(tex
)) {
2291 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
2292 struct si_texture_handle
*, tex_handle
);
2295 if (tex
->surface
.dcc_offset
&& p_atomic_read(&tex
->framebuffers_bound
))
2296 sctx
->need_check_render_feedback
= true;
2298 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2300 si_update_bindless_buffer_descriptor(sctx
, tex_handle
->desc_slot
, sview
->base
.texture
,
2301 sview
->base
.u
.buf
.offset
, &tex_handle
->desc_dirty
);
2304 /* Re-upload the descriptor if it has been updated while it
2307 if (tex_handle
->desc_dirty
)
2308 sctx
->bindless_descriptors_dirty
= true;
2310 /* Add the texture handle to the per-context list. */
2311 util_dynarray_append(&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
);
2313 /* Add the buffers to the current CS in case si_begin_new_cs()
2314 * is not going to be called.
2316 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2317 sview
->is_stencil_sampler
, false);
2319 /* Remove the texture handle from the per-context list. */
2320 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
, struct si_texture_handle
*,
2323 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2324 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_depth_decompress
,
2325 struct si_texture_handle
*, tex_handle
);
2327 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_color_decompress
,
2328 struct si_texture_handle
*, tex_handle
);
2333 static uint64_t si_create_image_handle(struct pipe_context
*ctx
, const struct pipe_image_view
*view
)
2335 struct si_context
*sctx
= (struct si_context
*)ctx
;
2336 struct si_image_handle
*img_handle
;
2337 uint32_t desc_list
[16];
2340 if (!view
|| !view
->resource
)
2343 img_handle
= CALLOC_STRUCT(si_image_handle
);
2347 memset(desc_list
, 0, sizeof(desc_list
));
2348 si_init_descriptor_list(&desc_list
[0], 8, 2, null_image_descriptor
);
2350 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], &desc_list
[8]);
2352 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2353 if (!img_handle
->desc_slot
) {
2358 handle
= img_handle
->desc_slot
;
2360 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)(uintptr_t)handle
, img_handle
)) {
2365 util_copy_image_view(&img_handle
->view
, view
);
2367 si_resource(view
->resource
)->image_handle_allocated
= true;
2372 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2374 struct si_context
*sctx
= (struct si_context
*)ctx
;
2375 struct si_image_handle
*img_handle
;
2376 struct hash_entry
*entry
;
2378 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2382 img_handle
= (struct si_image_handle
*)entry
->data
;
2384 util_copy_image_view(&img_handle
->view
, NULL
);
2385 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2389 static void si_make_image_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2390 unsigned access
, bool resident
)
2392 struct si_context
*sctx
= (struct si_context
*)ctx
;
2393 struct si_image_handle
*img_handle
;
2394 struct pipe_image_view
*view
;
2395 struct si_resource
*res
;
2396 struct hash_entry
*entry
;
2398 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2402 img_handle
= (struct si_image_handle
*)entry
->data
;
2403 view
= &img_handle
->view
;
2404 res
= si_resource(view
->resource
);
2407 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2408 struct si_texture
*tex
= (struct si_texture
*)res
;
2409 unsigned level
= view
->u
.tex
.level
;
2411 if (color_needs_decompression(tex
)) {
2412 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
2413 struct si_image_handle
*, img_handle
);
2416 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
2417 sctx
->need_check_render_feedback
= true;
2419 si_update_bindless_image_descriptor(sctx
, img_handle
);
2421 si_update_bindless_buffer_descriptor(sctx
, img_handle
->desc_slot
, view
->resource
,
2422 view
->u
.buf
.offset
, &img_handle
->desc_dirty
);
2425 /* Re-upload the descriptor if it has been updated while it
2428 if (img_handle
->desc_dirty
)
2429 sctx
->bindless_descriptors_dirty
= true;
2431 /* Add the image handle to the per-context list. */
2432 util_dynarray_append(&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
);
2434 /* Add the buffers to the current CS in case si_begin_new_cs()
2435 * is not going to be called.
2437 si_sampler_view_add_buffer(
2438 sctx
, view
->resource
,
2439 (access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
2442 /* Remove the image handle from the per-context list. */
2443 util_dynarray_delete_unordered(&sctx
->resident_img_handles
, struct si_image_handle
*,
2446 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2447 util_dynarray_delete_unordered(&sctx
->resident_img_needs_color_decompress
,
2448 struct si_image_handle
*, img_handle
);
2453 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2455 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2457 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/ sizeof(struct si_texture_handle
*);
2458 num_resident_img_handles
= sctx
->resident_img_handles
.size
/ sizeof(struct si_image_handle
*);
2460 /* Add all resident texture handles. */
2461 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
2462 struct si_sampler_view
*sview
= (struct si_sampler_view
*)(*tex_handle
)->view
;
2464 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2465 sview
->is_stencil_sampler
, false);
2468 /* Add all resident image handles. */
2469 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
2470 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2472 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
2475 sctx
->num_resident_handles
+= num_resident_tex_handles
+ num_resident_img_handles
;
2476 assert(sctx
->bo_list_add_all_resident_resources
);
2477 sctx
->bo_list_add_all_resident_resources
= false;
2480 /* INIT/DEINIT/UPLOAD */
2482 void si_init_all_descriptors(struct si_context
*sctx
)
2485 unsigned first_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2487 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2489 sctx
->chip_class
>= GFX9
&& (i
== PIPE_SHADER_TESS_CTRL
|| i
== PIPE_SHADER_GEOMETRY
);
2490 unsigned num_sampler_slots
= SI_NUM_IMAGE_SLOTS
/ 2 + SI_NUM_SAMPLERS
;
2491 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2493 struct si_descriptors
*desc
;
2496 if (i
== PIPE_SHADER_TESS_CTRL
) {
2498 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2499 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2501 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2504 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2507 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2509 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2510 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
, num_buffer_slots
,
2511 rel_dw_offset
, RADEON_PRIO_SHADER_RW_BUFFER
,
2512 RADEON_PRIO_CONST_BUFFER
);
2513 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2516 if (i
== PIPE_SHADER_TESS_CTRL
) {
2518 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2519 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2521 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2524 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2527 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2530 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2531 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2534 for (j
= 0; j
< SI_NUM_IMAGE_SLOTS
; j
++)
2535 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2536 for (; j
< SI_NUM_IMAGE_SLOTS
+ SI_NUM_SAMPLERS
* 2; j
++)
2537 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2540 si_init_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2541 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2542 /* The second priority is used by
2543 * const buffers in RW buffer slots. */
2544 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2545 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2547 /* Initialize an array of 1024 bindless descriptors, when the limit is
2548 * reached, just make it larger and re-upload the whole array.
2550 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2551 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
, 1024);
2553 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2555 /* Set pipe_context functions. */
2556 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2557 sctx
->b
.set_shader_images
= si_set_shader_images
;
2558 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2559 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2560 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2561 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2562 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2563 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2564 sctx
->b
.create_image_handle
= si_create_image_handle
;
2565 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2566 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2568 if (!sctx
->has_graphics
)
2571 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2573 /* Shader user data. */
2574 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2576 /* Set default and immutable mappings. */
2578 assert(sctx
->chip_class
>= GFX10
);
2579 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2581 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2584 if (sctx
->chip_class
== GFX9
) {
2585 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2586 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2588 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2589 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2591 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2594 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2596 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2598 /* Assume nothing will go wrong: */
2599 sctx
->shader_pointers_dirty
|= dirty
;
2602 unsigned i
= u_bit_scan(&dirty
);
2604 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2608 sctx
->descriptors_dirty
&= ~mask
;
2610 si_upload_bindless_descriptors(sctx
);
2615 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2617 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2618 return si_upload_shader_descriptors(sctx
, mask
);
2621 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2623 /* Does not update rw_buffers as that is not needed for compute shaders
2624 * and the input buffer is using the same SGPR's anyway.
2626 const unsigned mask
=
2627 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2628 return si_upload_shader_descriptors(sctx
, mask
);
2631 void si_release_all_descriptors(struct si_context
*sctx
)
2635 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2636 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2637 si_const_and_shader_buffer_descriptors(sctx
, i
));
2638 si_release_sampler_views(&sctx
->samplers
[i
]);
2639 si_release_image_views(&sctx
->images
[i
]);
2641 si_release_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2642 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2643 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2645 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2646 si_release_descriptors(&sctx
->descriptors
[i
]);
2648 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2649 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2651 si_release_bindless_descriptors(sctx
);
2654 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2656 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2657 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2658 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2659 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2661 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2662 si_vertex_buffers_begin_new_cs(sctx
);
2664 if (sctx
->bo_list_add_all_resident_resources
)
2665 si_resident_buffers_add_all_to_bo_list(sctx
);
2667 assert(sctx
->bo_list_add_all_gfx_resources
);
2668 sctx
->bo_list_add_all_gfx_resources
= false;
2671 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2673 unsigned sh
= PIPE_SHADER_COMPUTE
;
2675 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2676 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2677 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2678 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2680 if (sctx
->bo_list_add_all_resident_resources
)
2681 si_resident_buffers_add_all_to_bo_list(sctx
);
2683 assert(sctx
->bo_list_add_all_compute_resources
);
2684 sctx
->bo_list_add_all_compute_resources
= false;
2687 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2689 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2690 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2691 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2693 si_shader_pointers_begin_new_cs(sctx
);
2695 sctx
->bo_list_add_all_resident_resources
= true;
2696 sctx
->bo_list_add_all_gfx_resources
= true;
2697 sctx
->bo_list_add_all_compute_resources
= true;
2700 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
, uint64_t new_active_mask
)
2702 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2704 /* Ignore no-op updates and updates that disable all slots. */
2705 if (!new_active_mask
||
2706 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
, desc
->num_active_slots
))
2710 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2711 assert(new_active_mask
== 0);
2713 /* Upload/dump descriptors if slots are being enabled. */
2714 if (first
< desc
->first_active_slot
||
2715 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2716 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2718 desc
->first_active_slot
= first
;
2719 desc
->num_active_slots
= count
;
2722 void si_set_active_descriptors_for_shader(struct si_context
*sctx
, struct si_shader_selector
*sel
)
2727 si_set_active_descriptors(sctx
, si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2728 sel
->active_const_and_shader_buffers
);
2729 si_set_active_descriptors(sctx
, si_sampler_and_image_descriptors_idx(sel
->type
),
2730 sel
->active_samplers_and_images
);