2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 /* Resource binding slots and sampler states (each described with 8 or
25 * 4 dwords) are stored in lists in memory which is accessed by shaders
26 * using scalar load instructions.
28 * This file is responsible for managing such lists. It keeps a copy of all
29 * descriptors in CPU memory and re-uploads a whole list if some slots have
32 * This code is also reponsible for updating shader pointers to those lists.
34 * Note that CP DMA can't be used for updating the lists, because a GPU hang
35 * could leave the list in a mid-IB state and the next IB would get wrong
36 * descriptors and the whole context would be unusable at that point.
37 * (Note: The register shadowing can't be used due to the same reason)
39 * Also, uploading descriptors to newly allocated memory doesn't require
43 * Possible scenarios for one 16 dword image+sampler slot:
45 * | Image | w/ FMASK | Buffer | NULL
46 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
47 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
48 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
49 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 * FMASK implies MSAA, therefore no sampler state.
52 * Sampler states are never unbound except when FMASK is bound.
55 #include "radeon/r600_cs.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
103 if (va
& (1ull << 47))
104 va
|= 0xffffull
<< 48;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 r600_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 r600_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct r600_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
224 si_sampler_and_image_descriptors_idx(unsigned shader
)
226 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
227 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
230 static struct si_descriptors
*
231 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
233 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
236 static void si_release_sampler_views(struct si_samplers
*samplers
)
240 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
241 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
245 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
246 struct pipe_resource
*resource
,
247 enum radeon_bo_usage usage
,
248 bool is_stencil_sampler
,
251 struct r600_resource
*rres
;
252 struct r600_texture
*rtex
;
253 enum radeon_bo_priority priority
;
258 if (resource
->target
!= PIPE_BUFFER
) {
259 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
261 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
262 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
265 rres
= (struct r600_resource
*)resource
;
266 priority
= si_get_sampler_view_priority(rres
);
268 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
269 rres
, usage
, priority
,
272 if (resource
->target
== PIPE_BUFFER
)
275 /* Now add separate DCC or HTILE. */
276 rtex
= (struct r600_texture
*)resource
;
277 if (rtex
->dcc_separate_buffer
) {
278 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
279 rtex
->dcc_separate_buffer
, usage
,
280 RADEON_PRIO_DCC
, check_mem
);
284 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
285 struct si_samplers
*samplers
)
287 unsigned mask
= samplers
->enabled_mask
;
289 /* Add buffers to the CS. */
291 int i
= u_bit_scan(&mask
);
292 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
294 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
296 sview
->is_stencil_sampler
, false);
300 /* Set buffer descriptor fields that can be changed by reallocations. */
301 static void si_set_buf_desc_address(struct r600_resource
*buf
,
302 uint64_t offset
, uint32_t *state
)
304 uint64_t va
= buf
->gpu_address
+ offset
;
307 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
308 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
311 /* Set texture descriptor fields that can be changed by reallocations.
314 * \param base_level_info information of the level of BASE_ADDRESS
315 * \param base_level the level of BASE_ADDRESS
316 * \param first_level pipe_sampler_view.u.tex.first_level
317 * \param block_width util_format_get_blockwidth()
318 * \param is_stencil select between separate Z & Stencil
319 * \param state descriptor to update
321 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
322 struct r600_texture
*tex
,
323 const struct legacy_surf_level
*base_level_info
,
324 unsigned base_level
, unsigned first_level
,
325 unsigned block_width
, bool is_stencil
,
328 uint64_t va
, meta_va
= 0;
330 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
331 tex
= tex
->flushed_depth_texture
;
335 va
= tex
->resource
.gpu_address
;
337 if (sscreen
->info
.chip_class
>= GFX9
) {
338 /* Only stencil_offset needs to be added here. */
340 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
342 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
344 va
+= base_level_info
->offset
;
348 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
349 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
351 /* Only macrotiled modes can set tile swizzle.
352 * GFX9 doesn't use (legacy) base_level_info.
354 if (sscreen
->info
.chip_class
>= GFX9
||
355 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
356 state
[0] |= tex
->surface
.tile_swizzle
;
358 if (sscreen
->info
.chip_class
>= VI
) {
359 state
[6] &= C_008F28_COMPRESSION_EN
;
362 if (vi_dcc_enabled(tex
, first_level
)) {
363 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
366 if (sscreen
->info
.chip_class
== VI
) {
367 meta_va
+= base_level_info
->dcc_offset
;
368 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
371 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
372 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
373 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
377 state
[6] |= S_008F28_COMPRESSION_EN(1);
378 state
[7] = meta_va
>> 8;
382 if (sscreen
->info
.chip_class
>= GFX9
) {
383 state
[3] &= C_008F1C_SW_MODE
;
384 state
[4] &= C_008F20_PITCH_GFX9
;
387 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
388 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
390 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
391 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
394 state
[5] &= C_008F24_META_DATA_ADDRESS
&
395 C_008F24_META_PIPE_ALIGNED
&
396 C_008F24_META_RB_ALIGNED
;
398 struct gfx9_surf_meta_flags meta
;
401 meta
= tex
->surface
.u
.gfx9
.dcc
;
403 meta
= tex
->surface
.u
.gfx9
.htile
;
405 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
406 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
407 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
411 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
412 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
414 state
[3] &= C_008F1C_TILING_INDEX
;
415 state
[3] |= S_008F1C_TILING_INDEX(index
);
416 state
[4] &= C_008F20_PITCH_GFX6
;
417 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
421 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
422 struct si_sampler_view
*sview
,
423 struct r600_texture
*tex
,
426 if (sview
&& sview
->is_integer
)
427 memcpy(desc
, sstate
->integer_val
, 4*4);
428 else if (tex
&& tex
->upgraded_depth
&&
429 (!sview
|| !sview
->is_stencil_sampler
))
430 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
432 memcpy(desc
, sstate
->val
, 4*4);
435 static void si_set_sampler_view_desc(struct si_context
*sctx
,
436 struct si_sampler_view
*sview
,
437 struct si_sampler_state
*sstate
,
440 struct pipe_sampler_view
*view
= &sview
->base
;
441 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
442 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
444 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
445 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
446 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
447 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
449 sview
->dcc_incompatible
= false;
452 assert(rtex
); /* views with texture == NULL aren't supported */
453 memcpy(desc
, sview
->state
, 8*4);
456 si_set_buf_desc_address(&rtex
->resource
,
457 sview
->base
.u
.buf
.offset
,
460 bool is_separate_stencil
= rtex
->db_compatible
&&
461 sview
->is_stencil_sampler
;
463 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
464 sview
->base_level_info
,
466 sview
->base
.u
.tex
.first_level
,
472 if (!is_buffer
&& rtex
->fmask
.size
) {
473 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
475 /* Disable FMASK and bind sampler state in [12:15]. */
476 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
479 si_set_sampler_state_desc(sstate
, sview
,
480 is_buffer
? NULL
: rtex
,
485 static bool color_needs_decompression(struct r600_texture
*rtex
)
487 return rtex
->fmask
.size
||
488 (rtex
->dirty_level_mask
&&
489 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
492 static bool depth_needs_decompression(struct r600_texture
*rtex
)
494 /* If the depth/stencil texture is TC-compatible, no decompression
495 * will be done. The decompression function will only flush DB caches
496 * to make it coherent with shaders. That's necessary because the driver
497 * doesn't flush DB caches in any other case.
499 return rtex
->db_compatible
;
502 static void si_set_sampler_view(struct si_context
*sctx
,
504 unsigned slot
, struct pipe_sampler_view
*view
,
505 bool disallow_early_out
)
507 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
508 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
509 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
510 unsigned desc_slot
= si_get_sampler_slot(slot
);
511 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
513 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
517 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
519 si_set_sampler_view_desc(sctx
, rview
,
520 samplers
->sampler_states
[slot
], desc
);
522 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
523 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
524 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
525 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
527 if (depth_needs_decompression(rtex
)) {
528 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
530 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
532 if (color_needs_decompression(rtex
)) {
533 samplers
->needs_color_decompress_mask
|= 1u << slot
;
535 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
538 if (rtex
->dcc_offset
&&
539 p_atomic_read(&rtex
->framebuffers_bound
))
540 sctx
->need_check_render_feedback
= true;
543 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
544 samplers
->enabled_mask
|= 1u << slot
;
546 /* Since this can flush, it must be done after enabled_mask is
548 si_sampler_view_add_buffer(sctx
, view
->texture
,
550 rview
->is_stencil_sampler
, true);
552 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
553 memcpy(desc
, null_texture_descriptor
, 8*4);
554 /* Only clear the lower dwords of FMASK. */
555 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
556 /* Re-set the sampler state if we are transitioning from FMASK. */
557 if (samplers
->sampler_states
[slot
])
558 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
561 samplers
->enabled_mask
&= ~(1u << slot
);
562 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
563 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
566 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
569 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
572 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
573 unsigned shader_bit
= 1 << shader
;
575 if (samplers
->needs_depth_decompress_mask
||
576 samplers
->needs_color_decompress_mask
||
577 sctx
->images
[shader
].needs_color_decompress_mask
)
578 sctx
->shader_needs_decompress_mask
|= shader_bit
;
580 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
583 static void si_set_sampler_views(struct pipe_context
*ctx
,
584 enum pipe_shader_type shader
, unsigned start
,
586 struct pipe_sampler_view
**views
)
588 struct si_context
*sctx
= (struct si_context
*)ctx
;
591 if (!count
|| shader
>= SI_NUM_SHADERS
)
595 for (i
= 0; i
< count
; i
++)
596 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
598 for (i
= 0; i
< count
; i
++)
599 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
602 si_update_shader_needs_decompress_mask(sctx
, shader
);
606 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
608 unsigned mask
= samplers
->enabled_mask
;
611 int i
= u_bit_scan(&mask
);
612 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
614 if (res
&& res
->target
!= PIPE_BUFFER
) {
615 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
617 if (color_needs_decompression(rtex
)) {
618 samplers
->needs_color_decompress_mask
|= 1u << i
;
620 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
629 si_release_image_views(struct si_images
*images
)
633 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
634 struct pipe_image_view
*view
= &images
->views
[i
];
636 pipe_resource_reference(&view
->resource
, NULL
);
641 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
643 uint mask
= images
->enabled_mask
;
645 /* Add buffers to the CS. */
647 int i
= u_bit_scan(&mask
);
648 struct pipe_image_view
*view
= &images
->views
[i
];
650 assert(view
->resource
);
652 si_sampler_view_add_buffer(sctx
, view
->resource
,
653 RADEON_USAGE_READWRITE
, false, false);
658 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
660 struct si_images
*images
= &ctx
->images
[shader
];
662 if (images
->enabled_mask
& (1u << slot
)) {
663 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
664 unsigned desc_slot
= si_get_image_slot(slot
);
666 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
667 images
->needs_color_decompress_mask
&= ~(1 << slot
);
669 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
670 images
->enabled_mask
&= ~(1u << slot
);
671 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
676 si_mark_image_range_valid(const struct pipe_image_view
*view
)
678 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
680 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
682 util_range_add(&res
->valid_buffer_range
,
684 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
687 static void si_set_shader_image_desc(struct si_context
*ctx
,
688 const struct pipe_image_view
*view
,
689 bool skip_decompress
,
690 uint32_t *desc
, uint32_t *fmask_desc
)
692 struct si_screen
*screen
= ctx
->screen
;
693 struct r600_resource
*res
;
695 res
= (struct r600_resource
*)view
->resource
;
697 if (res
->b
.b
.target
== PIPE_BUFFER
) {
698 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
699 si_mark_image_range_valid(view
);
701 si_make_buffer_descriptor(screen
, res
,
704 view
->u
.buf
.size
, desc
);
705 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
707 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
708 struct r600_texture
*tex
= (struct r600_texture
*)res
;
709 unsigned level
= view
->u
.tex
.level
;
710 unsigned width
, height
, depth
, hw_level
;
711 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
712 unsigned access
= view
->access
;
714 /* Clear the write flag when writes can't occur.
715 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
716 * so we don't wanna trigger it.
719 (!fmask_desc
&& tex
->fmask
.size
!= 0)) {
720 assert(!"Z/S and MSAA image stores are not supported");
721 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
724 assert(!tex
->is_depth
);
725 assert(fmask_desc
|| tex
->fmask
.size
== 0);
727 if (uses_dcc
&& !skip_decompress
&&
728 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
729 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
730 /* If DCC can't be disabled, at least decompress it.
731 * The decompression is relatively cheap if the surface
732 * has been decompressed already.
734 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
735 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
738 if (ctx
->b
.chip_class
>= GFX9
) {
739 /* Always set the base address. The swizzle modes don't
740 * allow setting mipmap level offsets as the base.
742 width
= res
->b
.b
.width0
;
743 height
= res
->b
.b
.height0
;
744 depth
= res
->b
.b
.depth0
;
747 /* Always force the base level to the selected level.
749 * This is required for 3D textures, where otherwise
750 * selecting a single slice for non-layered bindings
751 * fails. It doesn't hurt the other targets.
753 width
= u_minify(res
->b
.b
.width0
, level
);
754 height
= u_minify(res
->b
.b
.height0
, level
);
755 depth
= u_minify(res
->b
.b
.depth0
, level
);
759 si_make_texture_descriptor(screen
, tex
,
760 false, res
->b
.b
.target
,
761 view
->format
, swizzle
,
763 view
->u
.tex
.first_layer
,
764 view
->u
.tex
.last_layer
,
765 width
, height
, depth
,
767 si_set_mutable_tex_desc_fields(screen
, tex
,
768 &tex
->surface
.u
.legacy
.level
[level
],
770 util_format_get_blockwidth(view
->format
),
775 static void si_set_shader_image(struct si_context
*ctx
,
777 unsigned slot
, const struct pipe_image_view
*view
,
778 bool skip_decompress
)
780 struct si_images
*images
= &ctx
->images
[shader
];
781 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
782 struct r600_resource
*res
;
783 unsigned desc_slot
= si_get_image_slot(slot
);
784 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
786 if (!view
|| !view
->resource
) {
787 si_disable_shader_image(ctx
, shader
, slot
);
791 res
= (struct r600_resource
*)view
->resource
;
793 if (&images
->views
[slot
] != view
)
794 util_copy_image_view(&images
->views
[slot
], view
);
796 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
798 if (res
->b
.b
.target
== PIPE_BUFFER
) {
799 images
->needs_color_decompress_mask
&= ~(1 << slot
);
800 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
802 struct r600_texture
*tex
= (struct r600_texture
*)res
;
803 unsigned level
= view
->u
.tex
.level
;
805 if (color_needs_decompression(tex
)) {
806 images
->needs_color_decompress_mask
|= 1 << slot
;
808 images
->needs_color_decompress_mask
&= ~(1 << slot
);
811 if (vi_dcc_enabled(tex
, level
) &&
812 p_atomic_read(&tex
->framebuffers_bound
))
813 ctx
->need_check_render_feedback
= true;
816 images
->enabled_mask
|= 1u << slot
;
817 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
819 /* Since this can flush, it must be done after enabled_mask is updated. */
820 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
821 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
822 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
827 si_set_shader_images(struct pipe_context
*pipe
,
828 enum pipe_shader_type shader
,
829 unsigned start_slot
, unsigned count
,
830 const struct pipe_image_view
*views
)
832 struct si_context
*ctx
= (struct si_context
*)pipe
;
835 assert(shader
< SI_NUM_SHADERS
);
840 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
843 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
844 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
846 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
847 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
850 si_update_shader_needs_decompress_mask(ctx
, shader
);
854 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
856 unsigned mask
= images
->enabled_mask
;
859 int i
= u_bit_scan(&mask
);
860 struct pipe_resource
*res
= images
->views
[i
].resource
;
862 if (res
&& res
->target
!= PIPE_BUFFER
) {
863 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
865 if (color_needs_decompression(rtex
)) {
866 images
->needs_color_decompress_mask
|= 1 << i
;
868 images
->needs_color_decompress_mask
&= ~(1 << i
);
874 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
876 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
877 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
878 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
879 struct pipe_surface
*surf
= NULL
;
881 /* si_texture_disable_dcc can get us here again. */
882 if (sctx
->blitter
->running
)
885 /* See whether FBFETCH is used and color buffer 0 is set. */
886 if (sctx
->ps_shader
.cso
&&
887 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
888 sctx
->framebuffer
.state
.nr_cbufs
&&
889 sctx
->framebuffer
.state
.cbufs
[0])
890 surf
= sctx
->framebuffer
.state
.cbufs
[0];
892 /* Return if FBFETCH transitions from disabled to disabled. */
893 if (!buffers
->buffers
[slot
] && !surf
)
896 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
897 si_update_ps_iter_samples(sctx
);
900 struct r600_texture
*tex
= (struct r600_texture
*)surf
->texture
;
901 struct pipe_image_view view
;
904 assert(!tex
->is_depth
);
906 /* Disable DCC, because the texture is used as both a sampler
909 si_texture_disable_dcc(&sctx
->b
, tex
);
911 if (tex
->resource
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
913 assert(tex
->cmask_buffer
!= &tex
->resource
);
914 si_eliminate_fast_color_clear(&sctx
->b
, tex
);
915 si_texture_discard_cmask(sctx
->screen
, tex
);
918 view
.resource
= surf
->texture
;
919 view
.format
= surf
->format
;
920 view
.access
= PIPE_IMAGE_ACCESS_READ
;
921 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
922 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
923 view
.u
.tex
.level
= surf
->u
.tex
.level
;
925 /* Set the descriptor. */
926 uint32_t *desc
= descs
->list
+ slot
*4;
927 memset(desc
, 0, 16 * 4);
928 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
930 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->resource
.b
.b
);
931 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
932 &tex
->resource
, RADEON_USAGE_READ
,
933 RADEON_PRIO_SHADER_RW_IMAGE
);
934 buffers
->enabled_mask
|= 1u << slot
;
936 /* Clear the descriptor. */
937 memset(descs
->list
+ slot
*4, 0, 8*4);
938 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
939 buffers
->enabled_mask
&= ~(1u << slot
);
942 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
947 static void si_bind_sampler_states(struct pipe_context
*ctx
,
948 enum pipe_shader_type shader
,
949 unsigned start
, unsigned count
, void **states
)
951 struct si_context
*sctx
= (struct si_context
*)ctx
;
952 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
953 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
954 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
957 if (!count
|| shader
>= SI_NUM_SHADERS
)
960 for (i
= 0; i
< count
; i
++) {
961 unsigned slot
= start
+ i
;
962 unsigned desc_slot
= si_get_sampler_slot(slot
);
965 sstates
[i
] == samplers
->sampler_states
[slot
])
969 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
971 samplers
->sampler_states
[slot
] = sstates
[i
];
973 /* If FMASK is bound, don't overwrite it.
974 * The sampler state will be set after FMASK is unbound.
976 struct si_sampler_view
*sview
=
977 (struct si_sampler_view
*)samplers
->views
[slot
];
979 struct r600_texture
*tex
= NULL
;
981 if (sview
&& sview
->base
.texture
&&
982 sview
->base
.texture
->target
!= PIPE_BUFFER
)
983 tex
= (struct r600_texture
*)sview
->base
.texture
;
985 if (tex
&& tex
->fmask
.size
)
988 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
989 desc
->list
+ desc_slot
* 16 + 12);
991 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
995 /* BUFFER RESOURCES */
997 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
998 struct si_descriptors
*descs
,
999 unsigned num_buffers
,
1000 short shader_userdata_rel_index
,
1001 enum radeon_bo_usage shader_usage
,
1002 enum radeon_bo_usage shader_usage_constbuf
,
1003 enum radeon_bo_priority priority
,
1004 enum radeon_bo_priority priority_constbuf
)
1006 buffers
->shader_usage
= shader_usage
;
1007 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
1008 buffers
->priority
= priority
;
1009 buffers
->priority_constbuf
= priority_constbuf
;
1010 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1012 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1015 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1016 struct si_descriptors
*descs
)
1020 for (i
= 0; i
< descs
->num_elements
; i
++) {
1021 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1024 FREE(buffers
->buffers
);
1027 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1028 struct si_buffer_resources
*buffers
)
1030 unsigned mask
= buffers
->enabled_mask
;
1032 /* Add buffers to the CS. */
1034 int i
= u_bit_scan(&mask
);
1036 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1037 r600_resource(buffers
->buffers
[i
]),
1038 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1039 buffers
->shader_usage_constbuf
,
1040 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1041 buffers
->priority_constbuf
);
1045 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1046 struct si_descriptors
*descs
,
1047 unsigned idx
, struct pipe_resource
**buf
,
1048 unsigned *offset
, unsigned *size
)
1050 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1052 struct r600_resource
*res
= r600_resource(*buf
);
1053 const uint32_t *desc
= descs
->list
+ idx
* 4;
1058 assert(G_008F04_STRIDE(desc
[1]) == 0);
1059 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1061 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1062 *offset
= va
- res
->gpu_address
;
1066 /* VERTEX BUFFERS */
1068 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1070 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1073 for (i
= 0; i
< count
; i
++) {
1074 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1076 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1078 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1081 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1082 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1083 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1086 if (!sctx
->vb_descriptors_buffer
)
1088 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1089 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1090 RADEON_PRIO_DESCRIPTORS
);
1093 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1095 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1097 unsigned desc_list_byte_size
;
1098 unsigned first_vb_use_mask
;
1101 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1104 count
= velems
->count
;
1109 desc_list_byte_size
= velems
->desc_list_byte_size
;
1110 first_vb_use_mask
= velems
->first_vb_use_mask
;
1112 /* Vertex buffer descriptors are the only ones which are uploaded
1113 * directly through a staging buffer and don't go through
1114 * the fine-grained upload path.
1116 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1117 desc_list_byte_size
,
1118 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1119 &sctx
->vb_descriptors_offset
,
1120 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1122 if (!sctx
->vb_descriptors_buffer
) {
1123 sctx
->vb_descriptors_offset
= 0;
1124 sctx
->vb_descriptors_gpu_list
= NULL
;
1128 sctx
->vb_descriptors_gpu_list
= ptr
;
1129 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1130 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1131 RADEON_PRIO_DESCRIPTORS
);
1133 assert(count
<= SI_MAX_ATTRIBS
);
1135 for (i
= 0; i
< count
; i
++) {
1136 struct pipe_vertex_buffer
*vb
;
1137 struct r600_resource
*rbuffer
;
1138 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1139 uint32_t *desc
= &ptr
[i
*4];
1141 vb
= &sctx
->vertex_buffer
[vbo_index
];
1142 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1144 memset(desc
, 0, 16);
1148 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1149 velems
->src_offset
[i
];
1150 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1152 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1153 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1154 /* Round up by rounding down and adding 1 */
1155 num_records
= (num_records
- velems
->format_size
[i
]) /
1158 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1161 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1162 S_008F04_STRIDE(vb
->stride
);
1163 desc
[2] = num_records
;
1164 desc
[3] = velems
->rsrc_word3
[i
];
1166 if (first_vb_use_mask
& (1 << i
)) {
1167 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1168 (struct r600_resource
*)vb
->buffer
.resource
,
1169 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1173 /* Don't flush the const cache. It would have a very negative effect
1174 * on performance (confirmed by testing). New descriptors are always
1175 * uploaded to a fresh new buffer, so I don't think flushing the const
1176 * cache is needed. */
1177 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1178 sctx
->vertex_buffers_dirty
= false;
1179 sctx
->vertex_buffer_pointer_dirty
= true;
1180 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1185 /* CONSTANT BUFFERS */
1188 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1190 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1191 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1194 static struct si_descriptors
*
1195 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1197 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1200 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1201 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1205 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1206 si_optimal_tcc_alignment(sctx
, size
),
1208 (struct pipe_resource
**)rbuffer
, &tmp
);
1210 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1213 static void si_set_constant_buffer(struct si_context
*sctx
,
1214 struct si_buffer_resources
*buffers
,
1215 unsigned descriptors_idx
,
1216 uint slot
, const struct pipe_constant_buffer
*input
)
1218 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1219 assert(slot
< descs
->num_elements
);
1220 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1222 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1223 * with a NULL buffer). We need to use a dummy buffer instead. */
1224 if (sctx
->b
.chip_class
== CIK
&&
1225 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1226 input
= &sctx
->null_const_buf
;
1228 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1229 struct pipe_resource
*buffer
= NULL
;
1232 /* Upload the user buffer if needed. */
1233 if (input
->user_buffer
) {
1234 unsigned buffer_offset
;
1236 si_upload_const_buffer(sctx
,
1237 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1238 input
->buffer_size
, &buffer_offset
);
1240 /* Just unbind on failure. */
1241 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1244 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1246 pipe_resource_reference(&buffer
, input
->buffer
);
1247 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1248 /* Only track usage for non-user buffers. */
1249 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1252 /* Set the descriptor. */
1253 uint32_t *desc
= descs
->list
+ slot
*4;
1255 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1257 desc
[2] = input
->buffer_size
;
1258 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1259 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1260 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1261 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1262 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1263 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1265 buffers
->buffers
[slot
] = buffer
;
1266 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1267 (struct r600_resource
*)buffer
,
1268 buffers
->shader_usage_constbuf
,
1269 buffers
->priority_constbuf
, true);
1270 buffers
->enabled_mask
|= 1u << slot
;
1272 /* Clear the descriptor. */
1273 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1274 buffers
->enabled_mask
&= ~(1u << slot
);
1277 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1280 void si_set_rw_buffer(struct si_context
*sctx
,
1281 uint slot
, const struct pipe_constant_buffer
*input
)
1283 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1284 SI_DESCS_RW_BUFFERS
, slot
, input
);
1287 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1288 enum pipe_shader_type shader
, uint slot
,
1289 const struct pipe_constant_buffer
*input
)
1291 struct si_context
*sctx
= (struct si_context
*)ctx
;
1293 if (shader
>= SI_NUM_SHADERS
)
1296 if (slot
== 0 && input
&& input
->buffer
&&
1297 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1298 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1302 slot
= si_get_constbuf_slot(slot
);
1303 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1304 si_const_and_shader_buffer_descriptors_idx(shader
),
1308 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1309 uint slot
, struct pipe_constant_buffer
*cbuf
)
1311 cbuf
->user_buffer
= NULL
;
1312 si_get_buffer_from_descriptors(
1313 &sctx
->const_and_shader_buffers
[shader
],
1314 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1315 si_get_constbuf_slot(slot
),
1316 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1319 /* SHADER BUFFERS */
1321 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1322 enum pipe_shader_type shader
,
1323 unsigned start_slot
, unsigned count
,
1324 const struct pipe_shader_buffer
*sbuffers
)
1326 struct si_context
*sctx
= (struct si_context
*)ctx
;
1327 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1328 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1331 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1333 for (i
= 0; i
< count
; ++i
) {
1334 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1335 struct r600_resource
*buf
;
1336 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1337 uint32_t *desc
= descs
->list
+ slot
* 4;
1340 if (!sbuffer
|| !sbuffer
->buffer
) {
1341 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1342 memset(desc
, 0, sizeof(uint32_t) * 4);
1343 buffers
->enabled_mask
&= ~(1u << slot
);
1344 sctx
->descriptors_dirty
|=
1345 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1349 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1350 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1353 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1355 desc
[2] = sbuffer
->buffer_size
;
1356 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1357 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1358 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1359 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1360 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1361 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1363 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1364 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1365 buffers
->shader_usage
,
1366 buffers
->priority
, true);
1367 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1369 buffers
->enabled_mask
|= 1u << slot
;
1370 sctx
->descriptors_dirty
|=
1371 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1373 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1374 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1378 void si_get_shader_buffers(struct si_context
*sctx
,
1379 enum pipe_shader_type shader
,
1380 uint start_slot
, uint count
,
1381 struct pipe_shader_buffer
*sbuf
)
1383 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1384 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1386 for (unsigned i
= 0; i
< count
; ++i
) {
1387 si_get_buffer_from_descriptors(
1389 si_get_shaderbuf_slot(start_slot
+ i
),
1390 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1391 &sbuf
[i
].buffer_size
);
1397 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1398 struct pipe_resource
*buffer
,
1399 unsigned stride
, unsigned num_records
,
1400 bool add_tid
, bool swizzle
,
1401 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1403 struct si_context
*sctx
= (struct si_context
*)ctx
;
1404 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1405 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1407 /* The stride field in the resource descriptor has 14 bits */
1408 assert(stride
< (1 << 14));
1410 assert(slot
< descs
->num_elements
);
1411 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1416 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1418 switch (element_size
) {
1420 assert(!"Unsupported ring buffer element size");
1436 switch (index_stride
) {
1438 assert(!"Unsupported ring buffer index stride");
1454 if (sctx
->b
.chip_class
>= VI
&& stride
)
1455 num_records
*= stride
;
1457 /* Set the descriptor. */
1458 uint32_t *desc
= descs
->list
+ slot
*4;
1460 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1461 S_008F04_STRIDE(stride
) |
1462 S_008F04_SWIZZLE_ENABLE(swizzle
);
1463 desc
[2] = num_records
;
1464 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1468 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1469 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1470 S_008F0C_INDEX_STRIDE(index_stride
) |
1471 S_008F0C_ADD_TID_ENABLE(add_tid
);
1473 if (sctx
->b
.chip_class
>= GFX9
)
1474 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1476 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1478 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1479 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1480 (struct r600_resource
*)buffer
,
1481 buffers
->shader_usage
, buffers
->priority
);
1482 buffers
->enabled_mask
|= 1u << slot
;
1484 /* Clear the descriptor. */
1485 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1486 buffers
->enabled_mask
&= ~(1u << slot
);
1489 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1492 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1493 uint32_t *desc
, uint64_t old_buf_va
,
1494 struct pipe_resource
*new_buf
)
1496 /* Retrieve the buffer offset from the descriptor. */
1497 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1499 assert(old_buf_va
<= old_desc_va
);
1500 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1502 /* Update the descriptor. */
1503 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1507 /* INTERNAL CONST BUFFERS */
1509 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1510 const struct pipe_poly_stipple
*state
)
1512 struct si_context
*sctx
= (struct si_context
*)ctx
;
1513 struct pipe_constant_buffer cb
= {};
1514 unsigned stipple
[32];
1517 for (i
= 0; i
< 32; i
++)
1518 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1520 cb
.user_buffer
= stipple
;
1521 cb
.buffer_size
= sizeof(stipple
);
1523 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1526 /* TEXTURE METADATA ENABLE/DISABLE */
1529 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1531 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1532 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1534 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1535 struct si_texture_handle
*, tex_handle
) {
1536 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1537 struct r600_texture
*rtex
;
1539 if (!res
|| res
->target
== PIPE_BUFFER
)
1542 rtex
= (struct r600_texture
*)res
;
1543 if (!color_needs_decompression(rtex
))
1546 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1547 struct si_texture_handle
*, *tex_handle
);
1550 util_dynarray_foreach(&sctx
->resident_img_handles
,
1551 struct si_image_handle
*, img_handle
) {
1552 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1553 struct pipe_resource
*res
= view
->resource
;
1554 struct r600_texture
*rtex
;
1556 if (!res
|| res
->target
== PIPE_BUFFER
)
1559 rtex
= (struct r600_texture
*)res
;
1560 if (!color_needs_decompression(rtex
))
1563 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1564 struct si_image_handle
*, *img_handle
);
1568 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1569 * while the texture is bound, possibly by a different context. In that case,
1570 * call this function to update needs_*_decompress_masks.
1572 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1574 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1575 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1576 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1577 si_update_shader_needs_decompress_mask(sctx
, i
);
1580 si_resident_handles_update_needs_color_decompress(sctx
);
1583 /* BUFFER DISCARD/INVALIDATION */
1585 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1586 static void si_reset_buffer_resources(struct si_context
*sctx
,
1587 struct si_buffer_resources
*buffers
,
1588 unsigned descriptors_idx
,
1590 struct pipe_resource
*buf
,
1592 enum radeon_bo_usage usage
,
1593 enum radeon_bo_priority priority
)
1595 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1596 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1599 unsigned i
= u_bit_scan(&mask
);
1600 if (buffers
->buffers
[i
] == buf
) {
1601 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1604 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1606 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1607 (struct r600_resource
*)buf
,
1608 usage
, priority
, true);
1613 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1616 struct si_context
*sctx
= (struct si_context
*)ctx
;
1617 struct r600_resource
*rbuffer
= r600_resource(buf
);
1619 unsigned num_elems
= sctx
->vertex_elements
?
1620 sctx
->vertex_elements
->count
: 0;
1622 /* We changed the buffer, now we need to bind it where the old one
1623 * was bound. This consists of 2 things:
1624 * 1) Updating the resource descriptor and dirtying it.
1625 * 2) Adding a relocation to the CS, so that it's usable.
1628 /* Vertex buffers. */
1629 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1630 for (i
= 0; i
< num_elems
; i
++) {
1631 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1633 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1635 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1638 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1639 sctx
->vertex_buffers_dirty
= true;
1645 /* Streamout buffers. (other internal buffers can't be invalidated) */
1646 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1647 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1648 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1649 struct si_descriptors
*descs
=
1650 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1652 if (buffers
->buffers
[i
] != buf
)
1655 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1657 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1659 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1660 rbuffer
, buffers
->shader_usage
,
1661 RADEON_PRIO_SHADER_RW_BUFFER
,
1664 /* Update the streamout state. */
1665 if (sctx
->streamout
.begin_emitted
)
1666 si_emit_streamout_end(sctx
);
1667 sctx
->streamout
.append_bitmask
=
1668 sctx
->streamout
.enabled_mask
;
1669 si_streamout_buffers_dirty(sctx
);
1673 /* Constant and shader buffers. */
1674 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1675 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1676 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1677 si_const_and_shader_buffer_descriptors_idx(shader
),
1678 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1680 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1681 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1684 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1685 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1686 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1687 si_const_and_shader_buffer_descriptors_idx(shader
),
1688 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1690 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1691 sctx
->const_and_shader_buffers
[shader
].priority
);
1694 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1695 /* Texture buffers - update bindings. */
1696 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1697 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1698 struct si_descriptors
*descs
=
1699 si_sampler_and_image_descriptors(sctx
, shader
);
1700 unsigned mask
= samplers
->enabled_mask
;
1703 unsigned i
= u_bit_scan(&mask
);
1704 if (samplers
->views
[i
]->texture
== buf
) {
1705 unsigned desc_slot
= si_get_sampler_slot(i
);
1707 si_desc_reset_buffer_offset(ctx
,
1711 sctx
->descriptors_dirty
|=
1712 1u << si_sampler_and_image_descriptors_idx(shader
);
1714 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1715 rbuffer
, RADEON_USAGE_READ
,
1716 RADEON_PRIO_SAMPLER_BUFFER
,
1724 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1725 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1726 struct si_images
*images
= &sctx
->images
[shader
];
1727 struct si_descriptors
*descs
=
1728 si_sampler_and_image_descriptors(sctx
, shader
);
1729 unsigned mask
= images
->enabled_mask
;
1732 unsigned i
= u_bit_scan(&mask
);
1734 if (images
->views
[i
].resource
== buf
) {
1735 unsigned desc_slot
= si_get_image_slot(i
);
1737 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1738 si_mark_image_range_valid(&images
->views
[i
]);
1740 si_desc_reset_buffer_offset(
1741 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1743 sctx
->descriptors_dirty
|=
1744 1u << si_sampler_and_image_descriptors_idx(shader
);
1746 radeon_add_to_buffer_list_check_mem(
1747 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1748 RADEON_USAGE_READWRITE
,
1749 RADEON_PRIO_SAMPLER_BUFFER
, true);
1755 /* Bindless texture handles */
1756 if (rbuffer
->texture_handle_allocated
) {
1757 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1759 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1760 struct si_texture_handle
*, tex_handle
) {
1761 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1762 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1764 if (view
->texture
== buf
) {
1765 si_set_buf_desc_address(rbuffer
,
1768 desc_slot
* 16 + 4);
1770 (*tex_handle
)->desc_dirty
= true;
1771 sctx
->bindless_descriptors_dirty
= true;
1773 radeon_add_to_buffer_list_check_mem(
1774 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1776 RADEON_PRIO_SAMPLER_BUFFER
, true);
1781 /* Bindless image handles */
1782 if (rbuffer
->image_handle_allocated
) {
1783 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1785 util_dynarray_foreach(&sctx
->resident_img_handles
,
1786 struct si_image_handle
*, img_handle
) {
1787 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1788 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1790 if (view
->resource
== buf
) {
1791 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1792 si_mark_image_range_valid(view
);
1794 si_set_buf_desc_address(rbuffer
,
1797 desc_slot
* 16 + 4);
1799 (*img_handle
)->desc_dirty
= true;
1800 sctx
->bindless_descriptors_dirty
= true;
1802 radeon_add_to_buffer_list_check_mem(
1803 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1804 RADEON_USAGE_READWRITE
,
1805 RADEON_PRIO_SAMPLER_BUFFER
, true);
1811 /* Reallocate a buffer a update all resource bindings where the buffer is
1814 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1815 * idle by discarding its contents. Apps usually tell us when to do this using
1816 * map_buffer flags, for example.
1818 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1820 struct si_context
*sctx
= (struct si_context
*)ctx
;
1821 struct r600_resource
*rbuffer
= r600_resource(buf
);
1822 uint64_t old_va
= rbuffer
->gpu_address
;
1824 /* Reallocate the buffer in the same pipe_resource. */
1825 si_alloc_resource(sctx
->screen
, rbuffer
);
1827 si_rebind_buffer(ctx
, buf
, old_va
);
1830 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1832 unsigned num_dwords
)
1834 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1835 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1836 unsigned desc_slot_offset
= desc_slot
* 16;
1840 data
= desc
->list
+ desc_slot_offset
;
1841 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1843 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1844 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1845 S_370_WR_CONFIRM(1) |
1846 S_370_ENGINE_SEL(V_370_ME
));
1847 radeon_emit(cs
, va
);
1848 radeon_emit(cs
, va
>> 32);
1849 radeon_emit_array(cs
, data
, num_dwords
);
1852 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1854 if (!sctx
->bindless_descriptors_dirty
)
1857 /* Wait for graphics/compute to be idle before updating the resident
1858 * descriptors directly in memory, in case the GPU is using them.
1860 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1861 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1862 si_emit_cache_flush(sctx
);
1864 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1865 struct si_texture_handle
*, tex_handle
) {
1866 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1868 if (!(*tex_handle
)->desc_dirty
)
1871 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1872 (*tex_handle
)->desc_dirty
= false;
1875 util_dynarray_foreach(&sctx
->resident_img_handles
,
1876 struct si_image_handle
*, img_handle
) {
1877 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1879 if (!(*img_handle
)->desc_dirty
)
1882 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1883 (*img_handle
)->desc_dirty
= false;
1886 /* Invalidate L1 because it doesn't know that L2 changed. */
1887 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1888 si_emit_cache_flush(sctx
);
1890 sctx
->bindless_descriptors_dirty
= false;
1893 /* Update mutable image descriptor fields of all resident textures. */
1894 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1895 struct si_texture_handle
*tex_handle
)
1897 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1898 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1899 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1900 uint32_t desc_list
[16];
1902 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1905 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1906 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1907 desc
->list
+ desc_slot_offset
);
1909 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1910 sizeof(desc_list
))) {
1911 tex_handle
->desc_dirty
= true;
1912 sctx
->bindless_descriptors_dirty
= true;
1916 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1917 struct si_image_handle
*img_handle
)
1919 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1920 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1921 struct pipe_image_view
*view
= &img_handle
->view
;
1922 uint32_t desc_list
[8];
1924 if (view
->resource
->target
== PIPE_BUFFER
)
1927 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1929 si_set_shader_image_desc(sctx
, view
, true,
1930 desc
->list
+ desc_slot_offset
, NULL
);
1932 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1933 sizeof(desc_list
))) {
1934 img_handle
->desc_dirty
= true;
1935 sctx
->bindless_descriptors_dirty
= true;
1939 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1941 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1942 struct si_texture_handle
*, tex_handle
) {
1943 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1946 util_dynarray_foreach(&sctx
->resident_img_handles
,
1947 struct si_image_handle
*, img_handle
) {
1948 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1951 si_upload_bindless_descriptors(sctx
);
1954 /* Update mutable image descriptor fields of all bound textures. */
1955 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1959 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1960 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1961 struct si_images
*images
= &sctx
->images
[shader
];
1965 mask
= images
->enabled_mask
;
1967 unsigned i
= u_bit_scan(&mask
);
1968 struct pipe_image_view
*view
= &images
->views
[i
];
1970 if (!view
->resource
||
1971 view
->resource
->target
== PIPE_BUFFER
)
1974 si_set_shader_image(sctx
, shader
, i
, view
, true);
1977 /* Sampler views. */
1978 mask
= samplers
->enabled_mask
;
1980 unsigned i
= u_bit_scan(&mask
);
1981 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1985 view
->texture
->target
== PIPE_BUFFER
)
1988 si_set_sampler_view(sctx
, shader
, i
,
1989 samplers
->views
[i
], true);
1992 si_update_shader_needs_decompress_mask(sctx
, shader
);
1995 si_update_all_resident_texture_descriptors(sctx
);
1996 si_update_ps_colorbuf0_slot(sctx
);
1999 /* SHADER USER DATA */
2001 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2004 sctx
->shader_pointers_dirty
|=
2005 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2006 SI_NUM_SHADER_DESCS
);
2008 if (shader
== PIPE_SHADER_VERTEX
)
2009 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2011 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
2014 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2016 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2017 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2018 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
2019 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2020 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2023 /* Set a base register address for user data constants in the given shader.
2024 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2026 static void si_set_user_data_base(struct si_context
*sctx
,
2027 unsigned shader
, uint32_t new_base
)
2029 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2031 if (*base
!= new_base
) {
2035 si_mark_shader_pointers_dirty(sctx
, shader
);
2037 if (shader
== PIPE_SHADER_VERTEX
)
2038 sctx
->last_vs_state
= ~0;
2043 /* This must be called when these shaders are changed from non-NULL to NULL
2046 * - tessellation control shader
2047 * - tessellation evaluation shader
2049 void si_shader_change_notify(struct si_context
*sctx
)
2051 /* VS can be bound as VS, ES, or LS. */
2052 if (sctx
->tes_shader
.cso
) {
2053 if (sctx
->b
.chip_class
>= GFX9
) {
2054 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2055 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2057 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2058 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2060 } else if (sctx
->gs_shader
.cso
) {
2061 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2062 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2064 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2065 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2068 /* TES can be bound as ES, VS, or not bound. */
2069 if (sctx
->tes_shader
.cso
) {
2070 if (sctx
->gs_shader
.cso
)
2071 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2072 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2074 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2075 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2077 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2081 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2083 unsigned pointer_count
)
2085 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2086 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2089 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2090 struct radeon_winsys_cs
*cs
,
2093 radeon_emit(cs
, va
);
2095 if (HAVE_32BIT_POINTERS
)
2096 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2098 radeon_emit(cs
, va
>> 32);
2101 static void si_emit_shader_pointer(struct si_context
*sctx
,
2102 struct si_descriptors
*desc
,
2105 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2106 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2108 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2109 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2112 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2113 unsigned pointer_mask
,
2119 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2120 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2124 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2126 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2127 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2129 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2130 for (int i
= 0; i
< count
; i
++)
2131 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2132 descs
[i
].gpu_address
);
2136 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2137 unsigned pointer_mask
,
2143 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2144 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2147 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2148 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2150 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2151 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
->gpu_address
);
2155 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2156 struct si_descriptors
*descs
)
2158 if (sctx
->b
.chip_class
== GFX9
) {
2159 /* Broadcast it to all shader stages. */
2160 si_emit_shader_pointer(sctx
, descs
,
2161 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2165 si_emit_shader_pointer(sctx
, descs
,
2166 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2167 si_emit_shader_pointer(sctx
, descs
,
2168 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2169 si_emit_shader_pointer(sctx
, descs
,
2170 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2171 si_emit_shader_pointer(sctx
, descs
,
2172 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2173 si_emit_shader_pointer(sctx
, descs
,
2174 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2175 si_emit_shader_pointer(sctx
, descs
,
2176 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2179 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2180 struct r600_atom
*atom
)
2182 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2184 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2185 si_emit_global_shader_pointers(sctx
,
2186 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2189 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2190 sh_base
[PIPE_SHADER_VERTEX
]);
2191 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2192 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2193 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2194 sh_base
[PIPE_SHADER_FRAGMENT
]);
2195 if (HAVE_32BIT_POINTERS
|| sctx
->b
.chip_class
<= VI
) {
2196 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2197 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2198 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2199 sh_base
[PIPE_SHADER_GEOMETRY
]);
2201 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2202 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2203 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2204 sh_base
[PIPE_SHADER_GEOMETRY
]);
2207 sctx
->shader_pointers_dirty
&=
2208 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2210 if (sctx
->vertex_buffer_pointer_dirty
) {
2211 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2213 /* Find the location of the VB descriptor pointer. */
2214 /* TODO: In the future, the pointer will be packed in unused
2215 * bits of the first 2 VB descriptors. */
2216 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2217 if (sctx
->b
.chip_class
>= GFX9
) {
2218 if (sctx
->tes_shader
.cso
)
2219 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2220 else if (sctx
->gs_shader
.cso
)
2221 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2224 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2225 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2226 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2227 sctx
->vb_descriptors_buffer
->gpu_address
+
2228 sctx
->vb_descriptors_offset
);
2229 sctx
->vertex_buffer_pointer_dirty
= false;
2232 if (sctx
->graphics_bindless_pointer_dirty
) {
2233 si_emit_global_shader_pointers(sctx
,
2234 &sctx
->bindless_descriptors
);
2235 sctx
->graphics_bindless_pointer_dirty
= false;
2239 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2241 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2243 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2244 R_00B900_COMPUTE_USER_DATA_0
);
2245 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2247 if (sctx
->compute_bindless_pointer_dirty
) {
2248 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2249 sctx
->compute_bindless_pointer_dirty
= false;
2255 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2256 struct si_descriptors
*desc
,
2257 short shader_userdata_rel_index
,
2258 unsigned num_elements
)
2260 MAYBE_UNUSED
unsigned desc_slot
;
2262 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2263 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2265 /* The first bindless descriptor is stored at slot 1, because 0 is not
2266 * considered to be a valid handle.
2268 sctx
->num_bindless_descriptors
= 1;
2270 /* Track which bindless slots are used (or not). */
2271 util_idalloc_init(&sctx
->bindless_used_slots
);
2272 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2274 /* Reserve slot 0 because it's an invalid handle for bindless. */
2275 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2276 assert(desc_slot
== 0);
2279 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2281 si_release_descriptors(&sctx
->bindless_descriptors
);
2282 util_idalloc_fini(&sctx
->bindless_used_slots
);
2285 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2287 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2290 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2291 if (desc_slot
>= desc
->num_elements
) {
2292 /* The array of bindless descriptors is full, resize it. */
2293 unsigned slot_size
= desc
->element_dw_size
* 4;
2294 unsigned new_num_elements
= desc
->num_elements
* 2;
2296 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2297 new_num_elements
* slot_size
);
2298 desc
->num_elements
= new_num_elements
;
2299 desc
->num_active_slots
= new_num_elements
;
2307 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2310 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2311 unsigned desc_slot
, desc_slot_offset
;
2313 /* Find a free slot. */
2314 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2316 /* For simplicity, sampler and image bindless descriptors use fixed
2317 * 16-dword slots for now. Image descriptors only need 8-dword but this
2318 * doesn't really matter because no real apps use image handles.
2320 desc_slot_offset
= desc_slot
* 16;
2322 /* Copy the descriptor into the array. */
2323 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2325 /* Re-upload the whole array of bindless descriptors into a new buffer.
2327 if (!si_upload_descriptors(sctx
, desc
))
2330 /* Make sure to re-emit the shader pointers for all stages. */
2331 sctx
->graphics_bindless_pointer_dirty
= true;
2332 sctx
->compute_bindless_pointer_dirty
= true;
2337 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2339 struct pipe_resource
*resource
,
2343 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2344 struct r600_resource
*buf
= r600_resource(resource
);
2345 unsigned desc_slot_offset
= desc_slot
* 16;
2346 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2347 uint64_t old_desc_va
;
2349 assert(resource
->target
== PIPE_BUFFER
);
2351 /* Retrieve the old buffer addr from the descriptor. */
2352 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2354 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2355 /* The buffer has been invalidated when the handle wasn't
2356 * resident, update the descriptor and the dirty flag.
2358 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2364 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2365 struct pipe_sampler_view
*view
,
2366 const struct pipe_sampler_state
*state
)
2368 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2369 struct si_context
*sctx
= (struct si_context
*)ctx
;
2370 struct si_texture_handle
*tex_handle
;
2371 struct si_sampler_state
*sstate
;
2372 uint32_t desc_list
[16];
2375 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2379 memset(desc_list
, 0, sizeof(desc_list
));
2380 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2382 sstate
= ctx
->create_sampler_state(ctx
, state
);
2388 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2389 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2390 ctx
->delete_sampler_state(ctx
, sstate
);
2392 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2394 if (!tex_handle
->desc_slot
) {
2399 handle
= tex_handle
->desc_slot
;
2401 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2402 (void *)(uintptr_t)handle
,
2408 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2410 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2415 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2417 struct si_context
*sctx
= (struct si_context
*)ctx
;
2418 struct si_texture_handle
*tex_handle
;
2419 struct hash_entry
*entry
;
2421 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2422 (void *)(uintptr_t)handle
);
2426 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2428 /* Allow this descriptor slot to be re-used. */
2429 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2431 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2432 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2436 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2437 uint64_t handle
, bool resident
)
2439 struct si_context
*sctx
= (struct si_context
*)ctx
;
2440 struct si_texture_handle
*tex_handle
;
2441 struct si_sampler_view
*sview
;
2442 struct hash_entry
*entry
;
2444 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2445 (void *)(uintptr_t)handle
);
2449 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2450 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2453 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2454 struct r600_texture
*rtex
=
2455 (struct r600_texture
*)sview
->base
.texture
;
2457 if (depth_needs_decompression(rtex
)) {
2458 util_dynarray_append(
2459 &sctx
->resident_tex_needs_depth_decompress
,
2460 struct si_texture_handle
*,
2464 if (color_needs_decompression(rtex
)) {
2465 util_dynarray_append(
2466 &sctx
->resident_tex_needs_color_decompress
,
2467 struct si_texture_handle
*,
2471 if (rtex
->dcc_offset
&&
2472 p_atomic_read(&rtex
->framebuffers_bound
))
2473 sctx
->need_check_render_feedback
= true;
2475 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2477 si_update_bindless_buffer_descriptor(sctx
,
2478 tex_handle
->desc_slot
,
2479 sview
->base
.texture
,
2480 sview
->base
.u
.buf
.offset
,
2481 &tex_handle
->desc_dirty
);
2484 /* Re-upload the descriptor if it has been updated while it
2487 if (tex_handle
->desc_dirty
)
2488 sctx
->bindless_descriptors_dirty
= true;
2490 /* Add the texture handle to the per-context list. */
2491 util_dynarray_append(&sctx
->resident_tex_handles
,
2492 struct si_texture_handle
*, tex_handle
);
2494 /* Add the buffers to the current CS in case si_begin_new_cs()
2495 * is not going to be called.
2497 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2499 sview
->is_stencil_sampler
, false);
2501 /* Remove the texture handle from the per-context list. */
2502 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2503 struct si_texture_handle
*,
2506 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2507 util_dynarray_delete_unordered(
2508 &sctx
->resident_tex_needs_depth_decompress
,
2509 struct si_texture_handle
*, tex_handle
);
2511 util_dynarray_delete_unordered(
2512 &sctx
->resident_tex_needs_color_decompress
,
2513 struct si_texture_handle
*, tex_handle
);
2518 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2519 const struct pipe_image_view
*view
)
2521 struct si_context
*sctx
= (struct si_context
*)ctx
;
2522 struct si_image_handle
*img_handle
;
2523 uint32_t desc_list
[8];
2526 if (!view
|| !view
->resource
)
2529 img_handle
= CALLOC_STRUCT(si_image_handle
);
2533 memset(desc_list
, 0, sizeof(desc_list
));
2534 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2536 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2538 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2540 if (!img_handle
->desc_slot
) {
2545 handle
= img_handle
->desc_slot
;
2547 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2548 (void *)(uintptr_t)handle
,
2554 util_copy_image_view(&img_handle
->view
, view
);
2556 r600_resource(view
->resource
)->image_handle_allocated
= true;
2561 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2563 struct si_context
*sctx
= (struct si_context
*)ctx
;
2564 struct si_image_handle
*img_handle
;
2565 struct hash_entry
*entry
;
2567 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2568 (void *)(uintptr_t)handle
);
2572 img_handle
= (struct si_image_handle
*)entry
->data
;
2574 util_copy_image_view(&img_handle
->view
, NULL
);
2575 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2579 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2580 uint64_t handle
, unsigned access
,
2583 struct si_context
*sctx
= (struct si_context
*)ctx
;
2584 struct si_image_handle
*img_handle
;
2585 struct pipe_image_view
*view
;
2586 struct r600_resource
*res
;
2587 struct hash_entry
*entry
;
2589 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2590 (void *)(uintptr_t)handle
);
2594 img_handle
= (struct si_image_handle
*)entry
->data
;
2595 view
= &img_handle
->view
;
2596 res
= (struct r600_resource
*)view
->resource
;
2599 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2600 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2601 unsigned level
= view
->u
.tex
.level
;
2603 if (color_needs_decompression(rtex
)) {
2604 util_dynarray_append(
2605 &sctx
->resident_img_needs_color_decompress
,
2606 struct si_image_handle
*,
2610 if (vi_dcc_enabled(rtex
, level
) &&
2611 p_atomic_read(&rtex
->framebuffers_bound
))
2612 sctx
->need_check_render_feedback
= true;
2614 si_update_bindless_image_descriptor(sctx
, img_handle
);
2616 si_update_bindless_buffer_descriptor(sctx
,
2617 img_handle
->desc_slot
,
2620 &img_handle
->desc_dirty
);
2623 /* Re-upload the descriptor if it has been updated while it
2626 if (img_handle
->desc_dirty
)
2627 sctx
->bindless_descriptors_dirty
= true;
2629 /* Add the image handle to the per-context list. */
2630 util_dynarray_append(&sctx
->resident_img_handles
,
2631 struct si_image_handle
*, img_handle
);
2633 /* Add the buffers to the current CS in case si_begin_new_cs()
2634 * is not going to be called.
2636 si_sampler_view_add_buffer(sctx
, view
->resource
,
2637 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2638 RADEON_USAGE_READWRITE
:
2639 RADEON_USAGE_READ
, false, false);
2641 /* Remove the image handle from the per-context list. */
2642 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2643 struct si_image_handle
*,
2646 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2647 util_dynarray_delete_unordered(
2648 &sctx
->resident_img_needs_color_decompress
,
2649 struct si_image_handle
*,
2656 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2658 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2660 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2661 sizeof(struct si_texture_handle
*);
2662 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2663 sizeof(struct si_image_handle
*);
2665 /* Add all resident texture handles. */
2666 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2667 struct si_texture_handle
*, tex_handle
) {
2668 struct si_sampler_view
*sview
=
2669 (struct si_sampler_view
*)(*tex_handle
)->view
;
2671 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2673 sview
->is_stencil_sampler
, false);
2676 /* Add all resident image handles. */
2677 util_dynarray_foreach(&sctx
->resident_img_handles
,
2678 struct si_image_handle
*, img_handle
) {
2679 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2681 si_sampler_view_add_buffer(sctx
, view
->resource
,
2682 RADEON_USAGE_READWRITE
,
2686 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2687 num_resident_img_handles
;
2690 /* INIT/DEINIT/UPLOAD */
2692 void si_init_all_descriptors(struct si_context
*sctx
)
2696 #if !HAVE_32BIT_POINTERS
2697 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2700 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2701 bool is_2nd
= sctx
->b
.chip_class
>= GFX9
&&
2702 (i
== PIPE_SHADER_TESS_CTRL
||
2703 i
== PIPE_SHADER_GEOMETRY
);
2704 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2705 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2707 struct si_descriptors
*desc
;
2710 if (i
== PIPE_SHADER_TESS_CTRL
) {
2711 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2712 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2713 } else { /* PIPE_SHADER_GEOMETRY */
2714 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2715 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2718 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2720 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2721 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2722 num_buffer_slots
, rel_dw_offset
,
2723 RADEON_USAGE_READWRITE
,
2725 RADEON_PRIO_SHADER_RW_BUFFER
,
2726 RADEON_PRIO_CONST_BUFFER
);
2727 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2730 #if HAVE_32BIT_POINTERS
2731 if (i
== PIPE_SHADER_TESS_CTRL
) {
2732 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2733 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2734 } else { /* PIPE_SHADER_GEOMETRY */
2735 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2736 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2739 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2742 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2745 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2746 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2749 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2750 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2751 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2752 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2755 si_init_buffer_resources(&sctx
->rw_buffers
,
2756 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2757 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2758 /* The second set of usage/priority is used by
2759 * const buffers in RW buffer slots. */
2760 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2761 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2762 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2764 /* Initialize an array of 1024 bindless descriptors, when the limit is
2765 * reached, just make it larger and re-upload the whole array.
2767 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2768 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2771 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2773 /* Set pipe_context functions. */
2774 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2775 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2776 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2777 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2778 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2779 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2780 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2781 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2782 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2783 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2784 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2785 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2786 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2787 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2789 /* Shader user data. */
2790 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2791 si_emit_graphics_shader_pointers
);
2793 /* Set default and immutable mappings. */
2794 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2796 if (sctx
->b
.chip_class
>= GFX9
) {
2797 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2798 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2799 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2800 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2802 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2803 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2804 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2805 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2807 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2810 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2812 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2814 /* Assume nothing will go wrong: */
2815 sctx
->shader_pointers_dirty
|= dirty
;
2818 unsigned i
= u_bit_scan(&dirty
);
2820 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2824 sctx
->descriptors_dirty
&= ~mask
;
2826 si_upload_bindless_descriptors(sctx
);
2831 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2833 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2834 return si_upload_shader_descriptors(sctx
, mask
);
2837 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2839 /* Does not update rw_buffers as that is not needed for compute shaders
2840 * and the input buffer is using the same SGPR's anyway.
2842 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2843 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2844 return si_upload_shader_descriptors(sctx
, mask
);
2847 void si_release_all_descriptors(struct si_context
*sctx
)
2851 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2852 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2853 si_const_and_shader_buffer_descriptors(sctx
, i
));
2854 si_release_sampler_views(&sctx
->samplers
[i
]);
2855 si_release_image_views(&sctx
->images
[i
]);
2857 si_release_buffer_resources(&sctx
->rw_buffers
,
2858 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2859 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2860 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2862 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2863 si_release_descriptors(&sctx
->descriptors
[i
]);
2865 r600_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2866 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2868 si_release_bindless_descriptors(sctx
);
2871 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2875 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2876 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2877 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2878 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2880 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2881 si_vertex_buffers_begin_new_cs(sctx
);
2883 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2884 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2885 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2887 si_shader_pointers_begin_new_cs(sctx
);
2890 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2891 uint64_t new_active_mask
)
2893 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2895 /* Ignore no-op updates and updates that disable all slots. */
2896 if (!new_active_mask
||
2897 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2898 desc
->num_active_slots
))
2902 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2903 assert(new_active_mask
== 0);
2905 /* Upload/dump descriptors if slots are being enabled. */
2906 if (first
< desc
->first_active_slot
||
2907 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2908 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2910 desc
->first_active_slot
= first
;
2911 desc
->num_active_slots
= count
;
2914 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2915 struct si_shader_selector
*sel
)
2920 si_set_active_descriptors(sctx
,
2921 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2922 sel
->active_const_and_shader_buffers
);
2923 si_set_active_descriptors(sctx
,
2924 si_sampler_and_image_descriptors_idx(sel
->type
),
2925 sel
->active_samplers_and_images
);