2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
58 #include "util/format/u_format.h"
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/u_memory.h"
62 #include "util/u_upload_mgr.h"
64 /* NULL image and buffer descriptor for textures (alpha = 1) and images
67 * For images, all fields must be zero except for the swizzle, which
68 * supports arbitrary combinations of 0s and 1s. The texture type must be
69 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
71 * For buffers, all fields must be zero. If they are not, the hw hangs.
73 * This is the only reason why the buffer descriptor must be in words [4:7].
75 static uint32_t null_texture_descriptor
[8] = {
76 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
77 /* the rest must contain zeros, which is also used by the buffer
81 static uint32_t null_image_descriptor
[8] = {
82 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
89 uint64_t va
= desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
91 /* Sign-extend the 48-bit address. */
93 va
= (int64_t)va
>> 16;
97 static void si_init_descriptor_list(uint32_t *desc_list
, unsigned element_dw_size
,
98 unsigned num_elements
, const uint32_t *null_descriptor
)
102 /* Initialize the array to NULL descriptors if the element size is 8. */
103 if (null_descriptor
) {
104 assert(element_dw_size
% 8 == 0);
105 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
106 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
110 static void si_init_descriptors(struct si_descriptors
*desc
, short shader_userdata_rel_index
,
111 unsigned element_dw_size
, unsigned num_elements
)
113 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
114 desc
->element_dw_size
= element_dw_size
;
115 desc
->num_elements
= num_elements
;
116 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
117 desc
->slot_index_to_bind_directly
= -1;
120 static void si_release_descriptors(struct si_descriptors
*desc
)
122 si_resource_reference(&desc
->buffer
, NULL
);
126 static bool si_upload_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
)
128 unsigned slot_size
= desc
->element_dw_size
* 4;
129 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
130 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
132 /* Skip the upload if no shader is using the descriptors. dirty_mask
133 * will stay dirty and the descriptors will be uploaded when there is
134 * a shader using them.
139 /* If there is just one active descriptor, bind it directly. */
140 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
141 desc
->num_active_slots
== 1) {
142 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
* desc
->element_dw_size
];
144 /* The buffer is already in the buffer list. */
145 si_resource_reference(&desc
->buffer
, NULL
);
146 desc
->gpu_list
= NULL
;
147 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
148 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
153 unsigned buffer_offset
;
154 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
155 si_optimal_tcc_alignment(sctx
, upload_size
), &buffer_offset
,
156 (struct pipe_resource
**)&desc
->buffer
, (void **)&ptr
);
158 desc
->gpu_address
= 0;
159 return false; /* skip the draw call */
162 util_memcpy_cpu_to_le32(ptr
, (char *)desc
->list
+ first_slot_offset
, upload_size
);
163 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
165 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
166 RADEON_PRIO_DESCRIPTORS
);
168 /* The shader pointer should point to slot 0. */
169 buffer_offset
-= first_slot_offset
;
170 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
172 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
173 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
174 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
176 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
180 static void si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
185 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
186 RADEON_PRIO_DESCRIPTORS
);
191 static inline enum radeon_bo_priority
si_get_sampler_view_priority(struct si_resource
*res
)
193 if (res
->b
.b
.target
== PIPE_BUFFER
)
194 return RADEON_PRIO_SAMPLER_BUFFER
;
196 if (res
->b
.b
.nr_samples
> 1)
197 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
199 return RADEON_PRIO_SAMPLER_TEXTURE
;
202 static struct si_descriptors
*si_sampler_and_image_descriptors(struct si_context
*sctx
,
205 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
208 static void si_release_sampler_views(struct si_samplers
*samplers
)
212 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
213 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
217 static void si_sampler_view_add_buffer(struct si_context
*sctx
, struct pipe_resource
*resource
,
218 enum radeon_bo_usage usage
, bool is_stencil_sampler
,
221 struct si_texture
*tex
= (struct si_texture
*)resource
;
222 enum radeon_bo_priority priority
;
227 /* Use the flushed depth texture if direct sampling is unsupported. */
228 if (resource
->target
!= PIPE_BUFFER
&& tex
->is_depth
&&
229 !si_can_sample_zs(tex
, is_stencil_sampler
))
230 tex
= tex
->flushed_depth_texture
;
232 priority
= si_get_sampler_view_priority(&tex
->buffer
);
233 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
, check_mem
);
235 if (resource
->target
== PIPE_BUFFER
)
238 /* Add separate DCC. */
239 if (tex
->dcc_separate_buffer
) {
240 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
, usage
,
241 RADEON_PRIO_SEPARATE_META
, check_mem
);
245 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
, struct si_samplers
*samplers
)
247 unsigned mask
= samplers
->enabled_mask
;
249 /* Add buffers to the CS. */
251 int i
= u_bit_scan(&mask
);
252 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
254 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
255 sview
->is_stencil_sampler
, false);
259 /* Set buffer descriptor fields that can be changed by reallocations. */
260 static void si_set_buf_desc_address(struct si_resource
*buf
, uint64_t offset
, uint32_t *state
)
262 uint64_t va
= buf
->gpu_address
+ offset
;
265 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
266 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
269 /* Set texture descriptor fields that can be changed by reallocations.
272 * \param base_level_info information of the level of BASE_ADDRESS
273 * \param base_level the level of BASE_ADDRESS
274 * \param first_level pipe_sampler_view.u.tex.first_level
275 * \param block_width util_format_get_blockwidth()
276 * \param is_stencil select between separate Z & Stencil
277 * \param state descriptor to update
279 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
, struct si_texture
*tex
,
280 const struct legacy_surf_level
*base_level_info
,
281 unsigned base_level
, unsigned first_level
, unsigned block_width
,
282 bool is_stencil
, bool force_dcc_off
, uint32_t *state
)
284 uint64_t va
, meta_va
= 0;
286 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
287 tex
= tex
->flushed_depth_texture
;
291 va
= tex
->buffer
.gpu_address
;
293 if (sscreen
->info
.chip_class
>= GFX9
) {
294 /* Only stencil_offset needs to be added here. */
296 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
298 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
300 va
+= base_level_info
->offset
;
304 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
305 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
307 /* Only macrotiled modes can set tile swizzle.
308 * GFX9 doesn't use (legacy) base_level_info.
310 if (sscreen
->info
.chip_class
>= GFX9
|| base_level_info
->mode
== RADEON_SURF_MODE_2D
)
311 state
[0] |= tex
->surface
.tile_swizzle
;
313 if (sscreen
->info
.chip_class
>= GFX8
) {
314 state
[6] &= C_008F28_COMPRESSION_EN
;
316 if (!force_dcc_off
&& vi_dcc_enabled(tex
, first_level
)) {
318 (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
;
320 if (sscreen
->info
.chip_class
== GFX8
) {
321 meta_va
+= base_level_info
->dcc_offset
;
322 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
325 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
326 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
327 meta_va
|= dcc_tile_swizzle
;
328 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
329 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
330 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
334 state
[6] |= S_008F28_COMPRESSION_EN(1);
337 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
338 state
[7] = meta_va
>> 8;
340 if (sscreen
->info
.chip_class
>= GFX10
) {
341 state
[3] &= C_00A00C_SW_MODE
;
344 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
346 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
349 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
& C_00A018_META_PIPE_ALIGNED
;
352 struct gfx9_surf_meta_flags meta
= {
357 if (tex
->surface
.dcc_offset
)
358 meta
= tex
->surface
.u
.gfx9
.dcc
;
360 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
361 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
364 state
[7] = meta_va
>> 16;
365 } else if (sscreen
->info
.chip_class
== GFX9
) {
366 state
[3] &= C_008F1C_SW_MODE
;
367 state
[4] &= C_008F20_PITCH
;
370 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
371 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
373 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
374 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
378 C_008F24_META_DATA_ADDRESS
& C_008F24_META_PIPE_ALIGNED
& C_008F24_META_RB_ALIGNED
;
380 struct gfx9_surf_meta_flags meta
= {
385 if (tex
->surface
.dcc_offset
)
386 meta
= tex
->surface
.u
.gfx9
.dcc
;
388 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
389 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
390 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
394 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
395 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
397 state
[3] &= C_008F1C_TILING_INDEX
;
398 state
[3] |= S_008F1C_TILING_INDEX(index
);
399 state
[4] &= C_008F20_PITCH
;
400 state
[4] |= S_008F20_PITCH(pitch
- 1);
404 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
405 struct si_sampler_view
*sview
, struct si_texture
*tex
,
408 if (sview
&& sview
->is_integer
)
409 memcpy(desc
, sstate
->integer_val
, 4 * 4);
410 else if (tex
&& tex
->upgraded_depth
&& (!sview
|| !sview
->is_stencil_sampler
))
411 memcpy(desc
, sstate
->upgraded_depth_val
, 4 * 4);
413 memcpy(desc
, sstate
->val
, 4 * 4);
416 static void si_set_sampler_view_desc(struct si_context
*sctx
, struct si_sampler_view
*sview
,
417 struct si_sampler_state
*sstate
, uint32_t *desc
)
419 struct pipe_sampler_view
*view
= &sview
->base
;
420 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
421 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
423 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
424 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
425 if (!si_texture_disable_dcc(sctx
, tex
))
426 si_decompress_dcc(sctx
, tex
);
428 sview
->dcc_incompatible
= false;
431 assert(tex
); /* views with texture == NULL aren't supported */
432 memcpy(desc
, sview
->state
, 8 * 4);
435 si_set_buf_desc_address(&tex
->buffer
, sview
->base
.u
.buf
.offset
, desc
+ 4);
437 bool is_separate_stencil
= tex
->db_compatible
&& sview
->is_stencil_sampler
;
439 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
, sview
->base_level_info
, sview
->base_level
,
440 sview
->base
.u
.tex
.first_level
, sview
->block_width
,
441 is_separate_stencil
, false, desc
);
444 if (!is_buffer
&& tex
->surface
.fmask_size
) {
445 memcpy(desc
+ 8, sview
->fmask_state
, 8 * 4);
447 /* Disable FMASK and bind sampler state in [12:15]. */
448 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
451 si_set_sampler_state_desc(sstate
, sview
, is_buffer
? NULL
: tex
, desc
+ 12);
455 static bool color_needs_decompression(struct si_texture
*tex
)
457 return tex
->surface
.fmask_size
||
458 (tex
->dirty_level_mask
&& (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
461 static bool depth_needs_decompression(struct si_texture
*tex
)
463 /* If the depth/stencil texture is TC-compatible, no decompression
464 * will be done. The decompression function will only flush DB caches
465 * to make it coherent with shaders. That's necessary because the driver
466 * doesn't flush DB caches in any other case.
468 return tex
->db_compatible
;
471 static void si_set_sampler_view(struct si_context
*sctx
, unsigned shader
, unsigned slot
,
472 struct pipe_sampler_view
*view
, bool disallow_early_out
)
474 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
475 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
476 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
477 unsigned desc_slot
= si_get_sampler_slot(slot
);
478 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
480 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
484 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
486 si_set_sampler_view_desc(sctx
, sview
, samplers
->sampler_states
[slot
], desc
);
488 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
489 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
490 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
491 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
493 if (depth_needs_decompression(tex
)) {
494 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
496 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
498 if (color_needs_decompression(tex
)) {
499 samplers
->needs_color_decompress_mask
|= 1u << slot
;
501 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
504 if (tex
->surface
.dcc_offset
&& p_atomic_read(&tex
->framebuffers_bound
))
505 sctx
->need_check_render_feedback
= true;
508 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
509 samplers
->enabled_mask
|= 1u << slot
;
511 /* Since this can flush, it must be done after enabled_mask is
513 si_sampler_view_add_buffer(sctx
, view
->texture
, RADEON_USAGE_READ
, sview
->is_stencil_sampler
,
516 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
517 memcpy(desc
, null_texture_descriptor
, 8 * 4);
518 /* Only clear the lower dwords of FMASK. */
519 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
520 /* Re-set the sampler state if we are transitioning from FMASK. */
521 if (samplers
->sampler_states
[slot
])
522 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
, desc
+ 12);
524 samplers
->enabled_mask
&= ~(1u << slot
);
525 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
526 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
529 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
532 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
, unsigned shader
)
534 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
535 unsigned shader_bit
= 1 << shader
;
537 if (samplers
->needs_depth_decompress_mask
|| samplers
->needs_color_decompress_mask
||
538 sctx
->images
[shader
].needs_color_decompress_mask
)
539 sctx
->shader_needs_decompress_mask
|= shader_bit
;
541 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
544 static void si_set_sampler_views(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
545 unsigned start
, unsigned count
, struct pipe_sampler_view
**views
)
547 struct si_context
*sctx
= (struct si_context
*)ctx
;
550 if (!count
|| shader
>= SI_NUM_SHADERS
)
554 for (i
= 0; i
< count
; i
++)
555 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
557 for (i
= 0; i
< count
; i
++)
558 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
561 si_update_shader_needs_decompress_mask(sctx
, shader
);
564 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
566 unsigned mask
= samplers
->enabled_mask
;
569 int i
= u_bit_scan(&mask
);
570 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
572 if (res
&& res
->target
!= PIPE_BUFFER
) {
573 struct si_texture
*tex
= (struct si_texture
*)res
;
575 if (color_needs_decompression(tex
)) {
576 samplers
->needs_color_decompress_mask
|= 1u << i
;
578 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
586 static void si_release_image_views(struct si_images
*images
)
590 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
591 struct pipe_image_view
*view
= &images
->views
[i
];
593 pipe_resource_reference(&view
->resource
, NULL
);
597 static void si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
599 uint mask
= images
->enabled_mask
;
601 /* Add buffers to the CS. */
603 int i
= u_bit_scan(&mask
);
604 struct pipe_image_view
*view
= &images
->views
[i
];
606 assert(view
->resource
);
608 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
612 static void si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
614 struct si_images
*images
= &ctx
->images
[shader
];
616 if (images
->enabled_mask
& (1u << slot
)) {
617 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
618 unsigned desc_slot
= si_get_image_slot(slot
);
620 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
621 images
->needs_color_decompress_mask
&= ~(1 << slot
);
623 memcpy(descs
->list
+ desc_slot
* 8, null_image_descriptor
, 8 * 4);
624 images
->enabled_mask
&= ~(1u << slot
);
625 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
629 static void si_mark_image_range_valid(const struct pipe_image_view
*view
)
631 struct si_resource
*res
= si_resource(view
->resource
);
633 if (res
->b
.b
.target
!= PIPE_BUFFER
)
636 util_range_add(&res
->b
.b
, &res
->valid_buffer_range
, view
->u
.buf
.offset
,
637 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
640 static void si_set_shader_image_desc(struct si_context
*ctx
, const struct pipe_image_view
*view
,
641 bool skip_decompress
, uint32_t *desc
, uint32_t *fmask_desc
)
643 struct si_screen
*screen
= ctx
->screen
;
644 struct si_resource
*res
;
646 res
= si_resource(view
->resource
);
648 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
649 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
650 si_mark_image_range_valid(view
);
652 si_make_buffer_descriptor(screen
, res
, view
->format
, view
->u
.buf
.offset
, view
->u
.buf
.size
,
654 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
656 static const unsigned char swizzle
[4] = {0, 1, 2, 3};
657 struct si_texture
*tex
= (struct si_texture
*)res
;
658 unsigned level
= view
->u
.tex
.level
;
659 unsigned width
, height
, depth
, hw_level
;
660 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
661 unsigned access
= view
->access
;
663 assert(!tex
->is_depth
);
664 assert(fmask_desc
|| tex
->surface
.fmask_offset
== 0);
666 if (uses_dcc
&& !skip_decompress
&&
667 !(access
& SI_IMAGE_ACCESS_DCC_OFF
) &&
668 (access
& PIPE_IMAGE_ACCESS_WRITE
||
669 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
670 /* If DCC can't be disabled, at least decompress it.
671 * The decompression is relatively cheap if the surface
672 * has been decompressed already.
674 if (!si_texture_disable_dcc(ctx
, tex
))
675 si_decompress_dcc(ctx
, tex
);
678 if (ctx
->chip_class
>= GFX9
) {
679 /* Always set the base address. The swizzle modes don't
680 * allow setting mipmap level offsets as the base.
682 width
= res
->b
.b
.width0
;
683 height
= res
->b
.b
.height0
;
684 depth
= res
->b
.b
.depth0
;
687 /* Always force the base level to the selected level.
689 * This is required for 3D textures, where otherwise
690 * selecting a single slice for non-layered bindings
691 * fails. It doesn't hurt the other targets.
693 width
= u_minify(res
->b
.b
.width0
, level
);
694 height
= u_minify(res
->b
.b
.height0
, level
);
695 depth
= u_minify(res
->b
.b
.depth0
, level
);
699 screen
->make_texture_descriptor(
700 screen
, tex
, false, res
->b
.b
.target
, view
->format
, swizzle
, hw_level
, hw_level
,
701 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
, width
, height
, depth
, desc
, fmask_desc
);
702 si_set_mutable_tex_desc_fields(screen
, tex
, &tex
->surface
.u
.legacy
.level
[level
], level
, level
,
703 util_format_get_blockwidth(view
->format
), false,
704 view
->access
& SI_IMAGE_ACCESS_DCC_OFF
, desc
);
708 static void si_set_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
,
709 const struct pipe_image_view
*view
, bool skip_decompress
)
711 struct si_images
*images
= &ctx
->images
[shader
];
712 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
713 struct si_resource
*res
;
715 if (!view
|| !view
->resource
) {
716 si_disable_shader_image(ctx
, shader
, slot
);
720 res
= si_resource(view
->resource
);
722 si_set_shader_image_desc(ctx
, view
, skip_decompress
, descs
->list
+ si_get_image_slot(slot
) * 8,
723 descs
->list
+ si_get_image_slot(slot
+ SI_NUM_IMAGES
) * 8);
725 if (&images
->views
[slot
] != view
)
726 util_copy_image_view(&images
->views
[slot
], view
);
728 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
729 images
->needs_color_decompress_mask
&= ~(1 << slot
);
730 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
732 struct si_texture
*tex
= (struct si_texture
*)res
;
733 unsigned level
= view
->u
.tex
.level
;
735 if (color_needs_decompression(tex
)) {
736 images
->needs_color_decompress_mask
|= 1 << slot
;
738 images
->needs_color_decompress_mask
&= ~(1 << slot
);
741 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
742 ctx
->need_check_render_feedback
= true;
745 images
->enabled_mask
|= 1u << slot
;
746 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
748 /* Since this can flush, it must be done after enabled_mask is updated. */
749 si_sampler_view_add_buffer(
751 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
755 static void si_set_shader_images(struct pipe_context
*pipe
, enum pipe_shader_type shader
,
756 unsigned start_slot
, unsigned count
,
757 const struct pipe_image_view
*views
)
759 struct si_context
*ctx
= (struct si_context
*)pipe
;
762 assert(shader
< SI_NUM_SHADERS
);
767 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
770 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
771 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
773 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
774 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
777 si_update_shader_needs_decompress_mask(ctx
, shader
);
780 static void si_images_update_needs_color_decompress_mask(struct si_images
*images
)
782 unsigned mask
= images
->enabled_mask
;
785 int i
= u_bit_scan(&mask
);
786 struct pipe_resource
*res
= images
->views
[i
].resource
;
788 if (res
&& res
->target
!= PIPE_BUFFER
) {
789 struct si_texture
*tex
= (struct si_texture
*)res
;
791 if (color_needs_decompression(tex
)) {
792 images
->needs_color_decompress_mask
|= 1 << i
;
794 images
->needs_color_decompress_mask
&= ~(1 << i
);
800 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
802 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
803 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
804 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
805 struct pipe_surface
*surf
= NULL
;
807 /* si_texture_disable_dcc can get us here again. */
808 if (sctx
->blitter
->running
)
811 /* See whether FBFETCH is used and color buffer 0 is set. */
812 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
813 sctx
->framebuffer
.state
.nr_cbufs
&& sctx
->framebuffer
.state
.cbufs
[0])
814 surf
= sctx
->framebuffer
.state
.cbufs
[0];
816 /* Return if FBFETCH transitions from disabled to disabled. */
817 if (!buffers
->buffers
[slot
] && !surf
)
820 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
821 si_update_ps_iter_samples(sctx
);
824 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
825 struct pipe_image_view view
= {0};
828 assert(!tex
->is_depth
);
830 /* Disable DCC, because the texture is used as both a sampler
833 si_texture_disable_dcc(sctx
, tex
);
835 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
837 assert(tex
->cmask_buffer
!= &tex
->buffer
);
838 si_eliminate_fast_color_clear(sctx
, tex
);
839 si_texture_discard_cmask(sctx
->screen
, tex
);
842 view
.resource
= surf
->texture
;
843 view
.format
= surf
->format
;
844 view
.access
= PIPE_IMAGE_ACCESS_READ
;
845 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
846 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
847 view
.u
.tex
.level
= surf
->u
.tex
.level
;
849 /* Set the descriptor. */
850 uint32_t *desc
= descs
->list
+ slot
* 4;
851 memset(desc
, 0, 16 * 4);
852 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
854 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
855 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READ
,
856 RADEON_PRIO_SHADER_RW_IMAGE
);
857 buffers
->enabled_mask
|= 1u << slot
;
859 /* Clear the descriptor. */
860 memset(descs
->list
+ slot
* 4, 0, 8 * 4);
861 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
862 buffers
->enabled_mask
&= ~(1u << slot
);
865 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
870 static void si_bind_sampler_states(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
871 unsigned start
, unsigned count
, void **states
)
873 struct si_context
*sctx
= (struct si_context
*)ctx
;
874 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
875 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
876 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
879 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
882 for (i
= 0; i
< count
; i
++) {
883 unsigned slot
= start
+ i
;
884 unsigned desc_slot
= si_get_sampler_slot(slot
);
886 if (!sstates
[i
] || sstates
[i
] == samplers
->sampler_states
[slot
])
890 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
892 samplers
->sampler_states
[slot
] = sstates
[i
];
894 /* If FMASK is bound, don't overwrite it.
895 * The sampler state will be set after FMASK is unbound.
897 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[slot
];
899 struct si_texture
*tex
= NULL
;
901 if (sview
&& sview
->base
.texture
&& sview
->base
.texture
->target
!= PIPE_BUFFER
)
902 tex
= (struct si_texture
*)sview
->base
.texture
;
904 if (tex
&& tex
->surface
.fmask_size
)
907 si_set_sampler_state_desc(sstates
[i
], sview
, tex
, desc
->list
+ desc_slot
* 16 + 12);
909 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
913 /* BUFFER RESOURCES */
915 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
916 struct si_descriptors
*descs
, unsigned num_buffers
,
917 short shader_userdata_rel_index
,
918 enum radeon_bo_priority priority
,
919 enum radeon_bo_priority priority_constbuf
)
921 buffers
->priority
= priority
;
922 buffers
->priority_constbuf
= priority_constbuf
;
923 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
924 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
926 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
929 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
930 struct si_descriptors
*descs
)
934 for (i
= 0; i
< descs
->num_elements
; i
++) {
935 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
938 FREE(buffers
->buffers
);
939 FREE(buffers
->offsets
);
942 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
943 struct si_buffer_resources
*buffers
)
945 unsigned mask
= buffers
->enabled_mask
;
947 /* Add buffers to the CS. */
949 int i
= u_bit_scan(&mask
);
951 radeon_add_to_buffer_list(
952 sctx
, sctx
->gfx_cs
, si_resource(buffers
->buffers
[i
]),
953 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
954 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
: buffers
->priority_constbuf
);
958 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
959 struct si_descriptors
*descs
, unsigned idx
,
960 struct pipe_resource
**buf
, unsigned *offset
,
963 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
965 struct si_resource
*res
= si_resource(*buf
);
966 const uint32_t *desc
= descs
->list
+ idx
* 4;
971 assert(G_008F04_STRIDE(desc
[1]) == 0);
972 va
= si_desc_extract_buffer_address(desc
);
974 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
975 *offset
= va
- res
->gpu_address
;
981 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
983 int count
= sctx
->num_vertex_elements
;
986 for (i
= 0; i
< count
; i
++) {
987 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
989 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
991 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
994 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
995 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
996 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
999 if (!sctx
->vb_descriptors_buffer
)
1001 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1002 RADEON_PRIO_DESCRIPTORS
);
1005 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1007 unsigned i
, count
= sctx
->num_vertex_elements
;
1010 if (!sctx
->vertex_buffers_dirty
|| !count
)
1013 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1014 unsigned alloc_size
= velems
->vb_desc_list_alloc_size
;
1017 /* Vertex buffer descriptors are the only ones which are uploaded
1018 * directly through a staging buffer and don't go through
1019 * the fine-grained upload path.
1021 u_upload_alloc(sctx
->b
.const_uploader
, 0, alloc_size
,
1022 si_optimal_tcc_alignment(sctx
, alloc_size
), &sctx
->vb_descriptors_offset
,
1023 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
, (void **)&ptr
);
1024 if (!sctx
->vb_descriptors_buffer
) {
1025 sctx
->vb_descriptors_offset
= 0;
1026 sctx
->vb_descriptors_gpu_list
= NULL
;
1030 sctx
->vb_descriptors_gpu_list
= ptr
;
1031 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1032 RADEON_PRIO_DESCRIPTORS
);
1033 sctx
->vertex_buffer_pointer_dirty
= true;
1034 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1036 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
1037 sctx
->vertex_buffer_pointer_dirty
= false;
1038 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VBO_DESCRIPTORS
;
1041 assert(count
<= SI_MAX_ATTRIBS
);
1043 unsigned first_vb_use_mask
= velems
->first_vb_use_mask
;
1044 unsigned num_vbos_in_user_sgprs
= sctx
->screen
->num_vbos_in_user_sgprs
;
1046 for (i
= 0; i
< count
; i
++) {
1047 struct pipe_vertex_buffer
*vb
;
1048 struct si_resource
*buf
;
1049 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1050 uint32_t *desc
= i
< num_vbos_in_user_sgprs
? &sctx
->vb_descriptor_user_sgprs
[i
* 4]
1051 : &ptr
[(i
- num_vbos_in_user_sgprs
) * 4];
1053 vb
= &sctx
->vertex_buffer
[vbo_index
];
1054 buf
= si_resource(vb
->buffer
.resource
);
1056 memset(desc
, 0, 16);
1060 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) + velems
->src_offset
[i
];
1062 if (offset
>= buf
->b
.b
.width0
) {
1063 assert(offset
< buf
->b
.b
.width0
);
1064 memset(desc
, 0, 16);
1068 uint64_t va
= buf
->gpu_address
+ offset
;
1070 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1071 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1072 /* Round up by rounding down and adding 1 */
1073 num_records
= (num_records
- velems
->format_size
[i
]) / vb
->stride
+ 1;
1075 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1077 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1079 /* OOB_SELECT chooses the out-of-bounds check:
1080 * - 1: index >= NUM_RECORDS (Structured)
1081 * - 3: offset >= NUM_RECORDS (Raw)
1083 if (sctx
->chip_class
>= GFX10
)
1084 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? V_008F0C_OOB_SELECT_STRUCTURED
1085 : V_008F0C_OOB_SELECT_RAW
);
1088 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(vb
->stride
);
1089 desc
[2] = num_records
;
1090 desc
[3] = rsrc_word3
;
1092 if (first_vb_use_mask
& (1 << i
)) {
1093 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(vb
->buffer
.resource
),
1094 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1098 /* Don't flush the const cache. It would have a very negative effect
1099 * on performance (confirmed by testing). New descriptors are always
1100 * uploaded to a fresh new buffer, so I don't think flushing the const
1101 * cache is needed. */
1102 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1103 sctx
->vertex_buffer_user_sgprs_dirty
= num_vbos_in_user_sgprs
> 0;
1104 sctx
->vertex_buffers_dirty
= false;
1108 /* CONSTANT BUFFERS */
1110 static struct si_descriptors
*si_const_and_shader_buffer_descriptors(struct si_context
*sctx
,
1113 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1116 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
, const uint8_t *ptr
,
1117 unsigned size
, uint32_t *const_offset
)
1121 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
, si_optimal_tcc_alignment(sctx
, size
),
1122 const_offset
, (struct pipe_resource
**)buf
, &tmp
);
1124 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1127 static void si_set_constant_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1128 unsigned descriptors_idx
, uint slot
,
1129 const struct pipe_constant_buffer
*input
)
1131 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1132 assert(slot
< descs
->num_elements
);
1133 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1135 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1136 * with a NULL buffer). We need to use a dummy buffer instead. */
1137 if (sctx
->chip_class
== GFX7
&& (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1138 input
= &sctx
->null_const_buf
;
1140 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1141 struct pipe_resource
*buffer
= NULL
;
1143 unsigned buffer_offset
;
1145 /* Upload the user buffer if needed. */
1146 if (input
->user_buffer
) {
1147 si_upload_const_buffer(sctx
, (struct si_resource
**)&buffer
, input
->user_buffer
,
1148 input
->buffer_size
, &buffer_offset
);
1150 /* Just unbind on failure. */
1151 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1155 pipe_resource_reference(&buffer
, input
->buffer
);
1156 buffer_offset
= input
->buffer_offset
;
1159 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1161 /* Set the descriptor. */
1162 uint32_t *desc
= descs
->list
+ slot
* 4;
1164 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1165 desc
[2] = input
->buffer_size
;
1166 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1167 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1169 if (sctx
->chip_class
>= GFX10
) {
1170 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1171 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1173 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1174 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1177 buffers
->buffers
[slot
] = buffer
;
1178 buffers
->offsets
[slot
] = buffer_offset
;
1179 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1180 buffers
->priority_constbuf
, true);
1181 buffers
->enabled_mask
|= 1u << slot
;
1183 /* Clear the descriptor. */
1184 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1185 buffers
->enabled_mask
&= ~(1u << slot
);
1188 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1191 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1192 uint slot
, const struct pipe_constant_buffer
*input
)
1194 struct si_context
*sctx
= (struct si_context
*)ctx
;
1196 if (shader
>= SI_NUM_SHADERS
)
1199 if (slot
== 0 && input
&& input
->buffer
&&
1200 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1201 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1205 if (input
&& input
->buffer
)
1206 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1208 slot
= si_get_constbuf_slot(slot
);
1209 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1210 si_const_and_shader_buffer_descriptors_idx(shader
), slot
, input
);
1213 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
, uint slot
,
1214 struct pipe_constant_buffer
*cbuf
)
1216 cbuf
->user_buffer
= NULL
;
1217 si_get_buffer_from_descriptors(
1218 &sctx
->const_and_shader_buffers
[shader
], si_const_and_shader_buffer_descriptors(sctx
, shader
),
1219 si_get_constbuf_slot(slot
), &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1222 /* SHADER BUFFERS */
1224 static void si_set_shader_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1225 unsigned descriptors_idx
, uint slot
,
1226 const struct pipe_shader_buffer
*sbuffer
, bool writable
,
1227 enum radeon_bo_priority priority
)
1229 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1230 uint32_t *desc
= descs
->list
+ slot
* 4;
1232 if (!sbuffer
|| !sbuffer
->buffer
) {
1233 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1234 memset(desc
, 0, sizeof(uint32_t) * 4);
1235 buffers
->enabled_mask
&= ~(1u << slot
);
1236 buffers
->writable_mask
&= ~(1u << slot
);
1237 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1241 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1242 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1245 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1246 desc
[2] = sbuffer
->buffer_size
;
1247 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1248 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1250 if (sctx
->chip_class
>= GFX10
) {
1251 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1252 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1254 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1258 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1259 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1260 radeon_add_to_gfx_buffer_list_check_mem(
1261 sctx
, buf
, writable
? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, priority
, true);
1263 buffers
->writable_mask
|= 1u << slot
;
1265 buffers
->writable_mask
&= ~(1u << slot
);
1267 buffers
->enabled_mask
|= 1u << slot
;
1268 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1270 util_range_add(&buf
->b
.b
, &buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1271 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1274 static void si_set_shader_buffers(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1275 unsigned start_slot
, unsigned count
,
1276 const struct pipe_shader_buffer
*sbuffers
,
1277 unsigned writable_bitmask
)
1279 struct si_context
*sctx
= (struct si_context
*)ctx
;
1280 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1281 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1284 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1286 for (i
= 0; i
< count
; ++i
) {
1287 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1288 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1290 if (sbuffer
&& sbuffer
->buffer
)
1291 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1293 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1294 !!(writable_bitmask
& (1u << i
)), buffers
->priority
);
1298 void si_get_shader_buffers(struct si_context
*sctx
, enum pipe_shader_type shader
, uint start_slot
,
1299 uint count
, struct pipe_shader_buffer
*sbuf
)
1301 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1302 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1304 for (unsigned i
= 0; i
< count
; ++i
) {
1305 si_get_buffer_from_descriptors(buffers
, descs
, si_get_shaderbuf_slot(start_slot
+ i
),
1306 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
, &sbuf
[i
].buffer_size
);
1312 void si_set_rw_buffer(struct si_context
*sctx
, uint slot
, const struct pipe_constant_buffer
*input
)
1314 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, input
);
1317 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1318 const struct pipe_shader_buffer
*sbuffer
)
1320 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, sbuffer
, true,
1321 RADEON_PRIO_SHADER_RW_BUFFER
);
1324 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
, struct pipe_resource
*buffer
,
1325 unsigned stride
, unsigned num_records
, bool add_tid
, bool swizzle
,
1326 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1328 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1329 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1331 /* The stride field in the resource descriptor has 14 bits */
1332 assert(stride
< (1 << 14));
1334 assert(slot
< descs
->num_elements
);
1335 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1340 va
= si_resource(buffer
)->gpu_address
+ offset
;
1342 switch (element_size
) {
1344 assert(!"Unsupported ring buffer element size");
1360 switch (index_stride
) {
1362 assert(!"Unsupported ring buffer index stride");
1378 if (sctx
->chip_class
>= GFX8
&& stride
)
1379 num_records
*= stride
;
1381 /* Set the descriptor. */
1382 uint32_t *desc
= descs
->list
+ slot
* 4;
1384 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
) |
1385 S_008F04_SWIZZLE_ENABLE(swizzle
);
1386 desc
[2] = num_records
;
1387 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1388 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1389 S_008F0C_INDEX_STRIDE(index_stride
) | S_008F0C_ADD_TID_ENABLE(add_tid
);
1391 if (sctx
->chip_class
>= GFX9
)
1392 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1394 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1396 if (sctx
->chip_class
>= GFX10
) {
1397 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1398 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) | S_008F0C_RESOURCE_LEVEL(1);
1400 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1401 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1404 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1405 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(buffer
), RADEON_USAGE_READWRITE
,
1407 buffers
->enabled_mask
|= 1u << slot
;
1409 /* Clear the descriptor. */
1410 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1411 buffers
->enabled_mask
&= ~(1u << slot
);
1414 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1417 /* INTERNAL CONST BUFFERS */
1419 static void si_set_polygon_stipple(struct pipe_context
*ctx
, const struct pipe_poly_stipple
*state
)
1421 struct si_context
*sctx
= (struct si_context
*)ctx
;
1422 struct pipe_constant_buffer cb
= {};
1423 unsigned stipple
[32];
1426 for (i
= 0; i
< 32; i
++)
1427 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1429 cb
.user_buffer
= stipple
;
1430 cb
.buffer_size
= sizeof(stipple
);
1432 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1435 /* TEXTURE METADATA ENABLE/DISABLE */
1437 static void si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1439 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1440 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1442 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1443 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1444 struct si_texture
*tex
;
1446 if (!res
|| res
->target
== PIPE_BUFFER
)
1449 tex
= (struct si_texture
*)res
;
1450 if (!color_needs_decompression(tex
))
1453 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
, struct si_texture_handle
*,
1457 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1458 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1459 struct pipe_resource
*res
= view
->resource
;
1460 struct si_texture
*tex
;
1462 if (!res
|| res
->target
== PIPE_BUFFER
)
1465 tex
= (struct si_texture
*)res
;
1466 if (!color_needs_decompression(tex
))
1469 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
, struct si_image_handle
*,
1474 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1475 * while the texture is bound, possibly by a different context. In that case,
1476 * call this function to update needs_*_decompress_masks.
1478 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1480 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1481 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1482 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1483 si_update_shader_needs_decompress_mask(sctx
, i
);
1486 si_resident_handles_update_needs_color_decompress(sctx
);
1489 /* BUFFER DISCARD/INVALIDATION */
1491 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1492 * If buf == NULL, reset all descriptors.
1494 static void si_reset_buffer_resources(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1495 unsigned descriptors_idx
, unsigned slot_mask
,
1496 struct pipe_resource
*buf
, enum radeon_bo_priority priority
)
1498 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1499 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1502 unsigned i
= u_bit_scan(&mask
);
1503 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1505 if (buffer
&& (!buf
|| buffer
== buf
)) {
1506 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1507 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1509 radeon_add_to_gfx_buffer_list_check_mem(
1510 sctx
, si_resource(buffer
),
1511 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
1517 /* Update all buffer bindings where the buffer is bound, including
1518 * all resource descriptors. This is invalidate_buffer without
1521 * If buf == NULL, update all buffer bindings.
1523 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1525 struct si_resource
*buffer
= si_resource(buf
);
1527 unsigned num_elems
= sctx
->num_vertex_elements
;
1529 /* We changed the buffer, now we need to bind it where the old one
1530 * was bound. This consists of 2 things:
1531 * 1) Updating the resource descriptor and dirtying it.
1532 * 2) Adding a relocation to the CS, so that it's usable.
1535 /* Vertex buffers. */
1538 sctx
->vertex_buffers_dirty
= true;
1539 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1540 for (i
= 0; i
< num_elems
; i
++) {
1541 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1543 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1545 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1548 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1549 sctx
->vertex_buffers_dirty
= true;
1555 /* Streamout buffers. (other internal buffers can't be invalidated) */
1556 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1557 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1558 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1559 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1560 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1562 if (!buffer
|| (buf
&& buffer
!= buf
))
1565 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1566 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1568 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_WRITE
,
1569 RADEON_PRIO_SHADER_RW_BUFFER
, true);
1571 /* Update the streamout state. */
1572 if (sctx
->streamout
.begin_emitted
)
1573 si_emit_streamout_end(sctx
);
1574 sctx
->streamout
.append_bitmask
= sctx
->streamout
.enabled_mask
;
1575 si_streamout_buffers_dirty(sctx
);
1579 /* Constant and shader buffers. */
1580 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1581 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1582 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1583 si_const_and_shader_buffer_descriptors_idx(shader
),
1584 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1585 buf
, sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1588 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1589 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1590 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1591 si_const_and_shader_buffer_descriptors_idx(shader
),
1592 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
), buf
,
1593 sctx
->const_and_shader_buffers
[shader
].priority
);
1596 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1597 /* Texture buffers - update bindings. */
1598 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1599 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1600 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1601 unsigned mask
= samplers
->enabled_mask
;
1604 unsigned i
= u_bit_scan(&mask
);
1605 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1607 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1608 unsigned desc_slot
= si_get_sampler_slot(i
);
1610 si_set_buf_desc_address(si_resource(buffer
), samplers
->views
[i
]->u
.buf
.offset
,
1611 descs
->list
+ desc_slot
* 16 + 4);
1612 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1614 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1615 RADEON_PRIO_SAMPLER_BUFFER
, true);
1622 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1623 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1624 struct si_images
*images
= &sctx
->images
[shader
];
1625 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1626 unsigned mask
= images
->enabled_mask
;
1629 unsigned i
= u_bit_scan(&mask
);
1630 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1632 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1633 unsigned desc_slot
= si_get_image_slot(i
);
1635 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1636 si_mark_image_range_valid(&images
->views
[i
]);
1638 si_set_buf_desc_address(si_resource(buffer
), images
->views
[i
].u
.buf
.offset
,
1639 descs
->list
+ desc_slot
* 8 + 4);
1640 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1642 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
),
1643 RADEON_USAGE_READWRITE
,
1644 RADEON_PRIO_SAMPLER_BUFFER
, true);
1650 /* Bindless texture handles */
1651 if (!buffer
|| buffer
->texture_handle_allocated
) {
1652 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1654 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1655 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1656 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1657 struct pipe_resource
*buffer
= view
->texture
;
1659 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1660 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1661 descs
->list
+ desc_slot
* 16 + 4);
1663 (*tex_handle
)->desc_dirty
= true;
1664 sctx
->bindless_descriptors_dirty
= true;
1666 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1667 RADEON_PRIO_SAMPLER_BUFFER
, true);
1672 /* Bindless image handles */
1673 if (!buffer
|| buffer
->image_handle_allocated
) {
1674 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1676 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1677 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1678 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1679 struct pipe_resource
*buffer
= view
->resource
;
1681 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1682 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1683 si_mark_image_range_valid(view
);
1685 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1686 descs
->list
+ desc_slot
* 16 + 4);
1688 (*img_handle
)->desc_dirty
= true;
1689 sctx
->bindless_descriptors_dirty
= true;
1691 radeon_add_to_gfx_buffer_list_check_mem(
1692 sctx
, si_resource(buffer
), RADEON_USAGE_READWRITE
, RADEON_PRIO_SAMPLER_BUFFER
, true);
1698 /* Do the same for other contexts. They will invoke this function
1699 * with buffer == NULL.
1701 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1703 /* Skip the update for the current context, because we have already updated
1704 * the buffer bindings.
1706 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1707 sctx
->last_dirty_buf_counter
= new_counter
;
1711 static void si_upload_bindless_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
1712 unsigned num_dwords
)
1714 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1715 unsigned desc_slot_offset
= desc_slot
* 16;
1719 data
= desc
->list
+ desc_slot_offset
;
1720 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1722 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
, num_dwords
* 4, V_370_TC_L2
,
1726 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1728 if (!sctx
->bindless_descriptors_dirty
)
1731 /* Wait for graphics/compute to be idle before updating the resident
1732 * descriptors directly in memory, in case the GPU is using them.
1734 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
1735 sctx
->emit_cache_flush(sctx
);
1737 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1738 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1740 if (!(*tex_handle
)->desc_dirty
)
1743 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1744 (*tex_handle
)->desc_dirty
= false;
1747 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1748 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1750 if (!(*img_handle
)->desc_dirty
)
1753 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1754 (*img_handle
)->desc_dirty
= false;
1757 /* Invalidate L1 because it doesn't know that L2 changed. */
1758 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1759 sctx
->emit_cache_flush(sctx
);
1761 sctx
->bindless_descriptors_dirty
= false;
1764 /* Update mutable image descriptor fields of all resident textures. */
1765 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1766 struct si_texture_handle
*tex_handle
)
1768 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1769 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1770 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1771 uint32_t desc_list
[16];
1773 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1776 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1777 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
, desc
->list
+ desc_slot_offset
);
1779 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
))) {
1780 tex_handle
->desc_dirty
= true;
1781 sctx
->bindless_descriptors_dirty
= true;
1785 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1786 struct si_image_handle
*img_handle
)
1788 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1789 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1790 struct pipe_image_view
*view
= &img_handle
->view
;
1791 struct pipe_resource
*res
= view
->resource
;
1792 uint32_t image_desc
[16];
1793 unsigned desc_size
= (res
->nr_samples
>= 2 ? 16 : 8) * 4;
1795 if (res
->target
== PIPE_BUFFER
)
1798 memcpy(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
);
1799 si_set_shader_image_desc(sctx
, view
, true, desc
->list
+ desc_slot_offset
,
1800 desc
->list
+ desc_slot_offset
+ 8);
1802 if (memcmp(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
)) {
1803 img_handle
->desc_dirty
= true;
1804 sctx
->bindless_descriptors_dirty
= true;
1808 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1810 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1811 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1814 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1815 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1818 si_upload_bindless_descriptors(sctx
);
1821 /* Update mutable image descriptor fields of all bound textures. */
1822 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1826 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1827 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1828 struct si_images
*images
= &sctx
->images
[shader
];
1832 mask
= images
->enabled_mask
;
1834 unsigned i
= u_bit_scan(&mask
);
1835 struct pipe_image_view
*view
= &images
->views
[i
];
1837 if (!view
->resource
|| view
->resource
->target
== PIPE_BUFFER
)
1840 si_set_shader_image(sctx
, shader
, i
, view
, true);
1843 /* Sampler views. */
1844 mask
= samplers
->enabled_mask
;
1846 unsigned i
= u_bit_scan(&mask
);
1847 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1849 if (!view
|| !view
->texture
|| view
->texture
->target
== PIPE_BUFFER
)
1852 si_set_sampler_view(sctx
, shader
, i
, samplers
->views
[i
], true);
1855 si_update_shader_needs_decompress_mask(sctx
, shader
);
1858 si_update_all_resident_texture_descriptors(sctx
);
1859 si_update_ps_colorbuf0_slot(sctx
);
1862 /* SHADER USER DATA */
1864 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
, unsigned shader
)
1866 sctx
->shader_pointers_dirty
|=
1867 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
, SI_NUM_SHADER_DESCS
);
1869 if (shader
== PIPE_SHADER_VERTEX
) {
1870 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1871 sctx
->vertex_buffer_user_sgprs_dirty
=
1872 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1875 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1878 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1880 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1881 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1882 sctx
->vertex_buffer_user_sgprs_dirty
=
1883 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1884 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1885 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1886 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1889 /* Set a base register address for user data constants in the given shader.
1890 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1892 static void si_set_user_data_base(struct si_context
*sctx
, unsigned shader
, uint32_t new_base
)
1894 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1896 if (*base
!= new_base
) {
1900 si_mark_shader_pointers_dirty(sctx
, shader
);
1902 /* Any change in enabled shader stages requires re-emitting
1903 * the VS state SGPR, because it contains the clamp_vertex_color
1904 * state, which can be done in VS, TES, and GS.
1906 sctx
->last_vs_state
= ~0;
1910 /* This must be called when these are changed between enabled and disabled
1912 * - tessellation evaluation shader
1915 void si_shader_change_notify(struct si_context
*sctx
)
1917 /* VS can be bound as VS, ES, or LS. */
1918 if (sctx
->tes_shader
.cso
) {
1919 if (sctx
->chip_class
>= GFX10
) {
1920 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1921 } else if (sctx
->chip_class
== GFX9
) {
1922 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1924 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1926 } else if (sctx
->chip_class
>= GFX10
) {
1927 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1928 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1930 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1932 } else if (sctx
->gs_shader
.cso
) {
1933 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1935 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1938 /* TES can be bound as ES, VS, or not bound. */
1939 if (sctx
->tes_shader
.cso
) {
1940 if (sctx
->chip_class
>= GFX10
) {
1941 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1942 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1944 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1946 } else if (sctx
->gs_shader
.cso
) {
1947 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1949 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1952 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1956 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
, unsigned sh_offset
,
1957 unsigned pointer_count
)
1959 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
1960 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1963 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
, struct radeon_cmdbuf
*cs
,
1966 radeon_emit(cs
, va
);
1968 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
1971 static void si_emit_shader_pointer(struct si_context
*sctx
, struct si_descriptors
*desc
,
1974 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1975 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
1977 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
1978 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
1981 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
, unsigned pointer_mask
,
1987 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1988 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
1992 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
1994 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
1995 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
1997 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
1998 for (int i
= 0; i
< count
; i
++)
1999 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
[i
].gpu_address
);
2003 static void si_emit_global_shader_pointers(struct si_context
*sctx
, struct si_descriptors
*descs
)
2005 if (sctx
->chip_class
>= GFX10
) {
2006 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2007 /* HW VS stage only used in non-NGG mode. */
2008 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2009 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2010 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2012 } else if (sctx
->chip_class
== GFX9
) {
2013 /* Broadcast it to all shader stages. */
2014 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2018 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2019 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2020 si_emit_shader_pointer(sctx
, descs
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2021 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2022 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2023 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2026 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2028 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2030 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2031 si_emit_global_shader_pointers(sctx
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2034 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2035 sh_base
[PIPE_SHADER_VERTEX
]);
2036 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2037 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2038 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2039 sh_base
[PIPE_SHADER_FRAGMENT
]);
2040 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2041 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2042 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2043 sh_base
[PIPE_SHADER_GEOMETRY
]);
2045 sctx
->shader_pointers_dirty
&= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2047 if (sctx
->vertex_buffer_pointer_dirty
&& sctx
->num_vertex_elements
) {
2048 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2050 /* Find the location of the VB descriptor pointer. */
2051 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2052 if (sctx
->chip_class
>= GFX9
) {
2053 if (sctx
->tes_shader
.cso
)
2054 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2055 else if (sctx
->gs_shader
.cso
)
2056 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2059 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2060 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2061 si_emit_shader_pointer_body(
2062 sctx
->screen
, cs
, sctx
->vb_descriptors_buffer
->gpu_address
+ sctx
->vb_descriptors_offset
);
2063 sctx
->vertex_buffer_pointer_dirty
= false;
2066 if (sctx
->vertex_buffer_user_sgprs_dirty
&& sctx
->num_vertex_elements
&&
2067 sctx
->screen
->num_vbos_in_user_sgprs
) {
2068 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2069 unsigned num_desc
= MIN2(sctx
->num_vertex_elements
, sctx
->screen
->num_vbos_in_user_sgprs
);
2070 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST
* 4;
2072 si_emit_shader_pointer_head(cs
, sh_offset
, num_desc
* 4);
2073 radeon_emit_array(cs
, sctx
->vb_descriptor_user_sgprs
, num_desc
* 4);
2074 sctx
->vertex_buffer_user_sgprs_dirty
= false;
2077 if (sctx
->graphics_bindless_pointer_dirty
) {
2078 si_emit_global_shader_pointers(sctx
, &sctx
->bindless_descriptors
);
2079 sctx
->graphics_bindless_pointer_dirty
= false;
2083 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2085 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2087 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2088 R_00B900_COMPUTE_USER_DATA_0
);
2089 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2091 if (sctx
->compute_bindless_pointer_dirty
) {
2092 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2093 sctx
->compute_bindless_pointer_dirty
= false;
2099 static void si_init_bindless_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
,
2100 short shader_userdata_rel_index
, unsigned num_elements
)
2102 ASSERTED
unsigned desc_slot
;
2104 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2105 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2107 /* The first bindless descriptor is stored at slot 1, because 0 is not
2108 * considered to be a valid handle.
2110 sctx
->num_bindless_descriptors
= 1;
2112 /* Track which bindless slots are used (or not). */
2113 util_idalloc_init(&sctx
->bindless_used_slots
);
2114 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2116 /* Reserve slot 0 because it's an invalid handle for bindless. */
2117 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2118 assert(desc_slot
== 0);
2121 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2123 si_release_descriptors(&sctx
->bindless_descriptors
);
2124 util_idalloc_fini(&sctx
->bindless_used_slots
);
2127 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2129 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2132 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2133 if (desc_slot
>= desc
->num_elements
) {
2134 /* The array of bindless descriptors is full, resize it. */
2135 unsigned slot_size
= desc
->element_dw_size
* 4;
2136 unsigned new_num_elements
= desc
->num_elements
* 2;
2139 REALLOC(desc
->list
, desc
->num_elements
* slot_size
, new_num_elements
* slot_size
);
2140 desc
->num_elements
= new_num_elements
;
2141 desc
->num_active_slots
= new_num_elements
;
2148 static unsigned si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2151 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2152 unsigned desc_slot
, desc_slot_offset
;
2154 /* Find a free slot. */
2155 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2157 /* For simplicity, sampler and image bindless descriptors use fixed
2158 * 16-dword slots for now. Image descriptors only need 8-dword but this
2159 * doesn't really matter because no real apps use image handles.
2161 desc_slot_offset
= desc_slot
* 16;
2163 /* Copy the descriptor into the array. */
2164 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2166 /* Re-upload the whole array of bindless descriptors into a new buffer.
2168 if (!si_upload_descriptors(sctx
, desc
))
2171 /* Make sure to re-emit the shader pointers for all stages. */
2172 sctx
->graphics_bindless_pointer_dirty
= true;
2173 sctx
->compute_bindless_pointer_dirty
= true;
2178 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
2179 struct pipe_resource
*resource
, uint64_t offset
,
2182 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2183 struct si_resource
*buf
= si_resource(resource
);
2184 unsigned desc_slot_offset
= desc_slot
* 16;
2185 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2186 uint64_t old_desc_va
;
2188 assert(resource
->target
== PIPE_BUFFER
);
2190 /* Retrieve the old buffer addr from the descriptor. */
2191 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2193 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2194 /* The buffer has been invalidated when the handle wasn't
2195 * resident, update the descriptor and the dirty flag.
2197 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2203 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
, struct pipe_sampler_view
*view
,
2204 const struct pipe_sampler_state
*state
)
2206 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2207 struct si_context
*sctx
= (struct si_context
*)ctx
;
2208 struct si_texture_handle
*tex_handle
;
2209 struct si_sampler_state
*sstate
;
2210 uint32_t desc_list
[16];
2213 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2217 memset(desc_list
, 0, sizeof(desc_list
));
2218 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2220 sstate
= ctx
->create_sampler_state(ctx
, state
);
2226 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2227 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2228 ctx
->delete_sampler_state(ctx
, sstate
);
2230 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2231 if (!tex_handle
->desc_slot
) {
2236 handle
= tex_handle
->desc_slot
;
2238 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)(uintptr_t)handle
, tex_handle
)) {
2243 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2245 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2250 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2252 struct si_context
*sctx
= (struct si_context
*)ctx
;
2253 struct si_texture_handle
*tex_handle
;
2254 struct hash_entry
*entry
;
2256 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2260 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2262 /* Allow this descriptor slot to be re-used. */
2263 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2265 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2266 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2270 static void si_make_texture_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2273 struct si_context
*sctx
= (struct si_context
*)ctx
;
2274 struct si_texture_handle
*tex_handle
;
2275 struct si_sampler_view
*sview
;
2276 struct hash_entry
*entry
;
2278 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2282 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2283 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2286 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2287 struct si_texture
*tex
= (struct si_texture
*)sview
->base
.texture
;
2289 if (depth_needs_decompression(tex
)) {
2290 util_dynarray_append(&sctx
->resident_tex_needs_depth_decompress
,
2291 struct si_texture_handle
*, tex_handle
);
2294 if (color_needs_decompression(tex
)) {
2295 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
2296 struct si_texture_handle
*, tex_handle
);
2299 if (tex
->surface
.dcc_offset
&& p_atomic_read(&tex
->framebuffers_bound
))
2300 sctx
->need_check_render_feedback
= true;
2302 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2304 si_update_bindless_buffer_descriptor(sctx
, tex_handle
->desc_slot
, sview
->base
.texture
,
2305 sview
->base
.u
.buf
.offset
, &tex_handle
->desc_dirty
);
2308 /* Re-upload the descriptor if it has been updated while it
2311 if (tex_handle
->desc_dirty
)
2312 sctx
->bindless_descriptors_dirty
= true;
2314 /* Add the texture handle to the per-context list. */
2315 util_dynarray_append(&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
);
2317 /* Add the buffers to the current CS in case si_begin_new_cs()
2318 * is not going to be called.
2320 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2321 sview
->is_stencil_sampler
, false);
2323 /* Remove the texture handle from the per-context list. */
2324 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
, struct si_texture_handle
*,
2327 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2328 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_depth_decompress
,
2329 struct si_texture_handle
*, tex_handle
);
2331 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_color_decompress
,
2332 struct si_texture_handle
*, tex_handle
);
2337 static uint64_t si_create_image_handle(struct pipe_context
*ctx
, const struct pipe_image_view
*view
)
2339 struct si_context
*sctx
= (struct si_context
*)ctx
;
2340 struct si_image_handle
*img_handle
;
2341 uint32_t desc_list
[16];
2344 if (!view
|| !view
->resource
)
2347 img_handle
= CALLOC_STRUCT(si_image_handle
);
2351 memset(desc_list
, 0, sizeof(desc_list
));
2352 si_init_descriptor_list(&desc_list
[0], 8, 2, null_image_descriptor
);
2354 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], &desc_list
[8]);
2356 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2357 if (!img_handle
->desc_slot
) {
2362 handle
= img_handle
->desc_slot
;
2364 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)(uintptr_t)handle
, img_handle
)) {
2369 util_copy_image_view(&img_handle
->view
, view
);
2371 si_resource(view
->resource
)->image_handle_allocated
= true;
2376 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2378 struct si_context
*sctx
= (struct si_context
*)ctx
;
2379 struct si_image_handle
*img_handle
;
2380 struct hash_entry
*entry
;
2382 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2386 img_handle
= (struct si_image_handle
*)entry
->data
;
2388 util_copy_image_view(&img_handle
->view
, NULL
);
2389 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2393 static void si_make_image_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2394 unsigned access
, bool resident
)
2396 struct si_context
*sctx
= (struct si_context
*)ctx
;
2397 struct si_image_handle
*img_handle
;
2398 struct pipe_image_view
*view
;
2399 struct si_resource
*res
;
2400 struct hash_entry
*entry
;
2402 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2406 img_handle
= (struct si_image_handle
*)entry
->data
;
2407 view
= &img_handle
->view
;
2408 res
= si_resource(view
->resource
);
2411 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2412 struct si_texture
*tex
= (struct si_texture
*)res
;
2413 unsigned level
= view
->u
.tex
.level
;
2415 if (color_needs_decompression(tex
)) {
2416 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
2417 struct si_image_handle
*, img_handle
);
2420 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
2421 sctx
->need_check_render_feedback
= true;
2423 si_update_bindless_image_descriptor(sctx
, img_handle
);
2425 si_update_bindless_buffer_descriptor(sctx
, img_handle
->desc_slot
, view
->resource
,
2426 view
->u
.buf
.offset
, &img_handle
->desc_dirty
);
2429 /* Re-upload the descriptor if it has been updated while it
2432 if (img_handle
->desc_dirty
)
2433 sctx
->bindless_descriptors_dirty
= true;
2435 /* Add the image handle to the per-context list. */
2436 util_dynarray_append(&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
);
2438 /* Add the buffers to the current CS in case si_begin_new_cs()
2439 * is not going to be called.
2441 si_sampler_view_add_buffer(
2442 sctx
, view
->resource
,
2443 (access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
2446 /* Remove the image handle from the per-context list. */
2447 util_dynarray_delete_unordered(&sctx
->resident_img_handles
, struct si_image_handle
*,
2450 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2451 util_dynarray_delete_unordered(&sctx
->resident_img_needs_color_decompress
,
2452 struct si_image_handle
*, img_handle
);
2457 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2459 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2461 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/ sizeof(struct si_texture_handle
*);
2462 num_resident_img_handles
= sctx
->resident_img_handles
.size
/ sizeof(struct si_image_handle
*);
2464 /* Add all resident texture handles. */
2465 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
2466 struct si_sampler_view
*sview
= (struct si_sampler_view
*)(*tex_handle
)->view
;
2468 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2469 sview
->is_stencil_sampler
, false);
2472 /* Add all resident image handles. */
2473 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
2474 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2476 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
2479 sctx
->num_resident_handles
+= num_resident_tex_handles
+ num_resident_img_handles
;
2480 assert(sctx
->bo_list_add_all_resident_resources
);
2481 sctx
->bo_list_add_all_resident_resources
= false;
2484 /* INIT/DEINIT/UPLOAD */
2486 void si_init_all_descriptors(struct si_context
*sctx
)
2489 unsigned first_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2491 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2493 sctx
->chip_class
>= GFX9
&& (i
== PIPE_SHADER_TESS_CTRL
|| i
== PIPE_SHADER_GEOMETRY
);
2494 unsigned num_sampler_slots
= SI_NUM_IMAGE_SLOTS
/ 2 + SI_NUM_SAMPLERS
;
2495 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2497 struct si_descriptors
*desc
;
2500 if (i
== PIPE_SHADER_TESS_CTRL
) {
2502 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2503 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2505 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2508 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2511 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2513 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2514 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
, num_buffer_slots
,
2515 rel_dw_offset
, RADEON_PRIO_SHADER_RW_BUFFER
,
2516 RADEON_PRIO_CONST_BUFFER
);
2517 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2520 if (i
== PIPE_SHADER_TESS_CTRL
) {
2522 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2523 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2525 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2528 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2531 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2534 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2535 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2538 for (j
= 0; j
< SI_NUM_IMAGE_SLOTS
; j
++)
2539 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2540 for (; j
< SI_NUM_IMAGE_SLOTS
+ SI_NUM_SAMPLERS
* 2; j
++)
2541 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2544 si_init_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2545 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2546 /* The second priority is used by
2547 * const buffers in RW buffer slots. */
2548 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2549 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2551 /* Initialize an array of 1024 bindless descriptors, when the limit is
2552 * reached, just make it larger and re-upload the whole array.
2554 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2555 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
, 1024);
2557 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2559 /* Set pipe_context functions. */
2560 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2561 sctx
->b
.set_shader_images
= si_set_shader_images
;
2562 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2563 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2564 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2565 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2566 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2567 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2568 sctx
->b
.create_image_handle
= si_create_image_handle
;
2569 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2570 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2572 if (!sctx
->has_graphics
)
2575 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2577 /* Shader user data. */
2578 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2580 /* Set default and immutable mappings. */
2582 assert(sctx
->chip_class
>= GFX10
);
2583 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2585 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2588 if (sctx
->chip_class
== GFX9
) {
2589 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2590 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2592 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2593 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2595 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2598 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2600 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2602 /* Assume nothing will go wrong: */
2603 sctx
->shader_pointers_dirty
|= dirty
;
2606 unsigned i
= u_bit_scan(&dirty
);
2608 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2612 sctx
->descriptors_dirty
&= ~mask
;
2614 si_upload_bindless_descriptors(sctx
);
2619 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2621 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2622 return si_upload_shader_descriptors(sctx
, mask
);
2625 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2627 /* Does not update rw_buffers as that is not needed for compute shaders
2628 * and the input buffer is using the same SGPR's anyway.
2630 const unsigned mask
=
2631 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2632 return si_upload_shader_descriptors(sctx
, mask
);
2635 void si_release_all_descriptors(struct si_context
*sctx
)
2639 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2640 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2641 si_const_and_shader_buffer_descriptors(sctx
, i
));
2642 si_release_sampler_views(&sctx
->samplers
[i
]);
2643 si_release_image_views(&sctx
->images
[i
]);
2645 si_release_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2646 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2647 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2649 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2650 si_release_descriptors(&sctx
->descriptors
[i
]);
2652 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2653 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2655 si_release_bindless_descriptors(sctx
);
2658 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2660 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2661 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2662 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2663 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2665 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2666 si_vertex_buffers_begin_new_cs(sctx
);
2668 if (sctx
->bo_list_add_all_resident_resources
)
2669 si_resident_buffers_add_all_to_bo_list(sctx
);
2671 assert(sctx
->bo_list_add_all_gfx_resources
);
2672 sctx
->bo_list_add_all_gfx_resources
= false;
2675 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2677 unsigned sh
= PIPE_SHADER_COMPUTE
;
2679 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2680 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2681 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2682 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2684 if (sctx
->bo_list_add_all_resident_resources
)
2685 si_resident_buffers_add_all_to_bo_list(sctx
);
2687 assert(sctx
->bo_list_add_all_compute_resources
);
2688 sctx
->bo_list_add_all_compute_resources
= false;
2691 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2693 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2694 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2695 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2697 si_shader_pointers_begin_new_cs(sctx
);
2699 sctx
->bo_list_add_all_resident_resources
= true;
2700 sctx
->bo_list_add_all_gfx_resources
= true;
2701 sctx
->bo_list_add_all_compute_resources
= true;
2704 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
, uint64_t new_active_mask
)
2706 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2708 /* Ignore no-op updates and updates that disable all slots. */
2709 if (!new_active_mask
||
2710 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
, desc
->num_active_slots
))
2714 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2715 assert(new_active_mask
== 0);
2717 /* Upload/dump descriptors if slots are being enabled. */
2718 if (first
< desc
->first_active_slot
||
2719 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2720 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2722 desc
->first_active_slot
= first
;
2723 desc
->num_active_slots
= count
;
2726 void si_set_active_descriptors_for_shader(struct si_context
*sctx
, struct si_shader_selector
*sel
)
2731 si_set_active_descriptors(sctx
, si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2732 sel
->active_const_and_shader_buffers
);
2733 si_set_active_descriptors(sctx
, si_sampler_and_image_descriptors_idx(sel
->type
),
2734 sel
->active_samplers_and_images
);