2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 /* Resource binding slots and sampler states (each described with 8 or
25 * 4 dwords) are stored in lists in memory which is accessed by shaders
26 * using scalar load instructions.
28 * This file is responsible for managing such lists. It keeps a copy of all
29 * descriptors in CPU memory and re-uploads a whole list if some slots have
32 * This code is also reponsible for updating shader pointers to those lists.
34 * Note that CP DMA can't be used for updating the lists, because a GPU hang
35 * could leave the list in a mid-IB state and the next IB would get wrong
36 * descriptors and the whole context would be unusable at that point.
37 * (Note: The register shadowing can't be used due to the same reason)
39 * Also, uploading descriptors to newly allocated memory doesn't require
43 * Possible scenarios for one 16 dword image+sampler slot:
45 * | Image | w/ FMASK | Buffer | NULL
46 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
47 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
48 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
49 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 * FMASK implies MSAA, therefore no sampler state.
52 * Sampler states are never unbound except when FMASK is bound.
55 #include "radeon/r600_cs.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
103 if (va
& (1ull << 47))
104 va
|= 0xffffull
<< 48;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 r600_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 r600_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
171 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 (unsigned*)&buffer_offset
,
174 (struct pipe_resource
**)&desc
->buffer
,
177 desc
->gpu_address
= 0;
178 return false; /* skip the draw call */
181 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
183 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
185 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
186 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
188 /* The shader pointer should point to slot 0. */
189 buffer_offset
-= first_slot_offset
;
190 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
192 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
197 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
202 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
203 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
208 static inline enum radeon_bo_priority
209 si_get_sampler_view_priority(struct r600_resource
*res
)
211 if (res
->b
.b
.target
== PIPE_BUFFER
)
212 return RADEON_PRIO_SAMPLER_BUFFER
;
214 if (res
->b
.b
.nr_samples
> 1)
215 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
217 return RADEON_PRIO_SAMPLER_TEXTURE
;
221 si_sampler_and_image_descriptors_idx(unsigned shader
)
223 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
224 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
227 static struct si_descriptors
*
228 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
230 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
233 static void si_release_sampler_views(struct si_samplers
*samplers
)
237 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
238 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
242 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
243 struct pipe_resource
*resource
,
244 enum radeon_bo_usage usage
,
245 bool is_stencil_sampler
,
248 struct r600_resource
*rres
;
249 struct r600_texture
*rtex
;
250 enum radeon_bo_priority priority
;
255 if (resource
->target
!= PIPE_BUFFER
) {
256 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
258 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
259 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
262 rres
= (struct r600_resource
*)resource
;
263 priority
= si_get_sampler_view_priority(rres
);
265 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
266 rres
, usage
, priority
,
269 if (resource
->target
== PIPE_BUFFER
)
272 /* Now add separate DCC or HTILE. */
273 rtex
= (struct r600_texture
*)resource
;
274 if (rtex
->dcc_separate_buffer
) {
275 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
276 rtex
->dcc_separate_buffer
, usage
,
277 RADEON_PRIO_DCC
, check_mem
);
281 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
282 struct si_samplers
*samplers
)
284 unsigned mask
= samplers
->enabled_mask
;
286 /* Add buffers to the CS. */
288 int i
= u_bit_scan(&mask
);
289 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
291 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
293 sview
->is_stencil_sampler
, false);
297 /* Set buffer descriptor fields that can be changed by reallocations. */
298 static void si_set_buf_desc_address(struct r600_resource
*buf
,
299 uint64_t offset
, uint32_t *state
)
301 uint64_t va
= buf
->gpu_address
+ offset
;
304 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
305 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
308 /* Set texture descriptor fields that can be changed by reallocations.
311 * \param base_level_info information of the level of BASE_ADDRESS
312 * \param base_level the level of BASE_ADDRESS
313 * \param first_level pipe_sampler_view.u.tex.first_level
314 * \param block_width util_format_get_blockwidth()
315 * \param is_stencil select between separate Z & Stencil
316 * \param state descriptor to update
318 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
319 struct r600_texture
*tex
,
320 const struct legacy_surf_level
*base_level_info
,
321 unsigned base_level
, unsigned first_level
,
322 unsigned block_width
, bool is_stencil
,
325 uint64_t va
, meta_va
= 0;
327 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
328 tex
= tex
->flushed_depth_texture
;
332 va
= tex
->resource
.gpu_address
;
334 if (sscreen
->info
.chip_class
>= GFX9
) {
335 /* Only stencil_offset needs to be added here. */
337 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
339 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
341 va
+= base_level_info
->offset
;
345 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
346 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
348 /* Only macrotiled modes can set tile swizzle.
349 * GFX9 doesn't use (legacy) base_level_info.
351 if (sscreen
->info
.chip_class
>= GFX9
||
352 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
353 state
[0] |= tex
->surface
.tile_swizzle
;
355 if (sscreen
->info
.chip_class
>= VI
) {
356 state
[6] &= C_008F28_COMPRESSION_EN
;
359 if (vi_dcc_enabled(tex
, first_level
)) {
360 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
363 if (sscreen
->info
.chip_class
== VI
) {
364 meta_va
+= base_level_info
->dcc_offset
;
365 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
368 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
369 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
370 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
374 state
[6] |= S_008F28_COMPRESSION_EN(1);
375 state
[7] = meta_va
>> 8;
379 if (sscreen
->info
.chip_class
>= GFX9
) {
380 state
[3] &= C_008F1C_SW_MODE
;
381 state
[4] &= C_008F20_PITCH_GFX9
;
384 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
385 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
387 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
388 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
391 state
[5] &= C_008F24_META_DATA_ADDRESS
&
392 C_008F24_META_PIPE_ALIGNED
&
393 C_008F24_META_RB_ALIGNED
;
395 struct gfx9_surf_meta_flags meta
;
398 meta
= tex
->surface
.u
.gfx9
.dcc
;
400 meta
= tex
->surface
.u
.gfx9
.htile
;
402 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
403 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
404 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
408 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
409 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
411 state
[3] &= C_008F1C_TILING_INDEX
;
412 state
[3] |= S_008F1C_TILING_INDEX(index
);
413 state
[4] &= C_008F20_PITCH_GFX6
;
414 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
418 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
419 struct si_sampler_view
*sview
,
420 struct r600_texture
*tex
,
423 if (sview
&& sview
->is_integer
)
424 memcpy(desc
, sstate
->integer_val
, 4*4);
425 else if (tex
&& tex
->upgraded_depth
&&
426 (!sview
|| !sview
->is_stencil_sampler
))
427 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
429 memcpy(desc
, sstate
->val
, 4*4);
432 static void si_set_sampler_view_desc(struct si_context
*sctx
,
433 struct si_sampler_view
*sview
,
434 struct si_sampler_state
*sstate
,
437 struct pipe_sampler_view
*view
= &sview
->base
;
438 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
439 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
441 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
442 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
443 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
444 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
446 sview
->dcc_incompatible
= false;
449 assert(rtex
); /* views with texture == NULL aren't supported */
450 memcpy(desc
, sview
->state
, 8*4);
453 si_set_buf_desc_address(&rtex
->resource
,
454 sview
->base
.u
.buf
.offset
,
457 bool is_separate_stencil
= rtex
->db_compatible
&&
458 sview
->is_stencil_sampler
;
460 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
461 sview
->base_level_info
,
463 sview
->base
.u
.tex
.first_level
,
469 if (!is_buffer
&& rtex
->fmask
.size
) {
470 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
472 /* Disable FMASK and bind sampler state in [12:15]. */
473 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
476 si_set_sampler_state_desc(sstate
, sview
,
477 is_buffer
? NULL
: rtex
,
482 static bool color_needs_decompression(struct r600_texture
*rtex
)
484 return rtex
->fmask
.size
||
485 (rtex
->dirty_level_mask
&&
486 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
489 static bool depth_needs_decompression(struct r600_texture
*rtex
)
491 /* If the depth/stencil texture is TC-compatible, no decompression
492 * will be done. The decompression function will only flush DB caches
493 * to make it coherent with shaders. That's necessary because the driver
494 * doesn't flush DB caches in any other case.
496 return rtex
->db_compatible
;
499 static void si_set_sampler_view(struct si_context
*sctx
,
501 unsigned slot
, struct pipe_sampler_view
*view
,
502 bool disallow_early_out
)
504 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
505 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
506 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
507 unsigned desc_slot
= si_get_sampler_slot(slot
);
508 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
510 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
514 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
516 si_set_sampler_view_desc(sctx
, rview
,
517 samplers
->sampler_states
[slot
], desc
);
519 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
520 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
521 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
522 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
524 if (depth_needs_decompression(rtex
)) {
525 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
527 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
529 if (color_needs_decompression(rtex
)) {
530 samplers
->needs_color_decompress_mask
|= 1u << slot
;
532 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
535 if (rtex
->dcc_offset
&&
536 p_atomic_read(&rtex
->framebuffers_bound
))
537 sctx
->need_check_render_feedback
= true;
540 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
541 samplers
->enabled_mask
|= 1u << slot
;
543 /* Since this can flush, it must be done after enabled_mask is
545 si_sampler_view_add_buffer(sctx
, view
->texture
,
547 rview
->is_stencil_sampler
, true);
549 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
550 memcpy(desc
, null_texture_descriptor
, 8*4);
551 /* Only clear the lower dwords of FMASK. */
552 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
553 /* Re-set the sampler state if we are transitioning from FMASK. */
554 if (samplers
->sampler_states
[slot
])
555 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
558 samplers
->enabled_mask
&= ~(1u << slot
);
559 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
560 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
563 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
566 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
569 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
570 unsigned shader_bit
= 1 << shader
;
572 if (samplers
->needs_depth_decompress_mask
||
573 samplers
->needs_color_decompress_mask
||
574 sctx
->images
[shader
].needs_color_decompress_mask
)
575 sctx
->shader_needs_decompress_mask
|= shader_bit
;
577 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
580 static void si_set_sampler_views(struct pipe_context
*ctx
,
581 enum pipe_shader_type shader
, unsigned start
,
583 struct pipe_sampler_view
**views
)
585 struct si_context
*sctx
= (struct si_context
*)ctx
;
588 if (!count
|| shader
>= SI_NUM_SHADERS
)
592 for (i
= 0; i
< count
; i
++)
593 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
595 for (i
= 0; i
< count
; i
++)
596 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
599 si_update_shader_needs_decompress_mask(sctx
, shader
);
603 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
605 unsigned mask
= samplers
->enabled_mask
;
608 int i
= u_bit_scan(&mask
);
609 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
611 if (res
&& res
->target
!= PIPE_BUFFER
) {
612 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
614 if (color_needs_decompression(rtex
)) {
615 samplers
->needs_color_decompress_mask
|= 1u << i
;
617 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
626 si_release_image_views(struct si_images
*images
)
630 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
631 struct pipe_image_view
*view
= &images
->views
[i
];
633 pipe_resource_reference(&view
->resource
, NULL
);
638 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
640 uint mask
= images
->enabled_mask
;
642 /* Add buffers to the CS. */
644 int i
= u_bit_scan(&mask
);
645 struct pipe_image_view
*view
= &images
->views
[i
];
647 assert(view
->resource
);
649 si_sampler_view_add_buffer(sctx
, view
->resource
,
650 RADEON_USAGE_READWRITE
, false, false);
655 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
657 struct si_images
*images
= &ctx
->images
[shader
];
659 if (images
->enabled_mask
& (1u << slot
)) {
660 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
661 unsigned desc_slot
= si_get_image_slot(slot
);
663 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
664 images
->needs_color_decompress_mask
&= ~(1 << slot
);
666 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
667 images
->enabled_mask
&= ~(1u << slot
);
668 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
673 si_mark_image_range_valid(const struct pipe_image_view
*view
)
675 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
677 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
679 util_range_add(&res
->valid_buffer_range
,
681 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
684 static void si_set_shader_image_desc(struct si_context
*ctx
,
685 const struct pipe_image_view
*view
,
686 bool skip_decompress
,
689 struct si_screen
*screen
= ctx
->screen
;
690 struct r600_resource
*res
;
692 res
= (struct r600_resource
*)view
->resource
;
694 if (res
->b
.b
.target
== PIPE_BUFFER
) {
695 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
696 si_mark_image_range_valid(view
);
698 si_make_buffer_descriptor(screen
, res
,
701 view
->u
.buf
.size
, desc
);
702 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
704 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
705 struct r600_texture
*tex
= (struct r600_texture
*)res
;
706 unsigned level
= view
->u
.tex
.level
;
707 unsigned width
, height
, depth
, hw_level
;
708 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
709 unsigned access
= view
->access
;
711 /* Clear the write flag when writes can't occur.
712 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
713 * so we don't wanna trigger it.
715 if (tex
->is_depth
|| tex
->resource
.b
.b
.nr_samples
>= 2) {
716 assert(!"Z/S and MSAA image stores are not supported");
717 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
720 assert(!tex
->is_depth
);
721 assert(tex
->fmask
.size
== 0);
723 if (uses_dcc
&& !skip_decompress
&&
724 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
725 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
726 /* If DCC can't be disabled, at least decompress it.
727 * The decompression is relatively cheap if the surface
728 * has been decompressed already.
730 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
731 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
734 if (ctx
->b
.chip_class
>= GFX9
) {
735 /* Always set the base address. The swizzle modes don't
736 * allow setting mipmap level offsets as the base.
738 width
= res
->b
.b
.width0
;
739 height
= res
->b
.b
.height0
;
740 depth
= res
->b
.b
.depth0
;
743 /* Always force the base level to the selected level.
745 * This is required for 3D textures, where otherwise
746 * selecting a single slice for non-layered bindings
747 * fails. It doesn't hurt the other targets.
749 width
= u_minify(res
->b
.b
.width0
, level
);
750 height
= u_minify(res
->b
.b
.height0
, level
);
751 depth
= u_minify(res
->b
.b
.depth0
, level
);
755 si_make_texture_descriptor(screen
, tex
,
756 false, res
->b
.b
.target
,
757 view
->format
, swizzle
,
759 view
->u
.tex
.first_layer
,
760 view
->u
.tex
.last_layer
,
761 width
, height
, depth
,
763 si_set_mutable_tex_desc_fields(screen
, tex
,
764 &tex
->surface
.u
.legacy
.level
[level
],
766 util_format_get_blockwidth(view
->format
),
771 static void si_set_shader_image(struct si_context
*ctx
,
773 unsigned slot
, const struct pipe_image_view
*view
,
774 bool skip_decompress
)
776 struct si_images
*images
= &ctx
->images
[shader
];
777 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
778 struct r600_resource
*res
;
779 unsigned desc_slot
= si_get_image_slot(slot
);
780 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
782 if (!view
|| !view
->resource
) {
783 si_disable_shader_image(ctx
, shader
, slot
);
787 res
= (struct r600_resource
*)view
->resource
;
789 if (&images
->views
[slot
] != view
)
790 util_copy_image_view(&images
->views
[slot
], view
);
792 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
794 if (res
->b
.b
.target
== PIPE_BUFFER
) {
795 images
->needs_color_decompress_mask
&= ~(1 << slot
);
796 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
798 struct r600_texture
*tex
= (struct r600_texture
*)res
;
799 unsigned level
= view
->u
.tex
.level
;
801 if (color_needs_decompression(tex
)) {
802 images
->needs_color_decompress_mask
|= 1 << slot
;
804 images
->needs_color_decompress_mask
&= ~(1 << slot
);
807 if (vi_dcc_enabled(tex
, level
) &&
808 p_atomic_read(&tex
->framebuffers_bound
))
809 ctx
->need_check_render_feedback
= true;
812 images
->enabled_mask
|= 1u << slot
;
813 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
815 /* Since this can flush, it must be done after enabled_mask is updated. */
816 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
817 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
818 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
823 si_set_shader_images(struct pipe_context
*pipe
,
824 enum pipe_shader_type shader
,
825 unsigned start_slot
, unsigned count
,
826 const struct pipe_image_view
*views
)
828 struct si_context
*ctx
= (struct si_context
*)pipe
;
831 assert(shader
< SI_NUM_SHADERS
);
836 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
839 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
840 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
842 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
843 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
846 si_update_shader_needs_decompress_mask(ctx
, shader
);
850 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
852 unsigned mask
= images
->enabled_mask
;
855 int i
= u_bit_scan(&mask
);
856 struct pipe_resource
*res
= images
->views
[i
].resource
;
858 if (res
&& res
->target
!= PIPE_BUFFER
) {
859 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
861 if (color_needs_decompression(rtex
)) {
862 images
->needs_color_decompress_mask
|= 1 << i
;
864 images
->needs_color_decompress_mask
&= ~(1 << i
);
872 static void si_bind_sampler_states(struct pipe_context
*ctx
,
873 enum pipe_shader_type shader
,
874 unsigned start
, unsigned count
, void **states
)
876 struct si_context
*sctx
= (struct si_context
*)ctx
;
877 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
878 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
879 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
882 if (!count
|| shader
>= SI_NUM_SHADERS
)
885 for (i
= 0; i
< count
; i
++) {
886 unsigned slot
= start
+ i
;
887 unsigned desc_slot
= si_get_sampler_slot(slot
);
890 sstates
[i
] == samplers
->sampler_states
[slot
])
894 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
896 samplers
->sampler_states
[slot
] = sstates
[i
];
898 /* If FMASK is bound, don't overwrite it.
899 * The sampler state will be set after FMASK is unbound.
901 struct si_sampler_view
*sview
=
902 (struct si_sampler_view
*)samplers
->views
[slot
];
904 struct r600_texture
*tex
= NULL
;
906 if (sview
&& sview
->base
.texture
&&
907 sview
->base
.texture
->target
!= PIPE_BUFFER
)
908 tex
= (struct r600_texture
*)sview
->base
.texture
;
910 if (tex
&& tex
->fmask
.size
)
913 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
914 desc
->list
+ desc_slot
* 16 + 12);
916 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
920 /* BUFFER RESOURCES */
922 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
923 struct si_descriptors
*descs
,
924 unsigned num_buffers
,
925 short shader_userdata_rel_index
,
926 enum radeon_bo_usage shader_usage
,
927 enum radeon_bo_usage shader_usage_constbuf
,
928 enum radeon_bo_priority priority
,
929 enum radeon_bo_priority priority_constbuf
)
931 buffers
->shader_usage
= shader_usage
;
932 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
933 buffers
->priority
= priority
;
934 buffers
->priority_constbuf
= priority_constbuf
;
935 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
937 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
940 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
941 struct si_descriptors
*descs
)
945 for (i
= 0; i
< descs
->num_elements
; i
++) {
946 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
949 FREE(buffers
->buffers
);
952 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
953 struct si_buffer_resources
*buffers
)
955 unsigned mask
= buffers
->enabled_mask
;
957 /* Add buffers to the CS. */
959 int i
= u_bit_scan(&mask
);
961 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
962 r600_resource(buffers
->buffers
[i
]),
963 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
964 buffers
->shader_usage_constbuf
,
965 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
966 buffers
->priority_constbuf
);
970 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
971 struct si_descriptors
*descs
,
972 unsigned idx
, struct pipe_resource
**buf
,
973 unsigned *offset
, unsigned *size
)
975 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
977 struct r600_resource
*res
= r600_resource(*buf
);
978 const uint32_t *desc
= descs
->list
+ idx
* 4;
983 assert(G_008F04_STRIDE(desc
[1]) == 0);
984 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
986 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
987 *offset
= va
- res
->gpu_address
;
993 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
995 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
998 for (i
= 0; i
< count
; i
++) {
999 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1001 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1003 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1006 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1007 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1008 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1011 if (!sctx
->vb_descriptors_buffer
)
1013 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1014 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1015 RADEON_PRIO_DESCRIPTORS
);
1018 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1020 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1022 unsigned desc_list_byte_size
;
1023 unsigned first_vb_use_mask
;
1026 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1029 count
= velems
->count
;
1034 desc_list_byte_size
= velems
->desc_list_byte_size
;
1035 first_vb_use_mask
= velems
->first_vb_use_mask
;
1037 /* Vertex buffer descriptors are the only ones which are uploaded
1038 * directly through a staging buffer and don't go through
1039 * the fine-grained upload path.
1041 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1042 desc_list_byte_size
,
1043 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1044 &sctx
->vb_descriptors_offset
,
1045 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1047 if (!sctx
->vb_descriptors_buffer
) {
1048 sctx
->vb_descriptors_offset
= 0;
1049 sctx
->vb_descriptors_gpu_list
= NULL
;
1053 sctx
->vb_descriptors_gpu_list
= ptr
;
1054 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1055 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1056 RADEON_PRIO_DESCRIPTORS
);
1058 assert(count
<= SI_MAX_ATTRIBS
);
1060 for (i
= 0; i
< count
; i
++) {
1061 struct pipe_vertex_buffer
*vb
;
1062 struct r600_resource
*rbuffer
;
1063 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1064 uint32_t *desc
= &ptr
[i
*4];
1066 vb
= &sctx
->vertex_buffer
[vbo_index
];
1067 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1069 memset(desc
, 0, 16);
1073 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1074 velems
->src_offset
[i
];
1075 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1077 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1078 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1079 /* Round up by rounding down and adding 1 */
1080 num_records
= (num_records
- velems
->format_size
[i
]) /
1083 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1086 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1087 S_008F04_STRIDE(vb
->stride
);
1088 desc
[2] = num_records
;
1089 desc
[3] = velems
->rsrc_word3
[i
];
1091 if (first_vb_use_mask
& (1 << i
)) {
1092 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1093 (struct r600_resource
*)vb
->buffer
.resource
,
1094 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1098 /* Don't flush the const cache. It would have a very negative effect
1099 * on performance (confirmed by testing). New descriptors are always
1100 * uploaded to a fresh new buffer, so I don't think flushing the const
1101 * cache is needed. */
1102 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1103 sctx
->vertex_buffers_dirty
= false;
1104 sctx
->vertex_buffer_pointer_dirty
= true;
1105 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1110 /* CONSTANT BUFFERS */
1113 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1115 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1116 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1119 static struct si_descriptors
*
1120 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1122 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1125 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1126 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1130 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1131 si_optimal_tcc_alignment(sctx
, size
),
1133 (struct pipe_resource
**)rbuffer
, &tmp
);
1135 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1138 static void si_set_constant_buffer(struct si_context
*sctx
,
1139 struct si_buffer_resources
*buffers
,
1140 unsigned descriptors_idx
,
1141 uint slot
, const struct pipe_constant_buffer
*input
)
1143 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1144 assert(slot
< descs
->num_elements
);
1145 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1147 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1148 * with a NULL buffer). We need to use a dummy buffer instead. */
1149 if (sctx
->b
.chip_class
== CIK
&&
1150 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1151 input
= &sctx
->null_const_buf
;
1153 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1154 struct pipe_resource
*buffer
= NULL
;
1157 /* Upload the user buffer if needed. */
1158 if (input
->user_buffer
) {
1159 unsigned buffer_offset
;
1161 si_upload_const_buffer(sctx
,
1162 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1163 input
->buffer_size
, &buffer_offset
);
1165 /* Just unbind on failure. */
1166 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1169 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1171 pipe_resource_reference(&buffer
, input
->buffer
);
1172 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1173 /* Only track usage for non-user buffers. */
1174 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1177 /* Set the descriptor. */
1178 uint32_t *desc
= descs
->list
+ slot
*4;
1180 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1182 desc
[2] = input
->buffer_size
;
1183 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1187 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1188 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1190 buffers
->buffers
[slot
] = buffer
;
1191 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1192 (struct r600_resource
*)buffer
,
1193 buffers
->shader_usage_constbuf
,
1194 buffers
->priority_constbuf
, true);
1195 buffers
->enabled_mask
|= 1u << slot
;
1197 /* Clear the descriptor. */
1198 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1199 buffers
->enabled_mask
&= ~(1u << slot
);
1202 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1205 void si_set_rw_buffer(struct si_context
*sctx
,
1206 uint slot
, const struct pipe_constant_buffer
*input
)
1208 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1209 SI_DESCS_RW_BUFFERS
, slot
, input
);
1212 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1213 enum pipe_shader_type shader
, uint slot
,
1214 const struct pipe_constant_buffer
*input
)
1216 struct si_context
*sctx
= (struct si_context
*)ctx
;
1218 if (shader
>= SI_NUM_SHADERS
)
1221 if (slot
== 0 && input
&& input
->buffer
&&
1222 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1223 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1227 slot
= si_get_constbuf_slot(slot
);
1228 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1229 si_const_and_shader_buffer_descriptors_idx(shader
),
1233 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1234 uint slot
, struct pipe_constant_buffer
*cbuf
)
1236 cbuf
->user_buffer
= NULL
;
1237 si_get_buffer_from_descriptors(
1238 &sctx
->const_and_shader_buffers
[shader
],
1239 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1240 si_get_constbuf_slot(slot
),
1241 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1244 /* SHADER BUFFERS */
1246 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1247 enum pipe_shader_type shader
,
1248 unsigned start_slot
, unsigned count
,
1249 const struct pipe_shader_buffer
*sbuffers
)
1251 struct si_context
*sctx
= (struct si_context
*)ctx
;
1252 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1253 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1256 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1258 for (i
= 0; i
< count
; ++i
) {
1259 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1260 struct r600_resource
*buf
;
1261 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1262 uint32_t *desc
= descs
->list
+ slot
* 4;
1265 if (!sbuffer
|| !sbuffer
->buffer
) {
1266 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1267 memset(desc
, 0, sizeof(uint32_t) * 4);
1268 buffers
->enabled_mask
&= ~(1u << slot
);
1269 sctx
->descriptors_dirty
|=
1270 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1274 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1275 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1278 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1280 desc
[2] = sbuffer
->buffer_size
;
1281 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1282 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1283 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1284 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1285 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1286 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1288 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1289 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1290 buffers
->shader_usage
,
1291 buffers
->priority
, true);
1292 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1294 buffers
->enabled_mask
|= 1u << slot
;
1295 sctx
->descriptors_dirty
|=
1296 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1298 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1299 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1303 void si_get_shader_buffers(struct si_context
*sctx
,
1304 enum pipe_shader_type shader
,
1305 uint start_slot
, uint count
,
1306 struct pipe_shader_buffer
*sbuf
)
1308 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1309 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1311 for (unsigned i
= 0; i
< count
; ++i
) {
1312 si_get_buffer_from_descriptors(
1314 si_get_shaderbuf_slot(start_slot
+ i
),
1315 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1316 &sbuf
[i
].buffer_size
);
1322 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1323 struct pipe_resource
*buffer
,
1324 unsigned stride
, unsigned num_records
,
1325 bool add_tid
, bool swizzle
,
1326 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1328 struct si_context
*sctx
= (struct si_context
*)ctx
;
1329 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1330 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1332 /* The stride field in the resource descriptor has 14 bits */
1333 assert(stride
< (1 << 14));
1335 assert(slot
< descs
->num_elements
);
1336 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1341 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1343 switch (element_size
) {
1345 assert(!"Unsupported ring buffer element size");
1361 switch (index_stride
) {
1363 assert(!"Unsupported ring buffer index stride");
1379 if (sctx
->b
.chip_class
>= VI
&& stride
)
1380 num_records
*= stride
;
1382 /* Set the descriptor. */
1383 uint32_t *desc
= descs
->list
+ slot
*4;
1385 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1386 S_008F04_STRIDE(stride
) |
1387 S_008F04_SWIZZLE_ENABLE(swizzle
);
1388 desc
[2] = num_records
;
1389 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1390 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1391 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1392 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1393 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1394 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1395 S_008F0C_INDEX_STRIDE(index_stride
) |
1396 S_008F0C_ADD_TID_ENABLE(add_tid
);
1398 if (sctx
->b
.chip_class
>= GFX9
)
1399 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1401 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1403 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1404 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1405 (struct r600_resource
*)buffer
,
1406 buffers
->shader_usage
, buffers
->priority
);
1407 buffers
->enabled_mask
|= 1u << slot
;
1409 /* Clear the descriptor. */
1410 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1411 buffers
->enabled_mask
&= ~(1u << slot
);
1414 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1417 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1418 uint32_t *desc
, uint64_t old_buf_va
,
1419 struct pipe_resource
*new_buf
)
1421 /* Retrieve the buffer offset from the descriptor. */
1422 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1424 assert(old_buf_va
<= old_desc_va
);
1425 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1427 /* Update the descriptor. */
1428 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1432 /* INTERNAL CONST BUFFERS */
1434 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1435 const struct pipe_poly_stipple
*state
)
1437 struct si_context
*sctx
= (struct si_context
*)ctx
;
1438 struct pipe_constant_buffer cb
= {};
1439 unsigned stipple
[32];
1442 for (i
= 0; i
< 32; i
++)
1443 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1445 cb
.user_buffer
= stipple
;
1446 cb
.buffer_size
= sizeof(stipple
);
1448 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1451 /* TEXTURE METADATA ENABLE/DISABLE */
1454 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1456 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1457 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1459 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1460 struct si_texture_handle
*, tex_handle
) {
1461 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1462 struct r600_texture
*rtex
;
1464 if (!res
|| res
->target
== PIPE_BUFFER
)
1467 rtex
= (struct r600_texture
*)res
;
1468 if (!color_needs_decompression(rtex
))
1471 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1472 struct si_texture_handle
*, *tex_handle
);
1475 util_dynarray_foreach(&sctx
->resident_img_handles
,
1476 struct si_image_handle
*, img_handle
) {
1477 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1478 struct pipe_resource
*res
= view
->resource
;
1479 struct r600_texture
*rtex
;
1481 if (!res
|| res
->target
== PIPE_BUFFER
)
1484 rtex
= (struct r600_texture
*)res
;
1485 if (!color_needs_decompression(rtex
))
1488 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1489 struct si_image_handle
*, *img_handle
);
1493 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1494 * while the texture is bound, possibly by a different context. In that case,
1495 * call this function to update needs_*_decompress_masks.
1497 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1499 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1500 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1501 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1502 si_update_shader_needs_decompress_mask(sctx
, i
);
1505 si_resident_handles_update_needs_color_decompress(sctx
);
1508 /* BUFFER DISCARD/INVALIDATION */
1510 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1511 static void si_reset_buffer_resources(struct si_context
*sctx
,
1512 struct si_buffer_resources
*buffers
,
1513 unsigned descriptors_idx
,
1515 struct pipe_resource
*buf
,
1517 enum radeon_bo_usage usage
,
1518 enum radeon_bo_priority priority
)
1520 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1521 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1524 unsigned i
= u_bit_scan(&mask
);
1525 if (buffers
->buffers
[i
] == buf
) {
1526 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1529 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1531 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1532 (struct r600_resource
*)buf
,
1533 usage
, priority
, true);
1538 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1541 struct si_context
*sctx
= (struct si_context
*)ctx
;
1542 struct r600_resource
*rbuffer
= r600_resource(buf
);
1544 unsigned num_elems
= sctx
->vertex_elements
?
1545 sctx
->vertex_elements
->count
: 0;
1547 /* We changed the buffer, now we need to bind it where the old one
1548 * was bound. This consists of 2 things:
1549 * 1) Updating the resource descriptor and dirtying it.
1550 * 2) Adding a relocation to the CS, so that it's usable.
1553 /* Vertex buffers. */
1554 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1555 for (i
= 0; i
< num_elems
; i
++) {
1556 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1558 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1560 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1563 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1564 sctx
->vertex_buffers_dirty
= true;
1570 /* Streamout buffers. (other internal buffers can't be invalidated) */
1571 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1572 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1573 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1574 struct si_descriptors
*descs
=
1575 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1577 if (buffers
->buffers
[i
] != buf
)
1580 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1582 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1584 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1585 rbuffer
, buffers
->shader_usage
,
1586 RADEON_PRIO_SHADER_RW_BUFFER
,
1589 /* Update the streamout state. */
1590 if (sctx
->streamout
.begin_emitted
)
1591 si_emit_streamout_end(sctx
);
1592 sctx
->streamout
.append_bitmask
=
1593 sctx
->streamout
.enabled_mask
;
1594 si_streamout_buffers_dirty(sctx
);
1598 /* Constant and shader buffers. */
1599 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1600 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1601 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1602 si_const_and_shader_buffer_descriptors_idx(shader
),
1603 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1605 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1606 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1609 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1610 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1611 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1612 si_const_and_shader_buffer_descriptors_idx(shader
),
1613 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1615 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1616 sctx
->const_and_shader_buffers
[shader
].priority
);
1619 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1620 /* Texture buffers - update bindings. */
1621 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1622 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1623 struct si_descriptors
*descs
=
1624 si_sampler_and_image_descriptors(sctx
, shader
);
1625 unsigned mask
= samplers
->enabled_mask
;
1628 unsigned i
= u_bit_scan(&mask
);
1629 if (samplers
->views
[i
]->texture
== buf
) {
1630 unsigned desc_slot
= si_get_sampler_slot(i
);
1632 si_desc_reset_buffer_offset(ctx
,
1636 sctx
->descriptors_dirty
|=
1637 1u << si_sampler_and_image_descriptors_idx(shader
);
1639 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1640 rbuffer
, RADEON_USAGE_READ
,
1641 RADEON_PRIO_SAMPLER_BUFFER
,
1649 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1650 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1651 struct si_images
*images
= &sctx
->images
[shader
];
1652 struct si_descriptors
*descs
=
1653 si_sampler_and_image_descriptors(sctx
, shader
);
1654 unsigned mask
= images
->enabled_mask
;
1657 unsigned i
= u_bit_scan(&mask
);
1659 if (images
->views
[i
].resource
== buf
) {
1660 unsigned desc_slot
= si_get_image_slot(i
);
1662 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1663 si_mark_image_range_valid(&images
->views
[i
]);
1665 si_desc_reset_buffer_offset(
1666 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1668 sctx
->descriptors_dirty
|=
1669 1u << si_sampler_and_image_descriptors_idx(shader
);
1671 radeon_add_to_buffer_list_check_mem(
1672 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1673 RADEON_USAGE_READWRITE
,
1674 RADEON_PRIO_SAMPLER_BUFFER
, true);
1680 /* Bindless texture handles */
1681 if (rbuffer
->texture_handle_allocated
) {
1682 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1684 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1685 struct si_texture_handle
*, tex_handle
) {
1686 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1687 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1689 if (view
->texture
== buf
) {
1690 si_set_buf_desc_address(rbuffer
,
1693 desc_slot
* 16 + 4);
1695 (*tex_handle
)->desc_dirty
= true;
1696 sctx
->bindless_descriptors_dirty
= true;
1698 radeon_add_to_buffer_list_check_mem(
1699 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1701 RADEON_PRIO_SAMPLER_BUFFER
, true);
1706 /* Bindless image handles */
1707 if (rbuffer
->image_handle_allocated
) {
1708 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1710 util_dynarray_foreach(&sctx
->resident_img_handles
,
1711 struct si_image_handle
*, img_handle
) {
1712 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1713 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1715 if (view
->resource
== buf
) {
1716 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1717 si_mark_image_range_valid(view
);
1719 si_set_buf_desc_address(rbuffer
,
1722 desc_slot
* 16 + 4);
1724 (*img_handle
)->desc_dirty
= true;
1725 sctx
->bindless_descriptors_dirty
= true;
1727 radeon_add_to_buffer_list_check_mem(
1728 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1729 RADEON_USAGE_READWRITE
,
1730 RADEON_PRIO_SAMPLER_BUFFER
, true);
1736 /* Reallocate a buffer a update all resource bindings where the buffer is
1739 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1740 * idle by discarding its contents. Apps usually tell us when to do this using
1741 * map_buffer flags, for example.
1743 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1745 struct si_context
*sctx
= (struct si_context
*)ctx
;
1746 struct r600_resource
*rbuffer
= r600_resource(buf
);
1747 uint64_t old_va
= rbuffer
->gpu_address
;
1749 /* Reallocate the buffer in the same pipe_resource. */
1750 si_alloc_resource(sctx
->screen
, rbuffer
);
1752 si_rebind_buffer(ctx
, buf
, old_va
);
1755 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1757 unsigned num_dwords
)
1759 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1760 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1761 unsigned desc_slot_offset
= desc_slot
* 16;
1765 data
= desc
->list
+ desc_slot_offset
;
1766 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1768 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1769 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1770 S_370_WR_CONFIRM(1) |
1771 S_370_ENGINE_SEL(V_370_ME
));
1772 radeon_emit(cs
, va
);
1773 radeon_emit(cs
, va
>> 32);
1774 radeon_emit_array(cs
, data
, num_dwords
);
1777 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1779 if (!sctx
->bindless_descriptors_dirty
)
1782 /* Wait for graphics/compute to be idle before updating the resident
1783 * descriptors directly in memory, in case the GPU is using them.
1785 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1786 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1787 si_emit_cache_flush(sctx
);
1789 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1790 struct si_texture_handle
*, tex_handle
) {
1791 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1793 if (!(*tex_handle
)->desc_dirty
)
1796 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1797 (*tex_handle
)->desc_dirty
= false;
1800 util_dynarray_foreach(&sctx
->resident_img_handles
,
1801 struct si_image_handle
*, img_handle
) {
1802 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1804 if (!(*img_handle
)->desc_dirty
)
1807 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1808 (*img_handle
)->desc_dirty
= false;
1811 /* Invalidate L1 because it doesn't know that L2 changed. */
1812 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1813 si_emit_cache_flush(sctx
);
1815 sctx
->bindless_descriptors_dirty
= false;
1818 /* Update mutable image descriptor fields of all resident textures. */
1819 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1820 struct si_texture_handle
*tex_handle
)
1822 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1823 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1824 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1825 uint32_t desc_list
[16];
1827 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1830 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1831 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1832 desc
->list
+ desc_slot_offset
);
1834 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1835 sizeof(desc_list
))) {
1836 tex_handle
->desc_dirty
= true;
1837 sctx
->bindless_descriptors_dirty
= true;
1841 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1842 struct si_image_handle
*img_handle
)
1844 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1845 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1846 struct pipe_image_view
*view
= &img_handle
->view
;
1847 uint32_t desc_list
[8];
1849 if (view
->resource
->target
== PIPE_BUFFER
)
1852 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1854 si_set_shader_image_desc(sctx
, view
, true,
1855 desc
->list
+ desc_slot_offset
);
1857 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1858 sizeof(desc_list
))) {
1859 img_handle
->desc_dirty
= true;
1860 sctx
->bindless_descriptors_dirty
= true;
1864 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1866 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1867 struct si_texture_handle
*, tex_handle
) {
1868 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1871 util_dynarray_foreach(&sctx
->resident_img_handles
,
1872 struct si_image_handle
*, img_handle
) {
1873 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1876 si_upload_bindless_descriptors(sctx
);
1879 /* Update mutable image descriptor fields of all bound textures. */
1880 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1884 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1885 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1886 struct si_images
*images
= &sctx
->images
[shader
];
1890 mask
= images
->enabled_mask
;
1892 unsigned i
= u_bit_scan(&mask
);
1893 struct pipe_image_view
*view
= &images
->views
[i
];
1895 if (!view
->resource
||
1896 view
->resource
->target
== PIPE_BUFFER
)
1899 si_set_shader_image(sctx
, shader
, i
, view
, true);
1902 /* Sampler views. */
1903 mask
= samplers
->enabled_mask
;
1905 unsigned i
= u_bit_scan(&mask
);
1906 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1910 view
->texture
->target
== PIPE_BUFFER
)
1913 si_set_sampler_view(sctx
, shader
, i
,
1914 samplers
->views
[i
], true);
1917 si_update_shader_needs_decompress_mask(sctx
, shader
);
1920 si_update_all_resident_texture_descriptors(sctx
);
1923 /* SHADER USER DATA */
1925 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1928 sctx
->shader_pointers_dirty
|=
1929 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1930 SI_NUM_SHADER_DESCS
);
1932 if (shader
== PIPE_SHADER_VERTEX
)
1933 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1935 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1938 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1940 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1941 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1942 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1943 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1944 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1947 /* Set a base register address for user data constants in the given shader.
1948 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1950 static void si_set_user_data_base(struct si_context
*sctx
,
1951 unsigned shader
, uint32_t new_base
)
1953 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1955 if (*base
!= new_base
) {
1959 si_mark_shader_pointers_dirty(sctx
, shader
);
1961 if (shader
== PIPE_SHADER_VERTEX
)
1962 sctx
->last_vs_state
= ~0;
1967 /* This must be called when these shaders are changed from non-NULL to NULL
1970 * - tessellation control shader
1971 * - tessellation evaluation shader
1973 void si_shader_change_notify(struct si_context
*sctx
)
1975 /* VS can be bound as VS, ES, or LS. */
1976 if (sctx
->tes_shader
.cso
) {
1977 if (sctx
->b
.chip_class
>= GFX9
) {
1978 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1979 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1981 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1982 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1984 } else if (sctx
->gs_shader
.cso
) {
1985 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1986 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1988 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1989 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1992 /* TES can be bound as ES, VS, or not bound. */
1993 if (sctx
->tes_shader
.cso
) {
1994 if (sctx
->gs_shader
.cso
)
1995 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1996 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1998 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1999 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2001 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2005 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2007 unsigned pointer_count
)
2009 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2010 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2013 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2014 struct radeon_winsys_cs
*cs
,
2017 radeon_emit(cs
, va
);
2019 if (HAVE_32BIT_POINTERS
)
2020 assert((va
>> 32) == sscreen
->info
.address32_hi
);
2022 radeon_emit(cs
, va
>> 32);
2025 static void si_emit_shader_pointer(struct si_context
*sctx
,
2026 struct si_descriptors
*desc
,
2029 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2030 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2032 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2033 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2036 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2037 unsigned pointer_mask
,
2043 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2044 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2048 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2050 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2051 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2053 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2054 for (int i
= 0; i
< count
; i
++)
2055 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2056 descs
[i
].gpu_address
);
2060 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2061 unsigned pointer_mask
,
2067 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2068 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2071 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2072 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2074 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2075 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
->gpu_address
);
2079 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2080 struct si_descriptors
*descs
)
2082 if (sctx
->b
.chip_class
== GFX9
) {
2083 /* Broadcast it to all shader stages. */
2084 si_emit_shader_pointer(sctx
, descs
,
2085 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2089 si_emit_shader_pointer(sctx
, descs
,
2090 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2091 si_emit_shader_pointer(sctx
, descs
,
2092 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2093 si_emit_shader_pointer(sctx
, descs
,
2094 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2095 si_emit_shader_pointer(sctx
, descs
,
2096 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2097 si_emit_shader_pointer(sctx
, descs
,
2098 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2099 si_emit_shader_pointer(sctx
, descs
,
2100 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2103 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2104 struct r600_atom
*atom
)
2106 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2108 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2109 si_emit_global_shader_pointers(sctx
,
2110 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2113 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2114 sh_base
[PIPE_SHADER_VERTEX
]);
2115 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2116 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2117 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2118 sh_base
[PIPE_SHADER_FRAGMENT
]);
2119 if (HAVE_32BIT_POINTERS
|| sctx
->b
.chip_class
<= VI
) {
2120 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2121 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2122 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2123 sh_base
[PIPE_SHADER_GEOMETRY
]);
2125 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2126 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2127 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2128 sh_base
[PIPE_SHADER_GEOMETRY
]);
2131 sctx
->shader_pointers_dirty
&=
2132 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2134 if (sctx
->vertex_buffer_pointer_dirty
) {
2135 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2137 /* Find the location of the VB descriptor pointer. */
2138 /* TODO: In the future, the pointer will be packed in unused
2139 * bits of the first 2 VB descriptors. */
2140 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2141 if (sctx
->b
.chip_class
>= GFX9
) {
2142 if (sctx
->tes_shader
.cso
)
2143 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2144 else if (sctx
->gs_shader
.cso
)
2145 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2148 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2149 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2150 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2151 sctx
->vb_descriptors_buffer
->gpu_address
+
2152 sctx
->vb_descriptors_offset
);
2153 sctx
->vertex_buffer_pointer_dirty
= false;
2156 if (sctx
->graphics_bindless_pointer_dirty
) {
2157 si_emit_global_shader_pointers(sctx
,
2158 &sctx
->bindless_descriptors
);
2159 sctx
->graphics_bindless_pointer_dirty
= false;
2163 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2165 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2167 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2168 R_00B900_COMPUTE_USER_DATA_0
);
2169 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2171 if (sctx
->compute_bindless_pointer_dirty
) {
2172 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2173 sctx
->compute_bindless_pointer_dirty
= false;
2179 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2180 struct si_descriptors
*desc
,
2181 short shader_userdata_rel_index
,
2182 unsigned num_elements
)
2184 MAYBE_UNUSED
unsigned desc_slot
;
2186 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2187 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2189 /* The first bindless descriptor is stored at slot 1, because 0 is not
2190 * considered to be a valid handle.
2192 sctx
->num_bindless_descriptors
= 1;
2194 /* Track which bindless slots are used (or not). */
2195 util_idalloc_init(&sctx
->bindless_used_slots
);
2196 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2198 /* Reserve slot 0 because it's an invalid handle for bindless. */
2199 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2200 assert(desc_slot
== 0);
2203 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2205 si_release_descriptors(&sctx
->bindless_descriptors
);
2206 util_idalloc_fini(&sctx
->bindless_used_slots
);
2209 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2211 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2214 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2215 if (desc_slot
>= desc
->num_elements
) {
2216 /* The array of bindless descriptors is full, resize it. */
2217 unsigned slot_size
= desc
->element_dw_size
* 4;
2218 unsigned new_num_elements
= desc
->num_elements
* 2;
2220 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2221 new_num_elements
* slot_size
);
2222 desc
->num_elements
= new_num_elements
;
2223 desc
->num_active_slots
= new_num_elements
;
2231 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2234 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2235 unsigned desc_slot
, desc_slot_offset
;
2237 /* Find a free slot. */
2238 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2240 /* For simplicity, sampler and image bindless descriptors use fixed
2241 * 16-dword slots for now. Image descriptors only need 8-dword but this
2242 * doesn't really matter because no real apps use image handles.
2244 desc_slot_offset
= desc_slot
* 16;
2246 /* Copy the descriptor into the array. */
2247 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2249 /* Re-upload the whole array of bindless descriptors into a new buffer.
2251 if (!si_upload_descriptors(sctx
, desc
))
2254 /* Make sure to re-emit the shader pointers for all stages. */
2255 sctx
->graphics_bindless_pointer_dirty
= true;
2256 sctx
->compute_bindless_pointer_dirty
= true;
2261 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2263 struct pipe_resource
*resource
,
2267 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2268 struct r600_resource
*buf
= r600_resource(resource
);
2269 unsigned desc_slot_offset
= desc_slot
* 16;
2270 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2271 uint64_t old_desc_va
;
2273 assert(resource
->target
== PIPE_BUFFER
);
2275 /* Retrieve the old buffer addr from the descriptor. */
2276 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2278 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2279 /* The buffer has been invalidated when the handle wasn't
2280 * resident, update the descriptor and the dirty flag.
2282 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2288 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2289 struct pipe_sampler_view
*view
,
2290 const struct pipe_sampler_state
*state
)
2292 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2293 struct si_context
*sctx
= (struct si_context
*)ctx
;
2294 struct si_texture_handle
*tex_handle
;
2295 struct si_sampler_state
*sstate
;
2296 uint32_t desc_list
[16];
2299 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2303 memset(desc_list
, 0, sizeof(desc_list
));
2304 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2306 sstate
= ctx
->create_sampler_state(ctx
, state
);
2312 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2313 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2314 ctx
->delete_sampler_state(ctx
, sstate
);
2316 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2318 if (!tex_handle
->desc_slot
) {
2323 handle
= tex_handle
->desc_slot
;
2325 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2326 (void *)(uintptr_t)handle
,
2332 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2334 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2339 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2341 struct si_context
*sctx
= (struct si_context
*)ctx
;
2342 struct si_texture_handle
*tex_handle
;
2343 struct hash_entry
*entry
;
2345 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2346 (void *)(uintptr_t)handle
);
2350 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2352 /* Allow this descriptor slot to be re-used. */
2353 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2355 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2356 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2360 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2361 uint64_t handle
, bool resident
)
2363 struct si_context
*sctx
= (struct si_context
*)ctx
;
2364 struct si_texture_handle
*tex_handle
;
2365 struct si_sampler_view
*sview
;
2366 struct hash_entry
*entry
;
2368 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2369 (void *)(uintptr_t)handle
);
2373 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2374 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2377 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2378 struct r600_texture
*rtex
=
2379 (struct r600_texture
*)sview
->base
.texture
;
2381 if (depth_needs_decompression(rtex
)) {
2382 util_dynarray_append(
2383 &sctx
->resident_tex_needs_depth_decompress
,
2384 struct si_texture_handle
*,
2388 if (color_needs_decompression(rtex
)) {
2389 util_dynarray_append(
2390 &sctx
->resident_tex_needs_color_decompress
,
2391 struct si_texture_handle
*,
2395 if (rtex
->dcc_offset
&&
2396 p_atomic_read(&rtex
->framebuffers_bound
))
2397 sctx
->need_check_render_feedback
= true;
2399 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2401 si_update_bindless_buffer_descriptor(sctx
,
2402 tex_handle
->desc_slot
,
2403 sview
->base
.texture
,
2404 sview
->base
.u
.buf
.offset
,
2405 &tex_handle
->desc_dirty
);
2408 /* Re-upload the descriptor if it has been updated while it
2411 if (tex_handle
->desc_dirty
)
2412 sctx
->bindless_descriptors_dirty
= true;
2414 /* Add the texture handle to the per-context list. */
2415 util_dynarray_append(&sctx
->resident_tex_handles
,
2416 struct si_texture_handle
*, tex_handle
);
2418 /* Add the buffers to the current CS in case si_begin_new_cs()
2419 * is not going to be called.
2421 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2423 sview
->is_stencil_sampler
, false);
2425 /* Remove the texture handle from the per-context list. */
2426 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2427 struct si_texture_handle
*,
2430 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2431 util_dynarray_delete_unordered(
2432 &sctx
->resident_tex_needs_depth_decompress
,
2433 struct si_texture_handle
*, tex_handle
);
2435 util_dynarray_delete_unordered(
2436 &sctx
->resident_tex_needs_color_decompress
,
2437 struct si_texture_handle
*, tex_handle
);
2442 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2443 const struct pipe_image_view
*view
)
2445 struct si_context
*sctx
= (struct si_context
*)ctx
;
2446 struct si_image_handle
*img_handle
;
2447 uint32_t desc_list
[8];
2450 if (!view
|| !view
->resource
)
2453 img_handle
= CALLOC_STRUCT(si_image_handle
);
2457 memset(desc_list
, 0, sizeof(desc_list
));
2458 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2460 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2462 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2464 if (!img_handle
->desc_slot
) {
2469 handle
= img_handle
->desc_slot
;
2471 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2472 (void *)(uintptr_t)handle
,
2478 util_copy_image_view(&img_handle
->view
, view
);
2480 r600_resource(view
->resource
)->image_handle_allocated
= true;
2485 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2487 struct si_context
*sctx
= (struct si_context
*)ctx
;
2488 struct si_image_handle
*img_handle
;
2489 struct hash_entry
*entry
;
2491 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2492 (void *)(uintptr_t)handle
);
2496 img_handle
= (struct si_image_handle
*)entry
->data
;
2498 util_copy_image_view(&img_handle
->view
, NULL
);
2499 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2503 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2504 uint64_t handle
, unsigned access
,
2507 struct si_context
*sctx
= (struct si_context
*)ctx
;
2508 struct si_image_handle
*img_handle
;
2509 struct pipe_image_view
*view
;
2510 struct r600_resource
*res
;
2511 struct hash_entry
*entry
;
2513 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2514 (void *)(uintptr_t)handle
);
2518 img_handle
= (struct si_image_handle
*)entry
->data
;
2519 view
= &img_handle
->view
;
2520 res
= (struct r600_resource
*)view
->resource
;
2523 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2524 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2525 unsigned level
= view
->u
.tex
.level
;
2527 if (color_needs_decompression(rtex
)) {
2528 util_dynarray_append(
2529 &sctx
->resident_img_needs_color_decompress
,
2530 struct si_image_handle
*,
2534 if (vi_dcc_enabled(rtex
, level
) &&
2535 p_atomic_read(&rtex
->framebuffers_bound
))
2536 sctx
->need_check_render_feedback
= true;
2538 si_update_bindless_image_descriptor(sctx
, img_handle
);
2540 si_update_bindless_buffer_descriptor(sctx
,
2541 img_handle
->desc_slot
,
2544 &img_handle
->desc_dirty
);
2547 /* Re-upload the descriptor if it has been updated while it
2550 if (img_handle
->desc_dirty
)
2551 sctx
->bindless_descriptors_dirty
= true;
2553 /* Add the image handle to the per-context list. */
2554 util_dynarray_append(&sctx
->resident_img_handles
,
2555 struct si_image_handle
*, img_handle
);
2557 /* Add the buffers to the current CS in case si_begin_new_cs()
2558 * is not going to be called.
2560 si_sampler_view_add_buffer(sctx
, view
->resource
,
2561 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2562 RADEON_USAGE_READWRITE
:
2563 RADEON_USAGE_READ
, false, false);
2565 /* Remove the image handle from the per-context list. */
2566 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2567 struct si_image_handle
*,
2570 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2571 util_dynarray_delete_unordered(
2572 &sctx
->resident_img_needs_color_decompress
,
2573 struct si_image_handle
*,
2580 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2582 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2584 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2585 sizeof(struct si_texture_handle
*);
2586 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2587 sizeof(struct si_image_handle
*);
2589 /* Add all resident texture handles. */
2590 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2591 struct si_texture_handle
*, tex_handle
) {
2592 struct si_sampler_view
*sview
=
2593 (struct si_sampler_view
*)(*tex_handle
)->view
;
2595 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2597 sview
->is_stencil_sampler
, false);
2600 /* Add all resident image handles. */
2601 util_dynarray_foreach(&sctx
->resident_img_handles
,
2602 struct si_image_handle
*, img_handle
) {
2603 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2605 si_sampler_view_add_buffer(sctx
, view
->resource
,
2606 RADEON_USAGE_READWRITE
,
2610 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2611 num_resident_img_handles
;
2614 /* INIT/DEINIT/UPLOAD */
2616 void si_init_all_descriptors(struct si_context
*sctx
)
2620 #if !HAVE_32BIT_POINTERS
2621 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2624 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2625 bool is_2nd
= sctx
->b
.chip_class
>= GFX9
&&
2626 (i
== PIPE_SHADER_TESS_CTRL
||
2627 i
== PIPE_SHADER_GEOMETRY
);
2628 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2629 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2631 struct si_descriptors
*desc
;
2634 if (i
== PIPE_SHADER_TESS_CTRL
) {
2635 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2636 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2637 } else { /* PIPE_SHADER_GEOMETRY */
2638 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2639 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2642 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2644 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2645 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2646 num_buffer_slots
, rel_dw_offset
,
2647 RADEON_USAGE_READWRITE
,
2649 RADEON_PRIO_SHADER_RW_BUFFER
,
2650 RADEON_PRIO_CONST_BUFFER
);
2651 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2654 #if HAVE_32BIT_POINTERS
2655 if (i
== PIPE_SHADER_TESS_CTRL
) {
2656 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2657 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2658 } else { /* PIPE_SHADER_GEOMETRY */
2659 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2660 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2663 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2666 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2669 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2670 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2673 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2674 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2675 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2676 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2679 si_init_buffer_resources(&sctx
->rw_buffers
,
2680 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2681 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2682 /* The second set of usage/priority is used by
2683 * const buffers in RW buffer slots. */
2684 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2685 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2686 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2688 /* Initialize an array of 1024 bindless descriptors, when the limit is
2689 * reached, just make it larger and re-upload the whole array.
2691 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2692 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2695 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2697 /* Set pipe_context functions. */
2698 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2699 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2700 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2701 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2702 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2703 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2704 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2705 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2706 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2707 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2708 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2709 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2710 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2711 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2713 /* Shader user data. */
2714 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2715 si_emit_graphics_shader_pointers
);
2717 /* Set default and immutable mappings. */
2718 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2720 if (sctx
->b
.chip_class
>= GFX9
) {
2721 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2722 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2723 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2724 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2726 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2727 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2728 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2729 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2731 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2734 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2736 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2738 /* Assume nothing will go wrong: */
2739 sctx
->shader_pointers_dirty
|= dirty
;
2742 unsigned i
= u_bit_scan(&dirty
);
2744 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2748 sctx
->descriptors_dirty
&= ~mask
;
2750 si_upload_bindless_descriptors(sctx
);
2755 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2757 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2758 return si_upload_shader_descriptors(sctx
, mask
);
2761 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2763 /* Does not update rw_buffers as that is not needed for compute shaders
2764 * and the input buffer is using the same SGPR's anyway.
2766 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2767 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2768 return si_upload_shader_descriptors(sctx
, mask
);
2771 void si_release_all_descriptors(struct si_context
*sctx
)
2775 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2776 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2777 si_const_and_shader_buffer_descriptors(sctx
, i
));
2778 si_release_sampler_views(&sctx
->samplers
[i
]);
2779 si_release_image_views(&sctx
->images
[i
]);
2781 si_release_buffer_resources(&sctx
->rw_buffers
,
2782 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2783 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2784 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2786 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2787 si_release_descriptors(&sctx
->descriptors
[i
]);
2789 r600_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2790 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2792 si_release_bindless_descriptors(sctx
);
2795 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2799 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2800 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2801 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2802 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2804 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2805 si_vertex_buffers_begin_new_cs(sctx
);
2807 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2808 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2809 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2811 si_shader_pointers_begin_new_cs(sctx
);
2814 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2815 uint64_t new_active_mask
)
2817 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2819 /* Ignore no-op updates and updates that disable all slots. */
2820 if (!new_active_mask
||
2821 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2822 desc
->num_active_slots
))
2826 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2827 assert(new_active_mask
== 0);
2829 /* Upload/dump descriptors if slots are being enabled. */
2830 if (first
< desc
->first_active_slot
||
2831 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2832 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2834 desc
->first_active_slot
= first
;
2835 desc
->num_active_slots
= count
;
2838 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2839 struct si_shader_selector
*sel
)
2844 si_set_active_descriptors(sctx
,
2845 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2846 sel
->active_const_and_shader_buffers
);
2847 si_set_active_descriptors(sctx
,
2848 si_sampler_and_image_descriptors_idx(sel
->type
),
2849 sel
->active_samplers_and_images
);