2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
57 #include "si_compute.h"
59 #include "util/format/u_format.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
65 /* NULL image and buffer descriptor for textures (alpha = 1) and images
68 * For images, all fields must be zero except for the swizzle, which
69 * supports arbitrary combinations of 0s and 1s. The texture type must be
70 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
72 * For buffers, all fields must be zero. If they are not, the hw hangs.
74 * This is the only reason why the buffer descriptor must be in words [4:7].
76 static uint32_t null_texture_descriptor
[8] = {
77 0, 0, 0, S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) | S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
78 /* the rest must contain zeros, which is also used by the buffer
82 static uint32_t null_image_descriptor
[8] = {
83 0, 0, 0, S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
90 uint64_t va
= desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
92 /* Sign-extend the 48-bit address. */
94 va
= (int64_t)va
>> 16;
98 static void si_init_descriptor_list(uint32_t *desc_list
, unsigned element_dw_size
,
99 unsigned num_elements
, const uint32_t *null_descriptor
)
103 /* Initialize the array to NULL descriptors if the element size is 8. */
104 if (null_descriptor
) {
105 assert(element_dw_size
% 8 == 0);
106 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
107 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
111 static void si_init_descriptors(struct si_descriptors
*desc
, short shader_userdata_rel_index
,
112 unsigned element_dw_size
, unsigned num_elements
)
114 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
115 desc
->element_dw_size
= element_dw_size
;
116 desc
->num_elements
= num_elements
;
117 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
118 desc
->slot_index_to_bind_directly
= -1;
121 static void si_release_descriptors(struct si_descriptors
*desc
)
123 si_resource_reference(&desc
->buffer
, NULL
);
127 static bool si_upload_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
)
129 unsigned slot_size
= desc
->element_dw_size
* 4;
130 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
131 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
133 /* Skip the upload if no shader is using the descriptors. dirty_mask
134 * will stay dirty and the descriptors will be uploaded when there is
135 * a shader using them.
140 /* If there is just one active descriptor, bind it directly. */
141 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
142 desc
->num_active_slots
== 1) {
143 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
* desc
->element_dw_size
];
145 /* The buffer is already in the buffer list. */
146 si_resource_reference(&desc
->buffer
, NULL
);
147 desc
->gpu_list
= NULL
;
148 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
149 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
154 unsigned buffer_offset
;
155 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
156 si_optimal_tcc_alignment(sctx
, upload_size
), &buffer_offset
,
157 (struct pipe_resource
**)&desc
->buffer
, (void **)&ptr
);
159 desc
->gpu_address
= 0;
160 return false; /* skip the draw call */
163 util_memcpy_cpu_to_le32(ptr
, (char *)desc
->list
+ first_slot_offset
, upload_size
);
164 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
166 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
167 RADEON_PRIO_DESCRIPTORS
);
169 /* The shader pointer should point to slot 0. */
170 buffer_offset
-= first_slot_offset
;
171 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
173 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
174 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
175 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
177 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
181 static void si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
186 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
, RADEON_USAGE_READ
,
187 RADEON_PRIO_DESCRIPTORS
);
192 static inline enum radeon_bo_priority
si_get_sampler_view_priority(struct si_resource
*res
)
194 if (res
->b
.b
.target
== PIPE_BUFFER
)
195 return RADEON_PRIO_SAMPLER_BUFFER
;
197 if (res
->b
.b
.nr_samples
> 1)
198 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
200 return RADEON_PRIO_SAMPLER_TEXTURE
;
203 static struct si_descriptors
*si_sampler_and_image_descriptors(struct si_context
*sctx
,
206 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
209 static void si_release_sampler_views(struct si_samplers
*samplers
)
213 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
214 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
218 static void si_sampler_view_add_buffer(struct si_context
*sctx
, struct pipe_resource
*resource
,
219 enum radeon_bo_usage usage
, bool is_stencil_sampler
,
222 struct si_texture
*tex
= (struct si_texture
*)resource
;
223 enum radeon_bo_priority priority
;
228 /* Use the flushed depth texture if direct sampling is unsupported. */
229 if (resource
->target
!= PIPE_BUFFER
&& tex
->is_depth
&&
230 !si_can_sample_zs(tex
, is_stencil_sampler
))
231 tex
= tex
->flushed_depth_texture
;
233 priority
= si_get_sampler_view_priority(&tex
->buffer
);
234 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
, check_mem
);
236 if (resource
->target
== PIPE_BUFFER
)
239 /* Add separate DCC. */
240 if (tex
->dcc_separate_buffer
) {
241 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
, usage
,
242 RADEON_PRIO_SEPARATE_META
, check_mem
);
246 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
, struct si_samplers
*samplers
)
248 unsigned mask
= samplers
->enabled_mask
;
250 /* Add buffers to the CS. */
252 int i
= u_bit_scan(&mask
);
253 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
255 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
256 sview
->is_stencil_sampler
, false);
260 static bool si_sampler_views_check_encrypted(struct si_context
*sctx
, struct si_samplers
*samplers
,
261 unsigned samplers_declared
)
263 unsigned mask
= samplers
->enabled_mask
& samplers_declared
;
265 /* Verify if a samplers uses an encrypted resource */
267 int i
= u_bit_scan(&mask
);
268 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
270 struct si_resource
*res
= si_resource(sview
->base
.texture
);
271 if (res
->flags
& RADEON_FLAG_ENCRYPTED
)
277 /* Set buffer descriptor fields that can be changed by reallocations. */
278 static void si_set_buf_desc_address(struct si_resource
*buf
, uint64_t offset
, uint32_t *state
)
280 uint64_t va
= buf
->gpu_address
+ offset
;
283 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
284 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
287 /* Set texture descriptor fields that can be changed by reallocations.
290 * \param base_level_info information of the level of BASE_ADDRESS
291 * \param base_level the level of BASE_ADDRESS
292 * \param first_level pipe_sampler_view.u.tex.first_level
293 * \param block_width util_format_get_blockwidth()
294 * \param is_stencil select between separate Z & Stencil
295 * \param state descriptor to update
297 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
, struct si_texture
*tex
,
298 const struct legacy_surf_level
*base_level_info
,
299 unsigned base_level
, unsigned first_level
, unsigned block_width
,
300 bool is_stencil
, bool force_dcc_off
, uint32_t *state
)
302 uint64_t va
, meta_va
= 0;
304 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
305 tex
= tex
->flushed_depth_texture
;
309 va
= tex
->buffer
.gpu_address
;
311 if (sscreen
->info
.chip_class
>= GFX9
) {
312 /* Only stencil_offset needs to be added here. */
314 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
316 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
318 va
+= base_level_info
->offset
;
322 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
323 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
325 /* Only macrotiled modes can set tile swizzle.
326 * GFX9 doesn't use (legacy) base_level_info.
328 if (sscreen
->info
.chip_class
>= GFX9
|| base_level_info
->mode
== RADEON_SURF_MODE_2D
)
329 state
[0] |= tex
->surface
.tile_swizzle
;
331 if (sscreen
->info
.chip_class
>= GFX8
) {
332 state
[6] &= C_008F28_COMPRESSION_EN
;
334 if (!force_dcc_off
&& vi_dcc_enabled(tex
, first_level
)) {
336 (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
;
338 if (sscreen
->info
.chip_class
== GFX8
) {
339 meta_va
+= base_level_info
->dcc_offset
;
340 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
343 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
344 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
345 meta_va
|= dcc_tile_swizzle
;
346 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
347 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
348 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
352 state
[6] |= S_008F28_COMPRESSION_EN(1);
355 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
356 state
[7] = meta_va
>> 8;
358 if (sscreen
->info
.chip_class
>= GFX10
) {
359 state
[3] &= C_00A00C_SW_MODE
;
362 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
364 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
367 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
& C_00A018_META_PIPE_ALIGNED
;
370 struct gfx9_surf_meta_flags meta
= {
375 if (tex
->surface
.dcc_offset
)
376 meta
= tex
->surface
.u
.gfx9
.dcc
;
378 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
379 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
382 state
[7] = meta_va
>> 16;
383 } else if (sscreen
->info
.chip_class
== GFX9
) {
384 state
[3] &= C_008F1C_SW_MODE
;
385 state
[4] &= C_008F20_PITCH
;
388 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
389 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
391 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
392 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
396 C_008F24_META_DATA_ADDRESS
& C_008F24_META_PIPE_ALIGNED
& C_008F24_META_RB_ALIGNED
;
398 struct gfx9_surf_meta_flags meta
= {
403 if (tex
->surface
.dcc_offset
)
404 meta
= tex
->surface
.u
.gfx9
.dcc
;
406 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
407 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
408 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
412 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
413 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
415 state
[3] &= C_008F1C_TILING_INDEX
;
416 state
[3] |= S_008F1C_TILING_INDEX(index
);
417 state
[4] &= C_008F20_PITCH
;
418 state
[4] |= S_008F20_PITCH(pitch
- 1);
422 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
423 struct si_sampler_view
*sview
, struct si_texture
*tex
,
426 if (sview
&& sview
->is_integer
)
427 memcpy(desc
, sstate
->integer_val
, 4 * 4);
428 else if (tex
&& tex
->upgraded_depth
&& (!sview
|| !sview
->is_stencil_sampler
))
429 memcpy(desc
, sstate
->upgraded_depth_val
, 4 * 4);
431 memcpy(desc
, sstate
->val
, 4 * 4);
434 static void si_set_sampler_view_desc(struct si_context
*sctx
, struct si_sampler_view
*sview
,
435 struct si_sampler_state
*sstate
, uint32_t *desc
)
437 struct pipe_sampler_view
*view
= &sview
->base
;
438 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
439 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
441 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
442 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
443 if (!si_texture_disable_dcc(sctx
, tex
))
444 si_decompress_dcc(sctx
, tex
);
446 sview
->dcc_incompatible
= false;
449 assert(tex
); /* views with texture == NULL aren't supported */
450 memcpy(desc
, sview
->state
, 8 * 4);
453 si_set_buf_desc_address(&tex
->buffer
, sview
->base
.u
.buf
.offset
, desc
+ 4);
455 bool is_separate_stencil
= tex
->db_compatible
&& sview
->is_stencil_sampler
;
457 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
, sview
->base_level_info
, sview
->base_level
,
458 sview
->base
.u
.tex
.first_level
, sview
->block_width
,
459 is_separate_stencil
, false, desc
);
462 if (!is_buffer
&& tex
->surface
.fmask_size
) {
463 memcpy(desc
+ 8, sview
->fmask_state
, 8 * 4);
465 /* Disable FMASK and bind sampler state in [12:15]. */
466 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
469 si_set_sampler_state_desc(sstate
, sview
, is_buffer
? NULL
: tex
, desc
+ 12);
473 static bool color_needs_decompression(struct si_texture
*tex
)
475 return tex
->surface
.fmask_size
||
476 (tex
->dirty_level_mask
&& (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
479 static bool depth_needs_decompression(struct si_texture
*tex
)
481 /* If the depth/stencil texture is TC-compatible, no decompression
482 * will be done. The decompression function will only flush DB caches
483 * to make it coherent with shaders. That's necessary because the driver
484 * doesn't flush DB caches in any other case.
486 return tex
->db_compatible
;
489 static void si_set_sampler_view(struct si_context
*sctx
, unsigned shader
, unsigned slot
,
490 struct pipe_sampler_view
*view
, bool disallow_early_out
)
492 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
493 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
494 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
495 unsigned desc_slot
= si_get_sampler_slot(slot
);
496 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
498 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
502 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
504 si_set_sampler_view_desc(sctx
, sview
, samplers
->sampler_states
[slot
], desc
);
506 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
507 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
508 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
509 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
511 if (depth_needs_decompression(tex
)) {
512 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
514 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
516 if (color_needs_decompression(tex
)) {
517 samplers
->needs_color_decompress_mask
|= 1u << slot
;
519 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
522 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
) &&
523 p_atomic_read(&tex
->framebuffers_bound
))
524 sctx
->need_check_render_feedback
= true;
527 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
528 samplers
->enabled_mask
|= 1u << slot
;
530 /* Since this can flush, it must be done after enabled_mask is
532 si_sampler_view_add_buffer(sctx
, view
->texture
, RADEON_USAGE_READ
, sview
->is_stencil_sampler
,
535 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
536 memcpy(desc
, null_texture_descriptor
, 8 * 4);
537 /* Only clear the lower dwords of FMASK. */
538 memcpy(desc
+ 8, null_texture_descriptor
, 4 * 4);
539 /* Re-set the sampler state if we are transitioning from FMASK. */
540 if (samplers
->sampler_states
[slot
])
541 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
, desc
+ 12);
543 samplers
->enabled_mask
&= ~(1u << slot
);
544 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
545 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
548 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
551 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
, unsigned shader
)
553 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
554 unsigned shader_bit
= 1 << shader
;
556 if (samplers
->needs_depth_decompress_mask
|| samplers
->needs_color_decompress_mask
||
557 sctx
->images
[shader
].needs_color_decompress_mask
)
558 sctx
->shader_needs_decompress_mask
|= shader_bit
;
560 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
563 static void si_set_sampler_views(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
564 unsigned start
, unsigned count
, struct pipe_sampler_view
**views
)
566 struct si_context
*sctx
= (struct si_context
*)ctx
;
569 if (!count
|| shader
>= SI_NUM_SHADERS
)
573 for (i
= 0; i
< count
; i
++)
574 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
576 for (i
= 0; i
< count
; i
++)
577 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
580 si_update_shader_needs_decompress_mask(sctx
, shader
);
583 static void si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
585 unsigned mask
= samplers
->enabled_mask
;
588 int i
= u_bit_scan(&mask
);
589 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
591 if (res
&& res
->target
!= PIPE_BUFFER
) {
592 struct si_texture
*tex
= (struct si_texture
*)res
;
594 if (color_needs_decompression(tex
)) {
595 samplers
->needs_color_decompress_mask
|= 1u << i
;
597 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
605 static void si_release_image_views(struct si_images
*images
)
609 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
610 struct pipe_image_view
*view
= &images
->views
[i
];
612 pipe_resource_reference(&view
->resource
, NULL
);
616 static void si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
618 uint mask
= images
->enabled_mask
;
620 /* Add buffers to the CS. */
622 int i
= u_bit_scan(&mask
);
623 struct pipe_image_view
*view
= &images
->views
[i
];
625 assert(view
->resource
);
627 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
631 static bool si_image_views_check_encrypted(struct si_context
*sctx
, struct si_images
*images
,
632 unsigned images_declared
)
634 uint mask
= images
->enabled_mask
& images_declared
;
637 int i
= u_bit_scan(&mask
);
638 struct pipe_image_view
*view
= &images
->views
[i
];
640 assert(view
->resource
);
642 struct si_texture
*tex
= (struct si_texture
*)view
->resource
;
643 if (tex
->buffer
.flags
& RADEON_FLAG_ENCRYPTED
)
649 static void si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
651 struct si_images
*images
= &ctx
->images
[shader
];
653 if (images
->enabled_mask
& (1u << slot
)) {
654 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
655 unsigned desc_slot
= si_get_image_slot(slot
);
657 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
658 images
->needs_color_decompress_mask
&= ~(1 << slot
);
660 memcpy(descs
->list
+ desc_slot
* 8, null_image_descriptor
, 8 * 4);
661 images
->enabled_mask
&= ~(1u << slot
);
662 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
666 static void si_mark_image_range_valid(const struct pipe_image_view
*view
)
668 struct si_resource
*res
= si_resource(view
->resource
);
670 if (res
->b
.b
.target
!= PIPE_BUFFER
)
673 util_range_add(&res
->b
.b
, &res
->valid_buffer_range
, view
->u
.buf
.offset
,
674 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
677 static void si_set_shader_image_desc(struct si_context
*ctx
, const struct pipe_image_view
*view
,
678 bool skip_decompress
, uint32_t *desc
, uint32_t *fmask_desc
)
680 struct si_screen
*screen
= ctx
->screen
;
681 struct si_resource
*res
;
683 res
= si_resource(view
->resource
);
685 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
686 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
687 si_mark_image_range_valid(view
);
689 si_make_buffer_descriptor(screen
, res
, view
->format
, view
->u
.buf
.offset
, view
->u
.buf
.size
,
691 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
693 static const unsigned char swizzle
[4] = {0, 1, 2, 3};
694 struct si_texture
*tex
= (struct si_texture
*)res
;
695 unsigned level
= view
->u
.tex
.level
;
696 unsigned width
, height
, depth
, hw_level
;
697 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
698 unsigned access
= view
->access
;
700 assert(!tex
->is_depth
);
701 assert(fmask_desc
|| tex
->surface
.fmask_offset
== 0);
703 if (uses_dcc
&& !skip_decompress
&&
704 !(access
& SI_IMAGE_ACCESS_DCC_OFF
) &&
705 (access
& PIPE_IMAGE_ACCESS_WRITE
||
706 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
707 /* If DCC can't be disabled, at least decompress it.
708 * The decompression is relatively cheap if the surface
709 * has been decompressed already.
711 if (!si_texture_disable_dcc(ctx
, tex
))
712 si_decompress_dcc(ctx
, tex
);
715 if (ctx
->chip_class
>= GFX9
) {
716 /* Always set the base address. The swizzle modes don't
717 * allow setting mipmap level offsets as the base.
719 width
= res
->b
.b
.width0
;
720 height
= res
->b
.b
.height0
;
721 depth
= res
->b
.b
.depth0
;
724 /* Always force the base level to the selected level.
726 * This is required for 3D textures, where otherwise
727 * selecting a single slice for non-layered bindings
728 * fails. It doesn't hurt the other targets.
730 width
= u_minify(res
->b
.b
.width0
, level
);
731 height
= u_minify(res
->b
.b
.height0
, level
);
732 depth
= u_minify(res
->b
.b
.depth0
, level
);
736 screen
->make_texture_descriptor(
737 screen
, tex
, false, res
->b
.b
.target
, view
->format
, swizzle
, hw_level
, hw_level
,
738 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
, width
, height
, depth
, desc
, fmask_desc
);
739 si_set_mutable_tex_desc_fields(screen
, tex
, &tex
->surface
.u
.legacy
.level
[level
], level
, level
,
740 util_format_get_blockwidth(view
->format
), false,
741 view
->access
& SI_IMAGE_ACCESS_DCC_OFF
, desc
);
745 static void si_set_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
,
746 const struct pipe_image_view
*view
, bool skip_decompress
)
748 struct si_images
*images
= &ctx
->images
[shader
];
749 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
750 struct si_resource
*res
;
752 if (!view
|| !view
->resource
) {
753 si_disable_shader_image(ctx
, shader
, slot
);
757 res
= si_resource(view
->resource
);
759 si_set_shader_image_desc(ctx
, view
, skip_decompress
, descs
->list
+ si_get_image_slot(slot
) * 8,
760 descs
->list
+ si_get_image_slot(slot
+ SI_NUM_IMAGES
) * 8);
762 if (&images
->views
[slot
] != view
)
763 util_copy_image_view(&images
->views
[slot
], view
);
765 if (res
->b
.b
.target
== PIPE_BUFFER
|| view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
766 images
->needs_color_decompress_mask
&= ~(1 << slot
);
767 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
769 struct si_texture
*tex
= (struct si_texture
*)res
;
770 unsigned level
= view
->u
.tex
.level
;
772 if (color_needs_decompression(tex
)) {
773 images
->needs_color_decompress_mask
|= 1 << slot
;
775 images
->needs_color_decompress_mask
&= ~(1 << slot
);
778 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
779 ctx
->need_check_render_feedback
= true;
782 images
->enabled_mask
|= 1u << slot
;
783 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
785 /* Since this can flush, it must be done after enabled_mask is updated. */
786 si_sampler_view_add_buffer(
788 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
792 static void si_set_shader_images(struct pipe_context
*pipe
, enum pipe_shader_type shader
,
793 unsigned start_slot
, unsigned count
,
794 const struct pipe_image_view
*views
)
796 struct si_context
*ctx
= (struct si_context
*)pipe
;
799 assert(shader
< SI_NUM_SHADERS
);
804 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
807 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
808 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
810 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
811 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
814 si_update_shader_needs_decompress_mask(ctx
, shader
);
817 static void si_images_update_needs_color_decompress_mask(struct si_images
*images
)
819 unsigned mask
= images
->enabled_mask
;
822 int i
= u_bit_scan(&mask
);
823 struct pipe_resource
*res
= images
->views
[i
].resource
;
825 if (res
&& res
->target
!= PIPE_BUFFER
) {
826 struct si_texture
*tex
= (struct si_texture
*)res
;
828 if (color_needs_decompression(tex
)) {
829 images
->needs_color_decompress_mask
|= 1 << i
;
831 images
->needs_color_decompress_mask
&= ~(1 << i
);
837 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
839 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
840 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
841 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
842 struct pipe_surface
*surf
= NULL
;
844 /* si_texture_disable_dcc can get us here again. */
845 if (sctx
->blitter
->running
)
848 /* See whether FBFETCH is used and color buffer 0 is set. */
849 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
850 sctx
->framebuffer
.state
.nr_cbufs
&& sctx
->framebuffer
.state
.cbufs
[0])
851 surf
= sctx
->framebuffer
.state
.cbufs
[0];
853 /* Return if FBFETCH transitions from disabled to disabled. */
854 if (!buffers
->buffers
[slot
] && !surf
)
857 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
858 si_update_ps_iter_samples(sctx
);
861 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
862 struct pipe_image_view view
= {0};
865 assert(!tex
->is_depth
);
867 /* Disable DCC, because the texture is used as both a sampler
870 si_texture_disable_dcc(sctx
, tex
);
872 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
874 assert(tex
->cmask_buffer
!= &tex
->buffer
);
875 si_eliminate_fast_color_clear(sctx
, tex
, NULL
);
876 si_texture_discard_cmask(sctx
->screen
, tex
);
879 view
.resource
= surf
->texture
;
880 view
.format
= surf
->format
;
881 view
.access
= PIPE_IMAGE_ACCESS_READ
;
882 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
883 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
884 view
.u
.tex
.level
= surf
->u
.tex
.level
;
886 /* Set the descriptor. */
887 uint32_t *desc
= descs
->list
+ slot
* 4;
888 memset(desc
, 0, 16 * 4);
889 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
891 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
892 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READ
,
893 RADEON_PRIO_SHADER_RW_IMAGE
);
894 buffers
->enabled_mask
|= 1u << slot
;
896 /* Clear the descriptor. */
897 memset(descs
->list
+ slot
* 4, 0, 8 * 4);
898 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
899 buffers
->enabled_mask
&= ~(1u << slot
);
902 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
907 static void si_bind_sampler_states(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
908 unsigned start
, unsigned count
, void **states
)
910 struct si_context
*sctx
= (struct si_context
*)ctx
;
911 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
912 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
913 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
916 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
919 for (i
= 0; i
< count
; i
++) {
920 unsigned slot
= start
+ i
;
921 unsigned desc_slot
= si_get_sampler_slot(slot
);
923 if (!sstates
[i
] || sstates
[i
] == samplers
->sampler_states
[slot
])
927 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
929 samplers
->sampler_states
[slot
] = sstates
[i
];
931 /* If FMASK is bound, don't overwrite it.
932 * The sampler state will be set after FMASK is unbound.
934 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[slot
];
936 struct si_texture
*tex
= NULL
;
938 if (sview
&& sview
->base
.texture
&& sview
->base
.texture
->target
!= PIPE_BUFFER
)
939 tex
= (struct si_texture
*)sview
->base
.texture
;
941 if (tex
&& tex
->surface
.fmask_size
)
944 si_set_sampler_state_desc(sstates
[i
], sview
, tex
, desc
->list
+ desc_slot
* 16 + 12);
946 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
950 /* BUFFER RESOURCES */
952 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
953 struct si_descriptors
*descs
, unsigned num_buffers
,
954 short shader_userdata_rel_index
,
955 enum radeon_bo_priority priority
,
956 enum radeon_bo_priority priority_constbuf
)
958 buffers
->priority
= priority
;
959 buffers
->priority_constbuf
= priority_constbuf
;
960 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
961 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
963 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
966 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
967 struct si_descriptors
*descs
)
971 for (i
= 0; i
< descs
->num_elements
; i
++) {
972 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
975 FREE(buffers
->buffers
);
976 FREE(buffers
->offsets
);
979 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
980 struct si_buffer_resources
*buffers
)
982 unsigned mask
= buffers
->enabled_mask
;
984 /* Add buffers to the CS. */
986 int i
= u_bit_scan(&mask
);
988 radeon_add_to_buffer_list(
989 sctx
, sctx
->gfx_cs
, si_resource(buffers
->buffers
[i
]),
990 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
991 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
: buffers
->priority_constbuf
);
995 static bool si_buffer_resources_check_encrypted(struct si_context
*sctx
,
996 struct si_buffer_resources
*buffers
)
998 unsigned mask
= buffers
->enabled_mask
;
1001 int i
= u_bit_scan(&mask
);
1003 /* only check for reads */
1004 if ((buffers
->writable_mask
& (1u << i
)) == 0 &&
1005 (si_resource(buffers
->buffers
[i
])->flags
& RADEON_FLAG_ENCRYPTED
))
1012 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1013 struct si_descriptors
*descs
, unsigned idx
,
1014 struct pipe_resource
**buf
, unsigned *offset
,
1017 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1019 struct si_resource
*res
= si_resource(*buf
);
1020 const uint32_t *desc
= descs
->list
+ idx
* 4;
1025 assert(G_008F04_STRIDE(desc
[1]) == 0);
1026 va
= si_desc_extract_buffer_address(desc
);
1028 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1029 *offset
= va
- res
->gpu_address
;
1033 /* VERTEX BUFFERS */
1035 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1037 int count
= sctx
->num_vertex_elements
;
1040 for (i
= 0; i
< count
; i
++) {
1041 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1043 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1045 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1048 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1049 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1050 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1053 if (!sctx
->vb_descriptors_buffer
)
1055 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1056 RADEON_PRIO_DESCRIPTORS
);
1059 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1061 unsigned i
, count
= sctx
->num_vertex_elements
;
1064 if (!sctx
->vertex_buffers_dirty
|| !count
)
1067 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1068 unsigned alloc_size
= velems
->vb_desc_list_alloc_size
;
1071 /* Vertex buffer descriptors are the only ones which are uploaded
1072 * directly through a staging buffer and don't go through
1073 * the fine-grained upload path.
1075 u_upload_alloc(sctx
->b
.const_uploader
, 0, alloc_size
,
1076 si_optimal_tcc_alignment(sctx
, alloc_size
), &sctx
->vb_descriptors_offset
,
1077 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
, (void **)&ptr
);
1078 if (!sctx
->vb_descriptors_buffer
) {
1079 sctx
->vb_descriptors_offset
= 0;
1080 sctx
->vb_descriptors_gpu_list
= NULL
;
1084 sctx
->vb_descriptors_gpu_list
= ptr
;
1085 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1086 RADEON_PRIO_DESCRIPTORS
);
1087 sctx
->vertex_buffer_pointer_dirty
= true;
1088 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1090 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
1091 sctx
->vertex_buffer_pointer_dirty
= false;
1092 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VBO_DESCRIPTORS
;
1095 assert(count
<= SI_MAX_ATTRIBS
);
1097 unsigned first_vb_use_mask
= velems
->first_vb_use_mask
;
1098 unsigned num_vbos_in_user_sgprs
= sctx
->screen
->num_vbos_in_user_sgprs
;
1100 for (i
= 0; i
< count
; i
++) {
1101 struct pipe_vertex_buffer
*vb
;
1102 struct si_resource
*buf
;
1103 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1104 uint32_t *desc
= i
< num_vbos_in_user_sgprs
? &sctx
->vb_descriptor_user_sgprs
[i
* 4]
1105 : &ptr
[(i
- num_vbos_in_user_sgprs
) * 4];
1107 vb
= &sctx
->vertex_buffer
[vbo_index
];
1108 buf
= si_resource(vb
->buffer
.resource
);
1110 memset(desc
, 0, 16);
1114 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) + velems
->src_offset
[i
];
1116 if (offset
>= buf
->b
.b
.width0
) {
1117 assert(offset
< buf
->b
.b
.width0
);
1118 memset(desc
, 0, 16);
1122 uint64_t va
= buf
->gpu_address
+ offset
;
1124 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1125 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1126 /* Round up by rounding down and adding 1 */
1127 num_records
= (num_records
- velems
->format_size
[i
]) / vb
->stride
+ 1;
1129 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1131 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1133 /* OOB_SELECT chooses the out-of-bounds check:
1134 * - 1: index >= NUM_RECORDS (Structured)
1135 * - 3: offset >= NUM_RECORDS (Raw)
1137 if (sctx
->chip_class
>= GFX10
)
1138 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? V_008F0C_OOB_SELECT_STRUCTURED
1139 : V_008F0C_OOB_SELECT_RAW
);
1142 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(vb
->stride
);
1143 desc
[2] = num_records
;
1144 desc
[3] = rsrc_word3
;
1146 if (first_vb_use_mask
& (1 << i
)) {
1147 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(vb
->buffer
.resource
),
1148 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1152 /* Don't flush the const cache. It would have a very negative effect
1153 * on performance (confirmed by testing). New descriptors are always
1154 * uploaded to a fresh new buffer, so I don't think flushing the const
1155 * cache is needed. */
1156 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1157 sctx
->vertex_buffer_user_sgprs_dirty
= num_vbos_in_user_sgprs
> 0;
1158 sctx
->vertex_buffers_dirty
= false;
1162 /* CONSTANT BUFFERS */
1164 static struct si_descriptors
*si_const_and_shader_buffer_descriptors(struct si_context
*sctx
,
1167 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1170 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
, const uint8_t *ptr
,
1171 unsigned size
, uint32_t *const_offset
)
1175 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
, si_optimal_tcc_alignment(sctx
, size
),
1176 const_offset
, (struct pipe_resource
**)buf
, &tmp
);
1178 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1181 static void si_set_constant_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1182 unsigned descriptors_idx
, uint slot
,
1183 const struct pipe_constant_buffer
*input
)
1185 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1186 assert(slot
< descs
->num_elements
);
1187 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1189 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1190 * with a NULL buffer). We need to use a dummy buffer instead. */
1191 if (sctx
->chip_class
== GFX7
&& (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1192 input
= &sctx
->null_const_buf
;
1194 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1195 struct pipe_resource
*buffer
= NULL
;
1197 unsigned buffer_offset
;
1199 /* Upload the user buffer if needed. */
1200 if (input
->user_buffer
) {
1201 si_upload_const_buffer(sctx
, (struct si_resource
**)&buffer
, input
->user_buffer
,
1202 input
->buffer_size
, &buffer_offset
);
1204 /* Just unbind on failure. */
1205 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1209 pipe_resource_reference(&buffer
, input
->buffer
);
1210 buffer_offset
= input
->buffer_offset
;
1213 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1215 /* Set the descriptor. */
1216 uint32_t *desc
= descs
->list
+ slot
* 4;
1218 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1219 desc
[2] = input
->buffer_size
;
1220 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1223 if (sctx
->chip_class
>= GFX10
) {
1224 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1225 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1227 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1228 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1231 buffers
->buffers
[slot
] = buffer
;
1232 buffers
->offsets
[slot
] = buffer_offset
;
1233 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1234 buffers
->priority_constbuf
, true);
1235 buffers
->enabled_mask
|= 1u << slot
;
1237 /* Clear the descriptor. */
1238 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1239 buffers
->enabled_mask
&= ~(1u << slot
);
1242 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1245 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1246 uint slot
, const struct pipe_constant_buffer
*input
)
1248 struct si_context
*sctx
= (struct si_context
*)ctx
;
1250 if (shader
>= SI_NUM_SHADERS
)
1253 if (slot
== 0 && input
&& input
->buffer
&&
1254 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1255 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1259 if (input
&& input
->buffer
)
1260 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1262 slot
= si_get_constbuf_slot(slot
);
1263 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1264 si_const_and_shader_buffer_descriptors_idx(shader
), slot
, input
);
1267 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
, uint slot
,
1268 struct pipe_constant_buffer
*cbuf
)
1270 cbuf
->user_buffer
= NULL
;
1271 si_get_buffer_from_descriptors(
1272 &sctx
->const_and_shader_buffers
[shader
], si_const_and_shader_buffer_descriptors(sctx
, shader
),
1273 si_get_constbuf_slot(slot
), &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1276 /* SHADER BUFFERS */
1278 static void si_set_shader_buffer(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1279 unsigned descriptors_idx
, uint slot
,
1280 const struct pipe_shader_buffer
*sbuffer
, bool writable
,
1281 enum radeon_bo_priority priority
)
1283 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1284 uint32_t *desc
= descs
->list
+ slot
* 4;
1286 if (!sbuffer
|| !sbuffer
->buffer
) {
1287 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1288 memset(desc
, 0, sizeof(uint32_t) * 4);
1289 buffers
->enabled_mask
&= ~(1u << slot
);
1290 buffers
->writable_mask
&= ~(1u << slot
);
1291 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1295 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1296 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1299 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(0);
1300 desc
[2] = sbuffer
->buffer_size
;
1301 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1302 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1304 if (sctx
->chip_class
>= GFX10
) {
1305 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1306 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) | S_008F0C_RESOURCE_LEVEL(1);
1308 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1312 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1313 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1314 radeon_add_to_gfx_buffer_list_check_mem(
1315 sctx
, buf
, writable
? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, priority
, true);
1317 buffers
->writable_mask
|= 1u << slot
;
1319 buffers
->writable_mask
&= ~(1u << slot
);
1321 buffers
->enabled_mask
|= 1u << slot
;
1322 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1324 util_range_add(&buf
->b
.b
, &buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1325 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1328 static void si_set_shader_buffers(struct pipe_context
*ctx
, enum pipe_shader_type shader
,
1329 unsigned start_slot
, unsigned count
,
1330 const struct pipe_shader_buffer
*sbuffers
,
1331 unsigned writable_bitmask
)
1333 struct si_context
*sctx
= (struct si_context
*)ctx
;
1334 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1335 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1338 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1340 for (i
= 0; i
< count
; ++i
) {
1341 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1342 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1344 if (sbuffer
&& sbuffer
->buffer
)
1345 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1347 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1348 !!(writable_bitmask
& (1u << i
)), buffers
->priority
);
1352 void si_get_shader_buffers(struct si_context
*sctx
, enum pipe_shader_type shader
, uint start_slot
,
1353 uint count
, struct pipe_shader_buffer
*sbuf
)
1355 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1356 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1358 for (unsigned i
= 0; i
< count
; ++i
) {
1359 si_get_buffer_from_descriptors(buffers
, descs
, si_get_shaderbuf_slot(start_slot
+ i
),
1360 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
, &sbuf
[i
].buffer_size
);
1366 void si_set_rw_buffer(struct si_context
*sctx
, uint slot
, const struct pipe_constant_buffer
*input
)
1368 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, input
);
1371 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1372 const struct pipe_shader_buffer
*sbuffer
)
1374 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
, slot
, sbuffer
, true,
1375 RADEON_PRIO_SHADER_RW_BUFFER
);
1378 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
, struct pipe_resource
*buffer
,
1379 unsigned stride
, unsigned num_records
, bool add_tid
, bool swizzle
,
1380 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1382 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1383 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1385 /* The stride field in the resource descriptor has 14 bits */
1386 assert(stride
< (1 << 14));
1388 assert(slot
< descs
->num_elements
);
1389 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1394 va
= si_resource(buffer
)->gpu_address
+ offset
;
1396 switch (element_size
) {
1398 assert(!"Unsupported ring buffer element size");
1414 switch (index_stride
) {
1416 assert(!"Unsupported ring buffer index stride");
1432 if (sctx
->chip_class
>= GFX8
&& stride
)
1433 num_records
*= stride
;
1435 /* Set the descriptor. */
1436 uint32_t *desc
= descs
->list
+ slot
* 4;
1438 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
) |
1439 S_008F04_SWIZZLE_ENABLE(swizzle
);
1440 desc
[2] = num_records
;
1441 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1442 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1443 S_008F0C_INDEX_STRIDE(index_stride
) | S_008F0C_ADD_TID_ENABLE(add_tid
);
1445 if (sctx
->chip_class
>= GFX9
)
1446 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1448 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1450 if (sctx
->chip_class
>= GFX10
) {
1451 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1452 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) | S_008F0C_RESOURCE_LEVEL(1);
1454 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1455 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1458 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1459 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(buffer
), RADEON_USAGE_READWRITE
,
1461 buffers
->enabled_mask
|= 1u << slot
;
1463 /* Clear the descriptor. */
1464 memset(descs
->list
+ slot
* 4, 0, sizeof(uint32_t) * 4);
1465 buffers
->enabled_mask
&= ~(1u << slot
);
1468 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1471 /* INTERNAL CONST BUFFERS */
1473 static void si_set_polygon_stipple(struct pipe_context
*ctx
, const struct pipe_poly_stipple
*state
)
1475 struct si_context
*sctx
= (struct si_context
*)ctx
;
1476 struct pipe_constant_buffer cb
= {};
1477 unsigned stipple
[32];
1480 for (i
= 0; i
< 32; i
++)
1481 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1483 cb
.user_buffer
= stipple
;
1484 cb
.buffer_size
= sizeof(stipple
);
1486 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1489 /* TEXTURE METADATA ENABLE/DISABLE */
1491 static void si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1493 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1494 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1496 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1497 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1498 struct si_texture
*tex
;
1500 if (!res
|| res
->target
== PIPE_BUFFER
)
1503 tex
= (struct si_texture
*)res
;
1504 if (!color_needs_decompression(tex
))
1507 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
, struct si_texture_handle
*,
1511 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1512 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1513 struct pipe_resource
*res
= view
->resource
;
1514 struct si_texture
*tex
;
1516 if (!res
|| res
->target
== PIPE_BUFFER
)
1519 tex
= (struct si_texture
*)res
;
1520 if (!color_needs_decompression(tex
))
1523 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
, struct si_image_handle
*,
1528 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1529 * while the texture is bound, possibly by a different context. In that case,
1530 * call this function to update needs_*_decompress_masks.
1532 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1534 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1535 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1536 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1537 si_update_shader_needs_decompress_mask(sctx
, i
);
1540 si_resident_handles_update_needs_color_decompress(sctx
);
1543 /* BUFFER DISCARD/INVALIDATION */
1545 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1546 * If buf == NULL, reset all descriptors.
1548 static void si_reset_buffer_resources(struct si_context
*sctx
, struct si_buffer_resources
*buffers
,
1549 unsigned descriptors_idx
, unsigned slot_mask
,
1550 struct pipe_resource
*buf
, enum radeon_bo_priority priority
)
1552 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1553 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1556 unsigned i
= u_bit_scan(&mask
);
1557 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1559 if (buffer
&& (!buf
|| buffer
== buf
)) {
1560 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1561 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1563 radeon_add_to_gfx_buffer_list_check_mem(
1564 sctx
, si_resource(buffer
),
1565 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
1571 /* Update all buffer bindings where the buffer is bound, including
1572 * all resource descriptors. This is invalidate_buffer without
1575 * If buf == NULL, update all buffer bindings.
1577 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1579 struct si_resource
*buffer
= si_resource(buf
);
1581 unsigned num_elems
= sctx
->num_vertex_elements
;
1583 /* We changed the buffer, now we need to bind it where the old one
1584 * was bound. This consists of 2 things:
1585 * 1) Updating the resource descriptor and dirtying it.
1586 * 2) Adding a relocation to the CS, so that it's usable.
1589 /* Vertex buffers. */
1592 sctx
->vertex_buffers_dirty
= true;
1593 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1594 for (i
= 0; i
< num_elems
; i
++) {
1595 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1597 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1599 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1602 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1603 sctx
->vertex_buffers_dirty
= true;
1609 /* Streamout buffers. (other internal buffers can't be invalidated) */
1610 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1611 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1612 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1613 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1614 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1616 if (!buffer
|| (buf
&& buffer
!= buf
))
1619 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
], descs
->list
+ i
* 4);
1620 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1622 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_WRITE
,
1623 RADEON_PRIO_SHADER_RW_BUFFER
, true);
1625 /* Update the streamout state. */
1626 if (sctx
->streamout
.begin_emitted
)
1627 si_emit_streamout_end(sctx
);
1628 sctx
->streamout
.append_bitmask
= sctx
->streamout
.enabled_mask
;
1629 si_streamout_buffers_dirty(sctx
);
1633 /* Constant and shader buffers. */
1634 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1635 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1636 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1637 si_const_and_shader_buffer_descriptors_idx(shader
),
1638 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1639 buf
, sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1642 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1643 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1644 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1645 si_const_and_shader_buffer_descriptors_idx(shader
),
1646 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
), buf
,
1647 sctx
->const_and_shader_buffers
[shader
].priority
);
1650 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1651 /* Texture buffers - update bindings. */
1652 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1653 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1654 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1655 unsigned mask
= samplers
->enabled_mask
;
1658 unsigned i
= u_bit_scan(&mask
);
1659 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1661 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1662 unsigned desc_slot
= si_get_sampler_slot(i
);
1664 si_set_buf_desc_address(si_resource(buffer
), samplers
->views
[i
]->u
.buf
.offset
,
1665 descs
->list
+ desc_slot
* 16 + 4);
1666 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1668 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1669 RADEON_PRIO_SAMPLER_BUFFER
, true);
1676 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1677 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1678 struct si_images
*images
= &sctx
->images
[shader
];
1679 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
1680 unsigned mask
= images
->enabled_mask
;
1683 unsigned i
= u_bit_scan(&mask
);
1684 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1686 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1687 unsigned desc_slot
= si_get_image_slot(i
);
1689 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1690 si_mark_image_range_valid(&images
->views
[i
]);
1692 si_set_buf_desc_address(si_resource(buffer
), images
->views
[i
].u
.buf
.offset
,
1693 descs
->list
+ desc_slot
* 8 + 4);
1694 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1696 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
),
1697 RADEON_USAGE_READWRITE
,
1698 RADEON_PRIO_SAMPLER_BUFFER
, true);
1704 /* Bindless texture handles */
1705 if (!buffer
|| buffer
->texture_handle_allocated
) {
1706 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1708 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1709 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1710 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1711 struct pipe_resource
*buffer
= view
->texture
;
1713 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1714 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1715 descs
->list
+ desc_slot
* 16 + 4);
1717 (*tex_handle
)->desc_dirty
= true;
1718 sctx
->bindless_descriptors_dirty
= true;
1720 radeon_add_to_gfx_buffer_list_check_mem(sctx
, si_resource(buffer
), RADEON_USAGE_READ
,
1721 RADEON_PRIO_SAMPLER_BUFFER
, true);
1726 /* Bindless image handles */
1727 if (!buffer
|| buffer
->image_handle_allocated
) {
1728 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1730 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1731 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1732 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1733 struct pipe_resource
*buffer
= view
->resource
;
1735 if (buffer
&& buffer
->target
== PIPE_BUFFER
&& (!buf
|| buffer
== buf
)) {
1736 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1737 si_mark_image_range_valid(view
);
1739 si_set_buf_desc_address(si_resource(buffer
), view
->u
.buf
.offset
,
1740 descs
->list
+ desc_slot
* 16 + 4);
1742 (*img_handle
)->desc_dirty
= true;
1743 sctx
->bindless_descriptors_dirty
= true;
1745 radeon_add_to_gfx_buffer_list_check_mem(
1746 sctx
, si_resource(buffer
), RADEON_USAGE_READWRITE
, RADEON_PRIO_SAMPLER_BUFFER
, true);
1752 /* Do the same for other contexts. They will invoke this function
1753 * with buffer == NULL.
1755 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1757 /* Skip the update for the current context, because we have already updated
1758 * the buffer bindings.
1760 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1761 sctx
->last_dirty_buf_counter
= new_counter
;
1765 static void si_upload_bindless_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
1766 unsigned num_dwords
)
1768 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1769 unsigned desc_slot_offset
= desc_slot
* 16;
1773 data
= desc
->list
+ desc_slot_offset
;
1774 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1776 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
, num_dwords
* 4, V_370_TC_L2
,
1780 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1782 if (!sctx
->bindless_descriptors_dirty
)
1785 /* Wait for graphics/compute to be idle before updating the resident
1786 * descriptors directly in memory, in case the GPU is using them.
1788 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
1789 sctx
->emit_cache_flush(sctx
);
1791 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1792 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1794 if (!(*tex_handle
)->desc_dirty
)
1797 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1798 (*tex_handle
)->desc_dirty
= false;
1801 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1802 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1804 if (!(*img_handle
)->desc_dirty
)
1807 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1808 (*img_handle
)->desc_dirty
= false;
1811 /* Invalidate L1 because it doesn't know that L2 changed. */
1812 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1813 sctx
->emit_cache_flush(sctx
);
1815 sctx
->bindless_descriptors_dirty
= false;
1818 /* Update mutable image descriptor fields of all resident textures. */
1819 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1820 struct si_texture_handle
*tex_handle
)
1822 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1823 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1824 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1825 uint32_t desc_list
[16];
1827 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1830 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1831 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
, desc
->list
+ desc_slot_offset
);
1833 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
))) {
1834 tex_handle
->desc_dirty
= true;
1835 sctx
->bindless_descriptors_dirty
= true;
1839 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1840 struct si_image_handle
*img_handle
)
1842 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1843 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1844 struct pipe_image_view
*view
= &img_handle
->view
;
1845 struct pipe_resource
*res
= view
->resource
;
1846 uint32_t image_desc
[16];
1847 unsigned desc_size
= (res
->nr_samples
>= 2 ? 16 : 8) * 4;
1849 if (res
->target
== PIPE_BUFFER
)
1852 memcpy(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
);
1853 si_set_shader_image_desc(sctx
, view
, true, desc
->list
+ desc_slot_offset
,
1854 desc
->list
+ desc_slot_offset
+ 8);
1856 if (memcmp(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
)) {
1857 img_handle
->desc_dirty
= true;
1858 sctx
->bindless_descriptors_dirty
= true;
1862 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1864 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
1865 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1868 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
1869 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1872 si_upload_bindless_descriptors(sctx
);
1875 /* Update mutable image descriptor fields of all bound textures. */
1876 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1880 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1881 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1882 struct si_images
*images
= &sctx
->images
[shader
];
1886 mask
= images
->enabled_mask
;
1888 unsigned i
= u_bit_scan(&mask
);
1889 struct pipe_image_view
*view
= &images
->views
[i
];
1891 if (!view
->resource
|| view
->resource
->target
== PIPE_BUFFER
)
1894 si_set_shader_image(sctx
, shader
, i
, view
, true);
1897 /* Sampler views. */
1898 mask
= samplers
->enabled_mask
;
1900 unsigned i
= u_bit_scan(&mask
);
1901 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1903 if (!view
|| !view
->texture
|| view
->texture
->target
== PIPE_BUFFER
)
1906 si_set_sampler_view(sctx
, shader
, i
, samplers
->views
[i
], true);
1909 si_update_shader_needs_decompress_mask(sctx
, shader
);
1912 si_update_all_resident_texture_descriptors(sctx
);
1913 si_update_ps_colorbuf0_slot(sctx
);
1916 /* SHADER USER DATA */
1918 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
, unsigned shader
)
1920 sctx
->shader_pointers_dirty
|=
1921 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
, SI_NUM_SHADER_DESCS
);
1923 if (shader
== PIPE_SHADER_VERTEX
) {
1924 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1925 sctx
->vertex_buffer_user_sgprs_dirty
=
1926 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1929 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1932 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1934 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1935 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1936 sctx
->vertex_buffer_user_sgprs_dirty
=
1937 sctx
->num_vertex_elements
> 0 && sctx
->screen
->num_vbos_in_user_sgprs
;
1938 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1939 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1940 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1943 /* Set a base register address for user data constants in the given shader.
1944 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1946 static void si_set_user_data_base(struct si_context
*sctx
, unsigned shader
, uint32_t new_base
)
1948 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1950 if (*base
!= new_base
) {
1954 si_mark_shader_pointers_dirty(sctx
, shader
);
1956 /* Any change in enabled shader stages requires re-emitting
1957 * the VS state SGPR, because it contains the clamp_vertex_color
1958 * state, which can be done in VS, TES, and GS.
1960 sctx
->last_vs_state
= ~0;
1964 /* This must be called when these are changed between enabled and disabled
1966 * - tessellation evaluation shader
1969 void si_shader_change_notify(struct si_context
*sctx
)
1971 /* VS can be bound as VS, ES, or LS. */
1972 if (sctx
->tes_shader
.cso
) {
1973 if (sctx
->chip_class
>= GFX10
) {
1974 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1975 } else if (sctx
->chip_class
== GFX9
) {
1976 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1978 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1980 } else if (sctx
->chip_class
>= GFX10
) {
1981 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1982 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1984 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1986 } else if (sctx
->gs_shader
.cso
) {
1987 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1989 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1992 /* TES can be bound as ES, VS, or not bound. */
1993 if (sctx
->tes_shader
.cso
) {
1994 if (sctx
->chip_class
>= GFX10
) {
1995 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
1996 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1998 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2000 } else if (sctx
->gs_shader
.cso
) {
2001 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2003 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2006 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2010 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
, unsigned sh_offset
,
2011 unsigned pointer_count
)
2013 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2014 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2017 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
, struct radeon_cmdbuf
*cs
,
2020 radeon_emit(cs
, va
);
2022 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2025 static void si_emit_shader_pointer(struct si_context
*sctx
, struct si_descriptors
*desc
,
2028 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2029 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2031 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2032 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2035 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
, unsigned pointer_mask
,
2041 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2042 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2046 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2048 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2049 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2051 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2052 for (int i
= 0; i
< count
; i
++)
2053 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
[i
].gpu_address
);
2057 static void si_emit_global_shader_pointers(struct si_context
*sctx
, struct si_descriptors
*descs
)
2059 if (sctx
->chip_class
>= GFX10
) {
2060 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2061 /* HW VS stage only used in non-NGG mode. */
2062 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2063 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2064 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2066 } else if (sctx
->chip_class
== GFX9
) {
2067 /* Broadcast it to all shader stages. */
2068 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2072 si_emit_shader_pointer(sctx
, descs
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2073 si_emit_shader_pointer(sctx
, descs
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2074 si_emit_shader_pointer(sctx
, descs
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2075 si_emit_shader_pointer(sctx
, descs
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2076 si_emit_shader_pointer(sctx
, descs
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2077 si_emit_shader_pointer(sctx
, descs
, R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2080 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2082 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2084 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2085 si_emit_global_shader_pointers(sctx
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2088 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2089 sh_base
[PIPE_SHADER_VERTEX
]);
2090 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2091 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2092 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2093 sh_base
[PIPE_SHADER_FRAGMENT
]);
2094 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2095 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2096 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2097 sh_base
[PIPE_SHADER_GEOMETRY
]);
2099 sctx
->shader_pointers_dirty
&= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2101 if (sctx
->vertex_buffer_pointer_dirty
&& sctx
->num_vertex_elements
) {
2102 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2104 /* Find the location of the VB descriptor pointer. */
2105 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2106 if (sctx
->chip_class
>= GFX9
) {
2107 if (sctx
->tes_shader
.cso
)
2108 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2109 else if (sctx
->gs_shader
.cso
)
2110 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2113 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2114 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2115 si_emit_shader_pointer_body(
2116 sctx
->screen
, cs
, sctx
->vb_descriptors_buffer
->gpu_address
+ sctx
->vb_descriptors_offset
);
2117 sctx
->vertex_buffer_pointer_dirty
= false;
2120 if (sctx
->vertex_buffer_user_sgprs_dirty
&& sctx
->num_vertex_elements
&&
2121 sctx
->screen
->num_vbos_in_user_sgprs
) {
2122 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2123 unsigned num_desc
= MIN2(sctx
->num_vertex_elements
, sctx
->screen
->num_vbos_in_user_sgprs
);
2124 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST
* 4;
2126 si_emit_shader_pointer_head(cs
, sh_offset
, num_desc
* 4);
2127 radeon_emit_array(cs
, sctx
->vb_descriptor_user_sgprs
, num_desc
* 4);
2128 sctx
->vertex_buffer_user_sgprs_dirty
= false;
2131 if (sctx
->graphics_bindless_pointer_dirty
) {
2132 si_emit_global_shader_pointers(sctx
, &sctx
->bindless_descriptors
);
2133 sctx
->graphics_bindless_pointer_dirty
= false;
2137 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2139 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2141 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2142 R_00B900_COMPUTE_USER_DATA_0
);
2143 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2145 if (sctx
->compute_bindless_pointer_dirty
) {
2146 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2147 sctx
->compute_bindless_pointer_dirty
= false;
2153 static void si_init_bindless_descriptors(struct si_context
*sctx
, struct si_descriptors
*desc
,
2154 short shader_userdata_rel_index
, unsigned num_elements
)
2156 ASSERTED
unsigned desc_slot
;
2158 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2159 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2161 /* The first bindless descriptor is stored at slot 1, because 0 is not
2162 * considered to be a valid handle.
2164 sctx
->num_bindless_descriptors
= 1;
2166 /* Track which bindless slots are used (or not). */
2167 util_idalloc_init(&sctx
->bindless_used_slots
);
2168 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2170 /* Reserve slot 0 because it's an invalid handle for bindless. */
2171 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2172 assert(desc_slot
== 0);
2175 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2177 si_release_descriptors(&sctx
->bindless_descriptors
);
2178 util_idalloc_fini(&sctx
->bindless_used_slots
);
2181 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2183 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2186 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2187 if (desc_slot
>= desc
->num_elements
) {
2188 /* The array of bindless descriptors is full, resize it. */
2189 unsigned slot_size
= desc
->element_dw_size
* 4;
2190 unsigned new_num_elements
= desc
->num_elements
* 2;
2193 REALLOC(desc
->list
, desc
->num_elements
* slot_size
, new_num_elements
* slot_size
);
2194 desc
->num_elements
= new_num_elements
;
2195 desc
->num_active_slots
= new_num_elements
;
2202 static unsigned si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2205 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2206 unsigned desc_slot
, desc_slot_offset
;
2208 /* Find a free slot. */
2209 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2211 /* For simplicity, sampler and image bindless descriptors use fixed
2212 * 16-dword slots for now. Image descriptors only need 8-dword but this
2213 * doesn't really matter because no real apps use image handles.
2215 desc_slot_offset
= desc_slot
* 16;
2217 /* Copy the descriptor into the array. */
2218 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2220 /* Re-upload the whole array of bindless descriptors into a new buffer.
2222 if (!si_upload_descriptors(sctx
, desc
))
2225 /* Make sure to re-emit the shader pointers for all stages. */
2226 sctx
->graphics_bindless_pointer_dirty
= true;
2227 sctx
->compute_bindless_pointer_dirty
= true;
2232 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
, unsigned desc_slot
,
2233 struct pipe_resource
*resource
, uint64_t offset
,
2236 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2237 struct si_resource
*buf
= si_resource(resource
);
2238 unsigned desc_slot_offset
= desc_slot
* 16;
2239 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2240 uint64_t old_desc_va
;
2242 assert(resource
->target
== PIPE_BUFFER
);
2244 /* Retrieve the old buffer addr from the descriptor. */
2245 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2247 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2248 /* The buffer has been invalidated when the handle wasn't
2249 * resident, update the descriptor and the dirty flag.
2251 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2257 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
, struct pipe_sampler_view
*view
,
2258 const struct pipe_sampler_state
*state
)
2260 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2261 struct si_context
*sctx
= (struct si_context
*)ctx
;
2262 struct si_texture_handle
*tex_handle
;
2263 struct si_sampler_state
*sstate
;
2264 uint32_t desc_list
[16];
2267 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2271 memset(desc_list
, 0, sizeof(desc_list
));
2272 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2274 sstate
= ctx
->create_sampler_state(ctx
, state
);
2280 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2281 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2282 ctx
->delete_sampler_state(ctx
, sstate
);
2284 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2285 if (!tex_handle
->desc_slot
) {
2290 handle
= tex_handle
->desc_slot
;
2292 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)(uintptr_t)handle
, tex_handle
)) {
2297 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2299 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2304 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2306 struct si_context
*sctx
= (struct si_context
*)ctx
;
2307 struct si_texture_handle
*tex_handle
;
2308 struct hash_entry
*entry
;
2310 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2314 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2316 /* Allow this descriptor slot to be re-used. */
2317 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2319 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2320 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2324 static void si_make_texture_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2327 struct si_context
*sctx
= (struct si_context
*)ctx
;
2328 struct si_texture_handle
*tex_handle
;
2329 struct si_sampler_view
*sview
;
2330 struct hash_entry
*entry
;
2332 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)(uintptr_t)handle
);
2336 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2337 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2340 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2341 struct si_texture
*tex
= (struct si_texture
*)sview
->base
.texture
;
2343 if (depth_needs_decompression(tex
)) {
2344 util_dynarray_append(&sctx
->resident_tex_needs_depth_decompress
,
2345 struct si_texture_handle
*, tex_handle
);
2348 if (color_needs_decompression(tex
)) {
2349 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
2350 struct si_texture_handle
*, tex_handle
);
2353 if (vi_dcc_enabled(tex
, sview
->base
.u
.tex
.first_level
) &&
2354 p_atomic_read(&tex
->framebuffers_bound
))
2355 sctx
->need_check_render_feedback
= true;
2357 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2359 si_update_bindless_buffer_descriptor(sctx
, tex_handle
->desc_slot
, sview
->base
.texture
,
2360 sview
->base
.u
.buf
.offset
, &tex_handle
->desc_dirty
);
2363 /* Re-upload the descriptor if it has been updated while it
2366 if (tex_handle
->desc_dirty
)
2367 sctx
->bindless_descriptors_dirty
= true;
2369 /* Add the texture handle to the per-context list. */
2370 util_dynarray_append(&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
);
2372 /* Add the buffers to the current CS in case si_begin_new_cs()
2373 * is not going to be called.
2375 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2376 sview
->is_stencil_sampler
, false);
2378 /* Remove the texture handle from the per-context list. */
2379 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
, struct si_texture_handle
*,
2382 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2383 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_depth_decompress
,
2384 struct si_texture_handle
*, tex_handle
);
2386 util_dynarray_delete_unordered(&sctx
->resident_tex_needs_color_decompress
,
2387 struct si_texture_handle
*, tex_handle
);
2392 static uint64_t si_create_image_handle(struct pipe_context
*ctx
, const struct pipe_image_view
*view
)
2394 struct si_context
*sctx
= (struct si_context
*)ctx
;
2395 struct si_image_handle
*img_handle
;
2396 uint32_t desc_list
[16];
2399 if (!view
|| !view
->resource
)
2402 img_handle
= CALLOC_STRUCT(si_image_handle
);
2406 memset(desc_list
, 0, sizeof(desc_list
));
2407 si_init_descriptor_list(&desc_list
[0], 8, 2, null_image_descriptor
);
2409 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], &desc_list
[8]);
2411 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
, sizeof(desc_list
));
2412 if (!img_handle
->desc_slot
) {
2417 handle
= img_handle
->desc_slot
;
2419 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)(uintptr_t)handle
, img_handle
)) {
2424 util_copy_image_view(&img_handle
->view
, view
);
2426 si_resource(view
->resource
)->image_handle_allocated
= true;
2431 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2433 struct si_context
*sctx
= (struct si_context
*)ctx
;
2434 struct si_image_handle
*img_handle
;
2435 struct hash_entry
*entry
;
2437 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2441 img_handle
= (struct si_image_handle
*)entry
->data
;
2443 util_copy_image_view(&img_handle
->view
, NULL
);
2444 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2448 static void si_make_image_handle_resident(struct pipe_context
*ctx
, uint64_t handle
,
2449 unsigned access
, bool resident
)
2451 struct si_context
*sctx
= (struct si_context
*)ctx
;
2452 struct si_image_handle
*img_handle
;
2453 struct pipe_image_view
*view
;
2454 struct si_resource
*res
;
2455 struct hash_entry
*entry
;
2457 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)(uintptr_t)handle
);
2461 img_handle
= (struct si_image_handle
*)entry
->data
;
2462 view
= &img_handle
->view
;
2463 res
= si_resource(view
->resource
);
2466 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2467 struct si_texture
*tex
= (struct si_texture
*)res
;
2468 unsigned level
= view
->u
.tex
.level
;
2470 if (color_needs_decompression(tex
)) {
2471 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
2472 struct si_image_handle
*, img_handle
);
2475 if (vi_dcc_enabled(tex
, level
) && p_atomic_read(&tex
->framebuffers_bound
))
2476 sctx
->need_check_render_feedback
= true;
2478 si_update_bindless_image_descriptor(sctx
, img_handle
);
2480 si_update_bindless_buffer_descriptor(sctx
, img_handle
->desc_slot
, view
->resource
,
2481 view
->u
.buf
.offset
, &img_handle
->desc_dirty
);
2484 /* Re-upload the descriptor if it has been updated while it
2487 if (img_handle
->desc_dirty
)
2488 sctx
->bindless_descriptors_dirty
= true;
2490 /* Add the image handle to the per-context list. */
2491 util_dynarray_append(&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
);
2493 /* Add the buffers to the current CS in case si_begin_new_cs()
2494 * is not going to be called.
2496 si_sampler_view_add_buffer(
2497 sctx
, view
->resource
,
2498 (access
& PIPE_IMAGE_ACCESS_WRITE
) ? RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
, false,
2501 /* Remove the image handle from the per-context list. */
2502 util_dynarray_delete_unordered(&sctx
->resident_img_handles
, struct si_image_handle
*,
2505 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2506 util_dynarray_delete_unordered(&sctx
->resident_img_needs_color_decompress
,
2507 struct si_image_handle
*, img_handle
);
2512 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2514 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2516 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/ sizeof(struct si_texture_handle
*);
2517 num_resident_img_handles
= sctx
->resident_img_handles
.size
/ sizeof(struct si_image_handle
*);
2519 /* Add all resident texture handles. */
2520 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
2521 struct si_sampler_view
*sview
= (struct si_sampler_view
*)(*tex_handle
)->view
;
2523 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
, RADEON_USAGE_READ
,
2524 sview
->is_stencil_sampler
, false);
2527 /* Add all resident image handles. */
2528 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
2529 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2531 si_sampler_view_add_buffer(sctx
, view
->resource
, RADEON_USAGE_READWRITE
, false, false);
2534 sctx
->num_resident_handles
+= num_resident_tex_handles
+ num_resident_img_handles
;
2535 assert(sctx
->bo_list_add_all_resident_resources
);
2536 sctx
->bo_list_add_all_resident_resources
= false;
2539 /* INIT/DEINIT/UPLOAD */
2541 void si_init_all_descriptors(struct si_context
*sctx
)
2544 unsigned first_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2546 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2548 sctx
->chip_class
>= GFX9
&& (i
== PIPE_SHADER_TESS_CTRL
|| i
== PIPE_SHADER_GEOMETRY
);
2549 unsigned num_sampler_slots
= SI_NUM_IMAGE_SLOTS
/ 2 + SI_NUM_SAMPLERS
;
2550 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2552 struct si_descriptors
*desc
;
2555 if (i
== PIPE_SHADER_TESS_CTRL
) {
2557 (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2558 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2560 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2563 (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2566 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2568 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2569 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
, num_buffer_slots
,
2570 rel_dw_offset
, RADEON_PRIO_SHADER_RW_BUFFER
,
2571 RADEON_PRIO_CONST_BUFFER
);
2572 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2575 if (i
== PIPE_SHADER_TESS_CTRL
) {
2577 (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
- R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2578 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2580 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2583 (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
- R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2586 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2589 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2590 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2593 for (j
= 0; j
< SI_NUM_IMAGE_SLOTS
; j
++)
2594 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2595 for (; j
< SI_NUM_IMAGE_SLOTS
+ SI_NUM_SAMPLERS
* 2; j
++)
2596 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2599 si_init_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2600 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2601 /* The second priority is used by
2602 * const buffers in RW buffer slots. */
2603 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2604 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2606 /* Initialize an array of 1024 bindless descriptors, when the limit is
2607 * reached, just make it larger and re-upload the whole array.
2609 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2610 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
, 1024);
2612 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2614 /* Set pipe_context functions. */
2615 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2616 sctx
->b
.set_shader_images
= si_set_shader_images
;
2617 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2618 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2619 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2620 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2621 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2622 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2623 sctx
->b
.create_image_handle
= si_create_image_handle
;
2624 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2625 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2627 if (!sctx
->has_graphics
)
2630 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2632 /* Shader user data. */
2633 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2635 /* Set default and immutable mappings. */
2637 assert(sctx
->chip_class
>= GFX10
);
2638 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2640 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2643 if (sctx
->chip_class
== GFX9
) {
2644 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2645 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2647 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2648 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2650 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2653 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2655 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2657 /* Assume nothing will go wrong: */
2658 sctx
->shader_pointers_dirty
|= dirty
;
2661 unsigned i
= u_bit_scan(&dirty
);
2663 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2667 sctx
->descriptors_dirty
&= ~mask
;
2669 si_upload_bindless_descriptors(sctx
);
2674 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2676 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2677 return si_upload_shader_descriptors(sctx
, mask
);
2680 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2682 /* Does not update rw_buffers as that is not needed for compute shaders
2683 * and the input buffer is using the same SGPR's anyway.
2685 const unsigned mask
=
2686 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2687 return si_upload_shader_descriptors(sctx
, mask
);
2690 void si_release_all_descriptors(struct si_context
*sctx
)
2694 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2695 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2696 si_const_and_shader_buffer_descriptors(sctx
, i
));
2697 si_release_sampler_views(&sctx
->samplers
[i
]);
2698 si_release_image_views(&sctx
->images
[i
]);
2700 si_release_buffer_resources(&sctx
->rw_buffers
, &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2701 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2702 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2704 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2705 si_release_descriptors(&sctx
->descriptors
[i
]);
2707 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2708 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2710 si_release_bindless_descriptors(sctx
);
2713 bool si_gfx_resources_check_encrypted(struct si_context
*sctx
)
2715 bool use_encrypted_bo
= false;
2716 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2717 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2718 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2719 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2720 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2721 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2724 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
&& !use_encrypted_bo
; i
++) {
2725 if (!current_shader
[i
]->cso
)
2729 si_buffer_resources_check_encrypted(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2731 si_sampler_views_check_encrypted(sctx
, &sctx
->samplers
[i
],
2732 current_shader
[i
]->cso
->info
.samplers_declared
);
2733 use_encrypted_bo
|= si_image_views_check_encrypted(sctx
, &sctx
->images
[i
],
2734 current_shader
[i
]->cso
->info
.images_declared
);
2736 use_encrypted_bo
|= si_buffer_resources_check_encrypted(sctx
, &sctx
->rw_buffers
);
2738 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
2739 for (int i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
&& !use_encrypted_bo
; i
++) {
2740 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2741 if (surf
&& surf
->texture
) {
2742 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2743 if (!(tex
->buffer
.flags
& RADEON_FLAG_ENCRYPTED
))
2745 /* Are we reading from this framebuffer (blend) */
2746 if ((blend
->blend_enable_4bit
>> (4 * i
)) & 0xf) {
2747 /* TODO: blend op */
2748 use_encrypted_bo
= true;
2753 /* TODO: we should assert that either use_encrypted_bo is false,
2754 * or all writable buffers are encrypted.
2756 return use_encrypted_bo
;
2759 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2761 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2762 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2763 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2764 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2766 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2767 si_vertex_buffers_begin_new_cs(sctx
);
2769 if (sctx
->bo_list_add_all_resident_resources
)
2770 si_resident_buffers_add_all_to_bo_list(sctx
);
2772 assert(sctx
->bo_list_add_all_gfx_resources
);
2773 sctx
->bo_list_add_all_gfx_resources
= false;
2776 bool si_compute_resources_check_encrypted(struct si_context
*sctx
)
2778 unsigned sh
= PIPE_SHADER_COMPUTE
;
2780 struct si_shader_info
* info
= &sctx
->cs_shader_state
.program
->sel
.info
;
2782 /* TODO: we should assert that either use_encrypted_bo is false,
2783 * or all writable buffers are encrypted.
2785 return si_buffer_resources_check_encrypted(sctx
, &sctx
->const_and_shader_buffers
[sh
]) ||
2786 si_sampler_views_check_encrypted(sctx
, &sctx
->samplers
[sh
], info
->samplers_declared
) ||
2787 si_image_views_check_encrypted(sctx
, &sctx
->images
[sh
], info
->images_declared
) ||
2788 si_buffer_resources_check_encrypted(sctx
, &sctx
->rw_buffers
);
2791 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2793 unsigned sh
= PIPE_SHADER_COMPUTE
;
2795 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2796 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2797 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2798 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2800 if (sctx
->bo_list_add_all_resident_resources
)
2801 si_resident_buffers_add_all_to_bo_list(sctx
);
2803 assert(sctx
->bo_list_add_all_compute_resources
);
2804 sctx
->bo_list_add_all_compute_resources
= false;
2807 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2809 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2810 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2811 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2813 si_shader_pointers_begin_new_cs(sctx
);
2815 sctx
->bo_list_add_all_resident_resources
= true;
2816 sctx
->bo_list_add_all_gfx_resources
= true;
2817 sctx
->bo_list_add_all_compute_resources
= true;
2820 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
, uint64_t new_active_mask
)
2822 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2824 /* Ignore no-op updates and updates that disable all slots. */
2825 if (!new_active_mask
||
2826 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
, desc
->num_active_slots
))
2830 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2831 assert(new_active_mask
== 0);
2833 /* Upload/dump descriptors if slots are being enabled. */
2834 if (first
< desc
->first_active_slot
||
2835 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2836 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2838 desc
->first_active_slot
= first
;
2839 desc
->num_active_slots
= count
;
2842 void si_set_active_descriptors_for_shader(struct si_context
*sctx
, struct si_shader_selector
*sel
)
2847 si_set_active_descriptors(sctx
, si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2848 sel
->active_const_and_shader_buffers
);
2849 si_set_active_descriptors(sctx
, si_sampler_and_image_descriptors_idx(sel
->type
),
2850 sel
->active_samplers_and_images
);