src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <llvm/Config/llvm-config.h>
  37 #include <sys/utsname.h>
  38
  39 static const char *si_get_vendor(struct pipe_screen *pscreen)
  40 {
  41         /* Don't change this. Games such as Alien Isolation are broken if this
  42          * returns "Advanced Micro Devices, Inc."
  43          */
  44         return "X.Org";
  45 }
  46
  47 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  48 {
  49         return "AMD";
  50 }
  51
  52 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  53 {
  54         struct si_screen *sscreen = (struct si_screen *)pscreen;
  55
  56         switch (param) {
  57         /* Supported features (boolean caps). */
  58         case PIPE_CAP_ACCELERATED:
  59         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  60         case PIPE_CAP_ANISOTROPIC_FILTER:
  61         case PIPE_CAP_POINT_SPRITE:
  62         case PIPE_CAP_OCCLUSION_QUERY:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  64         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  65         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  66         case PIPE_CAP_TEXTURE_SWIZZLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  68         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  69         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  70         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  71         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  72         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  74         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  75         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  76         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  77         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  78         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  79         case PIPE_CAP_PRIMITIVE_RESTART:
  80         case PIPE_CAP_CONDITIONAL_RENDER:
  81         case PIPE_CAP_TEXTURE_BARRIER:
  82         case PIPE_CAP_INDEP_BLEND_ENABLE:
  83         case PIPE_CAP_INDEP_BLEND_FUNC:
  84         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  85         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  86         case PIPE_CAP_START_INSTANCE:
  87         case PIPE_CAP_NPOT_TEXTURES:
  88         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  89         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  90         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  91         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  92         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  93         case PIPE_CAP_TGSI_INSTANCEID:
  94         case PIPE_CAP_COMPUTE:
  95         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  96         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  97         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  98         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  99         case PIPE_CAP_CUBE_MAP_ARRAY:
 100         case PIPE_CAP_SAMPLE_SHADING:
 101         case PIPE_CAP_DRAW_INDIRECT:
 102         case PIPE_CAP_CLIP_HALFZ:
 103         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 104         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 105         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 106         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 107         case PIPE_CAP_TGSI_TEXCOORD:
 108         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 109         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 110         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 111         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 112         case PIPE_CAP_SHAREABLE_SHADERS:
 113         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 114         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 115         case PIPE_CAP_TEXTURE_QUERY_LOD:
 116         case PIPE_CAP_TEXTURE_GATHER_SM5:
 117         case PIPE_CAP_TGSI_TXQS:
 118         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 119         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 120         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 121         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 122         case PIPE_CAP_INVALIDATE_BUFFER:
 123         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 124         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 125         case PIPE_CAP_QUERY_MEMORY_INFO:
 126         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 127         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 128         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 129         case PIPE_CAP_GENERATE_MIPMAP:
 130         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 131         case PIPE_CAP_STRING_MARKER:
 132         case PIPE_CAP_CLEAR_TEXTURE:
 133         case PIPE_CAP_CULL_DISTANCE:
 134         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 135         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 136         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 137         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 138         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 139         case PIPE_CAP_DOUBLES:
 140         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 141         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 142         case PIPE_CAP_BINDLESS_TEXTURE:
 143         case PIPE_CAP_QUERY_TIMESTAMP:
 144         case PIPE_CAP_QUERY_TIME_ELAPSED:
 145         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 146         case PIPE_CAP_MEMOBJ:
 147         case PIPE_CAP_LOAD_CONSTBUF:
 148         case PIPE_CAP_INT64:
 149         case PIPE_CAP_INT64_DIVMOD:
 150         case PIPE_CAP_TGSI_CLOCK:
 151         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 152         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 153         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 154         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 155         case PIPE_CAP_TGSI_BALLOT:
 156         case PIPE_CAP_TGSI_VOTE:
 157         case PIPE_CAP_FBFETCH:
 158         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 159         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 160         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 161         case PIPE_CAP_TGSI_DIV:
 162         case PIPE_CAP_PACKED_UNIFORMS:
 163         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 164         case PIPE_CAP_GL_SPIRV:
 165                 return 1;
 166
 167         case PIPE_CAP_QUERY_SO_OVERFLOW:
 168                 return !sscreen->use_ngg_streamout;
 169
 170         case PIPE_CAP_POST_DEPTH_COVERAGE:
 171                 return sscreen->info.chip_class >= GFX10;
 172
 173         case PIPE_CAP_GRAPHICS:
 174                 return sscreen->info.has_graphics;
 175
 176         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 177                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 178
 179         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 180                 return sscreen->info.has_gpu_reset_status_query;
 181
 182         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 183                 return sscreen->info.has_2d_tiling;
 184
 185         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 186                 return SI_MAP_BUFFER_ALIGNMENT;
 187
 188         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 189         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 191         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 192         case PIPE_CAP_MAX_VERTEX_STREAMS:
 193         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 194         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 195                 return 4;
 196
 197         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 198         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 199                 if (!sscreen->info.has_indirect_compute_dispatch)
 200                         return 420;
 201                 return 460;
 202
 203         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 204                 /* Optimal number for good TexSubImage performance on Polaris10. */
 205                 return 64 * 1024 * 1024;
 206
 207         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 208         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 209                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 210
 211         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 212         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 213         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 214                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 215
 216         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 217                 return sscreen->info.has_sparse_vm_mappings ?
 218                                 RADEON_SPARSE_PAGE_SIZE : 0;
 219
 220
 221         /* Unsupported features. */
 222         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 223         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 224         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 225         case PIPE_CAP_USER_VERTEX_BUFFERS:
 226         case PIPE_CAP_FAKE_SW_MSAA:
 227         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 228         case PIPE_CAP_VERTEXID_NOBASE:
 229         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 230         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 231         case PIPE_CAP_UMA:
 232         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 233         case PIPE_CAP_TILE_RASTER_ORDER:
 234         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 235         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 236         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 237         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 238         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 239         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 240         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 241         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 242         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 243         case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 244                 return 0;
 245
 246         case PIPE_CAP_FENCE_SIGNAL:
 247                 return sscreen->info.has_syncobj;
 248
 249         case PIPE_CAP_CONSTBUF0_FLAGS:
 250                 return SI_RESOURCE_FLAG_32BIT;
 251
 252         case PIPE_CAP_NATIVE_FENCE_FD:
 253                 return sscreen->info.has_fence_to_handle;
 254
 255         case PIPE_CAP_DRAW_PARAMETERS:
 256         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 257         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 258                 return sscreen->has_draw_indirect_multi;
 259
 260         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 261                 return 30;
 262
 263         case PIPE_CAP_MAX_VARYINGS:
 264                 return 32;
 265
 266         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 267                 return sscreen->info.chip_class <= GFX8 ?
 268                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 269
 270         /* Stream output. */
 271         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 272         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 273                 return 32*4;
 274
 275         /* Geometry shader output. */
 276         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 277                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 278                  * gfx8 and earlier can do 1024.
 279                  */
 280                 return 256;
 281         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 282                 return 4095;
 283         case PIPE_CAP_MAX_GS_INVOCATIONS:
 284                 /* The closed driver exposes 127, but 125 is the greatest
 285                  * number that works. */
 286                 return 125;
 287
 288         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 289                 return 2048;
 290
 291         /* Texturing. */
 292         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 293                 return 16384;
 294         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 295                 return 15; /* 16384 */
 296         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 297                 if (sscreen->info.chip_class >= GFX10)
 298                         return 14;
 299                 /* textures support 8192, but layered rendering supports 2048 */
 300                 return 12;
 301         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 302                 if (sscreen->info.chip_class >= GFX10)
 303                         return 8192;
 304                 /* textures support 8192, but layered rendering supports 2048 */
 305                 return 2048;
 306
 307         /* Viewports and render targets. */
 308         case PIPE_CAP_MAX_VIEWPORTS:
 309                 return SI_MAX_VIEWPORTS;
 310         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 311         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 312         case PIPE_CAP_MAX_RENDER_TARGETS:
 313                 return 8;
 314         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 315                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 316
 317         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 318         case PIPE_CAP_MIN_TEXEL_OFFSET:
 319                 return -32;
 320
 321         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 322         case PIPE_CAP_MAX_TEXEL_OFFSET:
 323                 return 31;
 324
 325         case PIPE_CAP_ENDIANNESS:
 326                 return PIPE_ENDIAN_LITTLE;
 327
 328         case PIPE_CAP_VENDOR_ID:
 329                 return ATI_VENDOR_ID;
 330         case PIPE_CAP_DEVICE_ID:
 331                 return sscreen->info.pci_id;
 332         case PIPE_CAP_VIDEO_MEMORY:
 333                 return sscreen->info.vram_size >> 20;
 334         case PIPE_CAP_PCI_GROUP:
 335                 return sscreen->info.pci_domain;
 336         case PIPE_CAP_PCI_BUS:
 337                 return sscreen->info.pci_bus;
 338         case PIPE_CAP_PCI_DEVICE:
 339                 return sscreen->info.pci_dev;
 340         case PIPE_CAP_PCI_FUNCTION:
 341                 return sscreen->info.pci_func;
 342         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 343                 return LLVM_VERSION_MAJOR >= 10;
 344
 345         default:
 346                 return u_pipe_screen_get_param_defaults(pscreen, param);
 347         }
 348 }
 349
 350 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 351 {
 352         switch (param) {
 353         case PIPE_CAPF_MAX_LINE_WIDTH:
 354         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355                 /* This depends on the quant mode, though the precise interactions
 356                  * are unknown. */
 357                 return 2048;
 358         case PIPE_CAPF_MAX_POINT_WIDTH:
 359         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 360                 return SI_MAX_POINT_SIZE;
 361         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 362                 return 16.0f;
 363         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 364                 return 16.0f;
 365         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 366         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 367         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 368                 return 0.0f;
 369         }
 370         return 0.0f;
 371 }
 372
 373 static int si_get_shader_param(struct pipe_screen* pscreen,
 374                                enum pipe_shader_type shader,
 375                                enum pipe_shader_cap param)
 376 {
 377         struct si_screen *sscreen = (struct si_screen *)pscreen;
 378
 379         switch(shader)
 380         {
 381         case PIPE_SHADER_FRAGMENT:
 382         case PIPE_SHADER_VERTEX:
 383         case PIPE_SHADER_GEOMETRY:
 384         case PIPE_SHADER_TESS_CTRL:
 385         case PIPE_SHADER_TESS_EVAL:
 386                 break;
 387         case PIPE_SHADER_COMPUTE:
 388                 switch (param) {
 389                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 390                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 391
 392                         if (sscreen->info.has_indirect_compute_dispatch)
 393                                 ir |= 1 << PIPE_SHADER_IR_NIR;
 394
 395                         return ir;
 396                 }
 397
 398                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 399                         uint64_t max_const_buffer_size;
 400                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 401                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 402                                 &max_const_buffer_size);
 403                         return MIN2(max_const_buffer_size, INT_MAX);
 404                 }
 405                 default:
 406                         /* If compute shaders don't require a special value
 407                          * for this cap, we can return the same value we
 408                          * do for other shader types. */
 409                         break;
 410                 }
 411                 break;
 412         default:
 413                 return 0;
 414         }
 415
 416         switch (param) {
 417         /* Shader limits. */
 418         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 419         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 420         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 421         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 422         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 423                 return 16384;
 424         case PIPE_SHADER_CAP_MAX_INPUTS:
 425                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 426         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 427                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 428         case PIPE_SHADER_CAP_MAX_TEMPS:
 429                 return 256; /* Max native temporaries. */
 430         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 431                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 432         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 433                 return SI_NUM_CONST_BUFFERS;
 434         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 435         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 436                 return SI_NUM_SAMPLERS;
 437         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 438                 return SI_NUM_SHADER_BUFFERS;
 439         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 440                 return SI_NUM_IMAGES;
 441         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 442                 return 0;
 443         case PIPE_SHADER_CAP_PREFERRED_IR:
 444                 return PIPE_SHADER_IR_NIR;
 445         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 446                 return 4;
 447
 448         /* Supported boolean features. */
 449         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 450         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 451         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 452         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 453         case PIPE_SHADER_CAP_INTEGERS:
 454         case PIPE_SHADER_CAP_INT64_ATOMICS:
 455         case PIPE_SHADER_CAP_FP16:
 456         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 458         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 459         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 460         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 461         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 462                 return 1;
 463
 464         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 465                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 466                 if (shader == PIPE_SHADER_GEOMETRY)
 467                         return 0;
 468
 469                 if (shader == PIPE_SHADER_VERTEX &&
 470                     !sscreen->llvm_has_working_vgpr_indexing)
 471                         return 0;
 472
 473                 /* TCS and TES load inputs directly from LDS or offchip
 474                  * memory, so indirect indexing is always supported.
 475                  * PS has to support indirect indexing, because we can't
 476                  * lower that to TEMPs for INTERP instructions.
 477                  */
 478                 return 1;
 479
 480         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 481                 return sscreen->llvm_has_working_vgpr_indexing ||
 482                        /* TCS stores outputs directly to memory. */
 483                        shader == PIPE_SHADER_TESS_CTRL;
 484
 485         /* Unsupported boolean features. */
 486         case PIPE_SHADER_CAP_SUBROUTINES:
 487         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 488         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 489         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 490                 return 0;
 491         }
 492         return 0;
 493 }
 494
 495 static const struct nir_shader_compiler_options nir_options = {
 496         .lower_scmp = true,
 497         .lower_flrp32 = true,
 498         .lower_flrp64 = true,
 499         .lower_fsat = true,
 500         .lower_fdiv = true,
 501         .lower_bitfield_insert_to_bitfield_select = true,
 502         .lower_bitfield_extract = true,
 503         .lower_sub = true,
 504         .fuse_ffma = true,
 505         .lower_fmod = true,
 506         .lower_pack_snorm_4x8 = true,
 507         .lower_pack_unorm_4x8 = true,
 508         .lower_unpack_snorm_2x16 = true,
 509         .lower_unpack_snorm_4x8 = true,
 510         .lower_unpack_unorm_2x16 = true,
 511         .lower_unpack_unorm_4x8 = true,
 512         .lower_extract_byte = true,
 513         .lower_extract_word = true,
 514         .lower_rotate = true,
 515         .lower_to_scalar = true,
 516         .optimize_sample_mask_in = true,
 517         .max_unroll_iterations = 32,
 518         .use_interpolated_input_intrinsics = true,
 519 };
 520
 521 static const void *
 522 si_get_compiler_options(struct pipe_screen *screen,
 523                         enum pipe_shader_ir ir,
 524                         enum pipe_shader_type shader)
 525 {
 526         assert(ir == PIPE_SHADER_IR_NIR);
 527         return &nir_options;
 528 }
 529
 530 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 531 {
 532         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 533 }
 534
 535 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 536 {
 537         struct si_screen *sscreen = (struct si_screen *)pscreen;
 538
 539         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 540 }
 541
 542 static const char* si_get_name(struct pipe_screen *pscreen)
 543 {
 544         struct si_screen *sscreen = (struct si_screen*)pscreen;
 545
 546         return sscreen->renderer_string;
 547 }
 548
 549 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 550                                         enum pipe_video_profile profile,
 551                                         enum pipe_video_entrypoint entrypoint,
 552                                         enum pipe_video_cap param)
 553 {
 554         switch (param) {
 555         case PIPE_VIDEO_CAP_SUPPORTED:
 556                 return vl_profile_supported(screen, profile, entrypoint);
 557         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 558                 return 1;
 559         case PIPE_VIDEO_CAP_MAX_WIDTH:
 560         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 561                 return vl_video_buffer_max_size(screen);
 562         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 563                 return PIPE_FORMAT_NV12;
 564         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 565                 return false;
 566         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 567                 return false;
 568         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 569                 return true;
 570         case PIPE_VIDEO_CAP_MAX_LEVEL:
 571                 return vl_level_supported(screen, profile);
 572         default:
 573                 return 0;
 574         }
 575 }
 576
 577 static int si_get_video_param(struct pipe_screen *screen,
 578                               enum pipe_video_profile profile,
 579                               enum pipe_video_entrypoint entrypoint,
 580                               enum pipe_video_cap param)
 581 {
 582         struct si_screen *sscreen = (struct si_screen *)screen;
 583         enum pipe_video_format codec = u_reduce_video_profile(profile);
 584
 585         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 586                 switch (param) {
 587                 case PIPE_VIDEO_CAP_SUPPORTED:
 588                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 589                                 (si_vce_is_fw_version_supported(sscreen) ||
 590                                 sscreen->info.family >= CHIP_RAVEN)) ||
 591                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 592                                 (sscreen->info.family >= CHIP_RAVEN ||
 593                                 si_radeon_uvd_enc_supported(sscreen)));
 594                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 595                         return 1;
 596                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 597                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 598                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 599                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 600                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 601                         return PIPE_FORMAT_NV12;
 602                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 603                         return false;
 604                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 605                         return false;
 606                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 607                         return true;
 608                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 609                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 610                 default:
 611                         return 0;
 612                 }
 613         }
 614
 615         switch (param) {
 616         case PIPE_VIDEO_CAP_SUPPORTED:
 617                 switch (codec) {
 618                 case PIPE_VIDEO_FORMAT_MPEG12:
 619                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 620                 case PIPE_VIDEO_FORMAT_MPEG4:
 621                         return 1;
 622                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 623                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 624                              sscreen->info.family == CHIP_POLARIS11) &&
 625                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 626                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 627                                 return false;
 628                         }
 629                         return true;
 630                 case PIPE_VIDEO_FORMAT_VC1:
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_HEVC:
 633                         /* Carrizo only supports HEVC Main */
 634                         if (sscreen->info.family >= CHIP_STONEY)
 635                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 636                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 637                         else if (sscreen->info.family >= CHIP_CARRIZO)
 638                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 639                         return false;
 640                 case PIPE_VIDEO_FORMAT_JPEG:
 641                         if (sscreen->info.family >= CHIP_RAVEN)
 642                                 return true;
 643                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 644                                 return false;
 645                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 646                                 RVID_ERR("No MJPEG support for the kernel version\n");
 647                                 return false;
 648                         }
 649                         return true;
 650                 case PIPE_VIDEO_FORMAT_VP9:
 651                         if (sscreen->info.family < CHIP_RAVEN)
 652                                 return false;
 653                         return true;
 654                 default:
 655                         return false;
 656                 }
 657         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 658                 return 1;
 659         case PIPE_VIDEO_CAP_MAX_WIDTH:
 660                 switch (codec) {
 661                 case PIPE_VIDEO_FORMAT_HEVC:
 662                 case PIPE_VIDEO_FORMAT_VP9:
 663                         return (sscreen->info.family < CHIP_RENOIR) ?
 664                                ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
 665                                8192;
 666                 default:
 667                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 668                 }
 669         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 670                 switch (codec) {
 671                 case PIPE_VIDEO_FORMAT_HEVC:
 672                 case PIPE_VIDEO_FORMAT_VP9:
 673                         return (sscreen->info.family < CHIP_RENOIR) ?
 674                                ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
 675                                4352;
 676                 default:
 677                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 678                 }
 679         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 680                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 681                         return PIPE_FORMAT_P010;
 682                 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 683                         return PIPE_FORMAT_P016;
 684                 else
 685                         return PIPE_FORMAT_NV12;
 686
 687         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 688         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 689                 enum pipe_video_format format = u_reduce_video_profile(profile);
 690
 691                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 692                         return false; //The firmware doesn't support interlaced HEVC.
 693                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 694                         return false;
 695                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 696                         return false;
 697                 return true;
 698         }
 699         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 700                 return true;
 701         case PIPE_VIDEO_CAP_MAX_LEVEL:
 702                 switch (profile) {
 703                 case PIPE_VIDEO_PROFILE_MPEG1:
 704                         return 0;
 705                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 706                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 707                         return 3;
 708                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 709                         return 3;
 710                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 711                         return 5;
 712                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 713                         return 1;
 714                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 715                         return 2;
 716                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 717                         return 4;
 718                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 719                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 720                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 721                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 722                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 723                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 724                         return 186;
 725                 default:
 726                         return 0;
 727                 }
 728         default:
 729                 return 0;
 730         }
 731 }
 732
 733 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 734                                        enum pipe_format format,
 735                                        enum pipe_video_profile profile,
 736                                        enum pipe_video_entrypoint entrypoint)
 737 {
 738         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 739         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 740                 return (format == PIPE_FORMAT_NV12) ||
 741                         (format == PIPE_FORMAT_P016);
 742
 743         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 744         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 745                 return format == PIPE_FORMAT_P016;
 746
 747
 748         /* we can only handle this one with UVD */
 749         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 750                 return format == PIPE_FORMAT_NV12;
 751
 752         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 753 }
 754
 755 static unsigned get_max_threads_per_block(struct si_screen *screen,
 756                                           enum pipe_shader_ir ir_type)
 757 {
 758         if (ir_type == PIPE_SHADER_IR_NATIVE)
 759                 return 256;
 760
 761         /* LLVM 10 only supports 1024 threads per block. */
 762         return 1024;
 763 }
 764
 765 static int si_get_compute_param(struct pipe_screen *screen,
 766                                 enum pipe_shader_ir ir_type,
 767                                 enum pipe_compute_cap param,
 768                                 void *ret)
 769 {
 770         struct si_screen *sscreen = (struct si_screen *)screen;
 771
 772         //TODO: select these params by asic
 773         switch (param) {
 774         case PIPE_COMPUTE_CAP_IR_TARGET: {
 775                 const char *gpu, *triple;
 776
 777                 triple = "amdgcn-mesa-mesa3d";
 778                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 779                 if (ret) {
 780                         sprintf(ret, "%s-%s", gpu, triple);
 781                 }
 782                 /* +2 for dash and terminating NIL byte */
 783                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 784         }
 785         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 786                 if (ret) {
 787                         uint64_t *grid_dimension = ret;
 788                         grid_dimension[0] = 3;
 789                 }
 790                 return 1 * sizeof(uint64_t);
 791
 792         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 793                 if (ret) {
 794                         uint64_t *grid_size = ret;
 795                         grid_size[0] = 65535;
 796                         grid_size[1] = 65535;
 797                         grid_size[2] = 65535;
 798                 }
 799                 return 3 * sizeof(uint64_t) ;
 800
 801         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 802                 if (ret) {
 803                         uint64_t *block_size = ret;
 804                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 805                         block_size[0] = threads_per_block;
 806                         block_size[1] = threads_per_block;
 807                         block_size[2] = threads_per_block;
 808                 }
 809                 return 3 * sizeof(uint64_t);
 810
 811         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 812                 if (ret) {
 813                         uint64_t *max_threads_per_block = ret;
 814                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 815                 }
 816                 return sizeof(uint64_t);
 817         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 818                 if (ret) {
 819                         uint32_t *address_bits = ret;
 820                         address_bits[0] = 64;
 821                 }
 822                 return 1 * sizeof(uint32_t);
 823
 824         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 825                 if (ret) {
 826                         uint64_t *max_global_size = ret;
 827                         uint64_t max_mem_alloc_size;
 828
 829                         si_get_compute_param(screen, ir_type,
 830                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 831                                 &max_mem_alloc_size);
 832
 833                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 834                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 835                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 836                          * make sure we never report more than
 837                          * 4 * MAX_MEM_ALLOC_SIZE.
 838                          */
 839                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 840                                                 MAX2(sscreen->info.gart_size,
 841                                                      sscreen->info.vram_size));
 842                 }
 843                 return sizeof(uint64_t);
 844
 845         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 846                 if (ret) {
 847                         uint64_t *max_local_size = ret;
 848                         /* Value reported by the closed source driver. */
 849                         *max_local_size = 32768;
 850                 }
 851                 return sizeof(uint64_t);
 852
 853         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 854                 if (ret) {
 855                         uint64_t *max_input_size = ret;
 856                         /* Value reported by the closed source driver. */
 857                         *max_input_size = 1024;
 858                 }
 859                 return sizeof(uint64_t);
 860
 861         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 862                 if (ret) {
 863                         uint64_t *max_mem_alloc_size = ret;
 864
 865                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 866                 }
 867                 return sizeof(uint64_t);
 868
 869         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 870                 if (ret) {
 871                         uint32_t *max_clock_frequency = ret;
 872                         *max_clock_frequency = sscreen->info.max_shader_clock;
 873                 }
 874                 return sizeof(uint32_t);
 875
 876         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 877                 if (ret) {
 878                         uint32_t *max_compute_units = ret;
 879                         *max_compute_units = sscreen->info.num_good_compute_units;
 880                 }
 881                 return sizeof(uint32_t);
 882
 883         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 884                 if (ret) {
 885                         uint32_t *images_supported = ret;
 886                         *images_supported = 0;
 887                 }
 888                 return sizeof(uint32_t);
 889         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 890                 break; /* unused */
 891         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 892                 if (ret) {
 893                         uint32_t *subgroup_size = ret;
 894                         *subgroup_size = sscreen->compute_wave_size;
 895                 }
 896                 return sizeof(uint32_t);
 897         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 898                 if (ret) {
 899                         uint64_t *max_variable_threads_per_block = ret;
 900                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 901                                 *max_variable_threads_per_block = 0;
 902                         else
 903                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 904                 }
 905                 return sizeof(uint64_t);
 906         }
 907
 908         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 909         return 0;
 910 }
 911
 912 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 913 {
 914         struct si_screen *sscreen = (struct si_screen*)screen;
 915
 916         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 917                         sscreen->info.clock_crystal_freq;
 918 }
 919
 920 static void si_query_memory_info(struct pipe_screen *screen,
 921                                  struct pipe_memory_info *info)
 922 {
 923         struct si_screen *sscreen = (struct si_screen*)screen;
 924         struct radeon_winsys *ws = sscreen->ws;
 925         unsigned vram_usage, gtt_usage;
 926
 927         info->total_device_memory = sscreen->info.vram_size / 1024;
 928         info->total_staging_memory = sscreen->info.gart_size / 1024;
 929
 930         /* The real TTM memory usage is somewhat random, because:
 931          *
 932          * 1) TTM delays freeing memory, because it can only free it after
 933          *    fences expire.
 934          *
 935          * 2) The memory usage can be really low if big VRAM evictions are
 936          *    taking place, but the real usage is well above the size of VRAM.
 937          *
 938          * Instead, return statistics of this process.
 939          */
 940         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 941         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 942
 943         info->avail_device_memory =
 944                 vram_usage <= info->total_device_memory ?
 945                                 info->total_device_memory - vram_usage : 0;
 946         info->avail_staging_memory =
 947                 gtt_usage <= info->total_staging_memory ?
 948                                 info->total_staging_memory - gtt_usage : 0;
 949
 950         info->device_memory_evicted =
 951                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 952
 953         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 954                 info->nr_device_memory_evictions =
 955                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 956         else
 957                 /* Just return the number of evicted 64KB pages. */
 958                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 959 }
 960
 961 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 962 {
 963         struct si_screen *sscreen = (struct si_screen*)pscreen;
 964
 965         return sscreen->disk_shader_cache;
 966 }
 967
 968 static void si_init_renderer_string(struct si_screen *sscreen)
 969 {
 970         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 971         struct utsname uname_data;
 972
 973         if (sscreen->info.marketing_name) {
 974                 snprintf(first_name, sizeof(first_name), "%s",
 975                          sscreen->info.marketing_name);
 976                 snprintf(second_name, sizeof(second_name), "%s, ",
 977                          sscreen->info.name);
 978         } else {
 979                 snprintf(first_name, sizeof(first_name), "AMD %s",
 980                          sscreen->info.name);
 981         }
 982
 983         if (uname(&uname_data) == 0)
 984                 snprintf(kernel_version, sizeof(kernel_version),
 985                          ", %s", uname_data.release);
 986
 987         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 988                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 989                  first_name, second_name, sscreen->info.drm_major,
 990                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 991                  kernel_version);
 992 }
 993
 994 void si_init_screen_get_functions(struct si_screen *sscreen)
 995 {
 996         sscreen->b.get_name = si_get_name;
 997         sscreen->b.get_vendor = si_get_vendor;
 998         sscreen->b.get_device_vendor = si_get_device_vendor;
 999         sscreen->b.get_param = si_get_param;
1000         sscreen->b.get_paramf = si_get_paramf;
1001         sscreen->b.get_compute_param = si_get_compute_param;
1002         sscreen->b.get_timestamp = si_get_timestamp;
1003         sscreen->b.get_shader_param = si_get_shader_param;
1004         sscreen->b.get_compiler_options = si_get_compiler_options;
1005         sscreen->b.get_device_uuid = si_get_device_uuid;
1006         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1007         sscreen->b.query_memory_info = si_query_memory_info;
1008         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1009
1010         if (sscreen->info.has_hw_decode) {
1011                 sscreen->b.get_video_param = si_get_video_param;
1012                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1013         } else {
1014                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1015                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1016         }
1017
1018         si_init_renderer_string(sscreen);
1019 }