src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  52 {
  53         if (!ws->get_chip_name)
  54                 return NULL;
  55         return ws->get_chip_name(ws);
  56 }
  57
  58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60         struct si_screen *sscreen = (struct si_screen *)pscreen;
  61
  62         switch (param) {
  63         /* Supported features (boolean caps). */
  64         case PIPE_CAP_ACCELERATED:
  65         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  66         case PIPE_CAP_ANISOTROPIC_FILTER:
  67         case PIPE_CAP_POINT_SPRITE:
  68         case PIPE_CAP_OCCLUSION_QUERY:
  69         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  70         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72         case PIPE_CAP_TEXTURE_SWIZZLE:
  73         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  74         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  75         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  76         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  77         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  78         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81         case PIPE_CAP_SM3:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  83         case PIPE_CAP_PRIMITIVE_RESTART:
  84         case PIPE_CAP_CONDITIONAL_RENDER:
  85         case PIPE_CAP_TEXTURE_BARRIER:
  86         case PIPE_CAP_INDEP_BLEND_ENABLE:
  87         case PIPE_CAP_INDEP_BLEND_FUNC:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  89         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  90         case PIPE_CAP_START_INSTANCE:
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  93         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  94         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  95         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  96         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97         case PIPE_CAP_TGSI_INSTANCEID:
  98         case PIPE_CAP_COMPUTE:
  99         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 100         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 101         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 102         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 103         case PIPE_CAP_CUBE_MAP_ARRAY:
 104         case PIPE_CAP_SAMPLE_SHADING:
 105         case PIPE_CAP_DRAW_INDIRECT:
 106         case PIPE_CAP_CLIP_HALFZ:
 107         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 108         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 109         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 110         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 111         case PIPE_CAP_TGSI_TEXCOORD:
 112         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 113         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 114         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 115         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 116         case PIPE_CAP_SHAREABLE_SHADERS:
 117         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 118         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 119         case PIPE_CAP_TEXTURE_QUERY_LOD:
 120         case PIPE_CAP_TEXTURE_GATHER_SM5:
 121         case PIPE_CAP_TGSI_TXQS:
 122         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 123         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 124         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 125         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 126         case PIPE_CAP_INVALIDATE_BUFFER:
 127         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 128         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 129         case PIPE_CAP_QUERY_MEMORY_INFO:
 130         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 131         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 132         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 133         case PIPE_CAP_GENERATE_MIPMAP:
 134         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 135         case PIPE_CAP_STRING_MARKER:
 136         case PIPE_CAP_CLEAR_TEXTURE:
 137         case PIPE_CAP_CULL_DISTANCE:
 138         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 139         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 140         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 141         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 142         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143         case PIPE_CAP_DOUBLES:
 144         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 145         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 146         case PIPE_CAP_BINDLESS_TEXTURE:
 147         case PIPE_CAP_QUERY_TIMESTAMP:
 148         case PIPE_CAP_QUERY_TIME_ELAPSED:
 149         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 150         case PIPE_CAP_QUERY_SO_OVERFLOW:
 151         case PIPE_CAP_MEMOBJ:
 152         case PIPE_CAP_LOAD_CONSTBUF:
 153         case PIPE_CAP_INT64:
 154         case PIPE_CAP_INT64_DIVMOD:
 155         case PIPE_CAP_TGSI_CLOCK:
 156         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 157         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 158         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 159         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 160         case PIPE_CAP_TGSI_BALLOT:
 161         case PIPE_CAP_TGSI_VOTE:
 162         case PIPE_CAP_TGSI_FS_FBFETCH:
 163                 return 1;
 164
 165         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 166                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 167
 168         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 169                 return sscreen->info.has_gpu_reset_status_query ||
 170                        sscreen->info.has_gpu_reset_counter_query;
 171
 172         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 173                 return sscreen->info.has_2d_tiling;
 174
 175         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 176                 return SI_MAP_BUFFER_ALIGNMENT;
 177
 178         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 179         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 181         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 182         case PIPE_CAP_MAX_VERTEX_STREAMS:
 183         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 184         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 185                 return 4;
 186
 187         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 188         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 189                 if (sscreen->info.has_indirect_compute_dispatch)
 190                                 return 450;
 191                 return 420;
 192
 193         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 194                 /* Optimal number for good TexSubImage performance on Polaris10. */
 195                 return 64 * 1024 * 1024;
 196
 197         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 198         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 199                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 200
 201         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 202         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 203         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 204                 return !sscreen->info.has_unaligned_shader_loads;
 205
 206         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 207                 return sscreen->info.has_sparse_vm_mappings ?
 208                                 RADEON_SPARSE_PAGE_SIZE : 0;
 209
 210         case PIPE_CAP_PACKED_UNIFORMS:
 211                 if (sscreen->debug_flags & DBG(NIR))
 212                         return 1;
 213                 return 0;
 214
 215         /* Unsupported features. */
 216         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 217         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 218         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 219         case PIPE_CAP_USER_VERTEX_BUFFERS:
 220         case PIPE_CAP_FAKE_SW_MSAA:
 221         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 222         case PIPE_CAP_VERTEXID_NOBASE:
 223         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 224         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 225         case PIPE_CAP_UMA:
 226         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 227         case PIPE_CAP_POST_DEPTH_COVERAGE:
 228         case PIPE_CAP_TILE_RASTER_ORDER:
 229         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 230         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 231         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 232         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 233         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 234         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 235         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 236         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 237         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 238                 return 0;
 239
 240         case PIPE_CAP_FENCE_SIGNAL:
 241                 return sscreen->info.has_syncobj;
 242
 243         case PIPE_CAP_CONSTBUF0_FLAGS:
 244                 return SI_RESOURCE_FLAG_32BIT;
 245
 246         case PIPE_CAP_NATIVE_FENCE_FD:
 247                 return sscreen->info.has_fence_to_handle;
 248
 249         case PIPE_CAP_DRAW_PARAMETERS:
 250         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 251         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 252                 return sscreen->has_draw_indirect_multi;
 253
 254         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 255                 return 30;
 256
 257         case PIPE_CAP_MAX_VARYINGS:
 258                 return 32;
 259
 260         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 261                 return sscreen->info.chip_class <= VI ?
 262                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 263
 264         /* Stream output. */
 265         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 266         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 267                 return 32*4;
 268
 269         /* Geometry shader output. */
 270         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 271                 return 1024;
 272         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 273                 return 4095;
 274         case PIPE_CAP_MAX_GS_INVOCATIONS:
 275                 /* The closed driver exposes 127, but 125 is the greatest
 276                  * number that works. */
 277                 return 125;
 278
 279         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 280                 return 2048;
 281
 282         /* Texturing. */
 283         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 284         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 285                 return 15; /* 16384 */
 286         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 287                 /* textures support 8192, but layered rendering supports 2048 */
 288                 return 12;
 289         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 290                 /* textures support 8192, but layered rendering supports 2048 */
 291                 return 2048;
 292
 293         /* Viewports and render targets. */
 294         case PIPE_CAP_MAX_VIEWPORTS:
 295                 return SI_MAX_VIEWPORTS;
 296         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 297         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 298         case PIPE_CAP_MAX_RENDER_TARGETS:
 299                 return 8;
 300         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 301                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 302
 303         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304         case PIPE_CAP_MIN_TEXEL_OFFSET:
 305                 return -32;
 306
 307         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 308         case PIPE_CAP_MAX_TEXEL_OFFSET:
 309                 return 31;
 310
 311         case PIPE_CAP_ENDIANNESS:
 312                 return PIPE_ENDIAN_LITTLE;
 313
 314         case PIPE_CAP_VENDOR_ID:
 315                 return ATI_VENDOR_ID;
 316         case PIPE_CAP_DEVICE_ID:
 317                 return sscreen->info.pci_id;
 318         case PIPE_CAP_VIDEO_MEMORY:
 319                 return sscreen->info.vram_size >> 20;
 320         case PIPE_CAP_PCI_GROUP:
 321                 return sscreen->info.pci_domain;
 322         case PIPE_CAP_PCI_BUS:
 323                 return sscreen->info.pci_bus;
 324         case PIPE_CAP_PCI_DEVICE:
 325                 return sscreen->info.pci_dev;
 326         case PIPE_CAP_PCI_FUNCTION:
 327                 return sscreen->info.pci_func;
 328
 329         default:
 330                 return u_pipe_screen_get_param_defaults(pscreen, param);
 331         }
 332 }
 333
 334 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 335 {
 336         switch (param) {
 337         case PIPE_CAPF_MAX_LINE_WIDTH:
 338         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339                 /* This depends on the quant mode, though the precise interactions
 340                  * are unknown. */
 341                 return 2048;
 342         case PIPE_CAPF_MAX_POINT_WIDTH:
 343         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 344                 return SI_MAX_POINT_SIZE;
 345         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 346                 return 16.0f;
 347         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 348                 return 16.0f;
 349         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 350         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 351         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 352                 return 0.0f;
 353         }
 354         return 0.0f;
 355 }
 356
 357 static int si_get_shader_param(struct pipe_screen* pscreen,
 358                                enum pipe_shader_type shader,
 359                                enum pipe_shader_cap param)
 360 {
 361         struct si_screen *sscreen = (struct si_screen *)pscreen;
 362
 363         switch(shader)
 364         {
 365         case PIPE_SHADER_FRAGMENT:
 366         case PIPE_SHADER_VERTEX:
 367         case PIPE_SHADER_GEOMETRY:
 368         case PIPE_SHADER_TESS_CTRL:
 369         case PIPE_SHADER_TESS_EVAL:
 370                 break;
 371         case PIPE_SHADER_COMPUTE:
 372                 switch (param) {
 373                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 374                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 375
 376                         if (sscreen->info.has_indirect_compute_dispatch)
 377                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 378
 379                         return ir;
 380                 }
 381
 382                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 383                         uint64_t max_const_buffer_size;
 384                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 385                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 386                                 &max_const_buffer_size);
 387                         return MIN2(max_const_buffer_size, INT_MAX);
 388                 }
 389                 default:
 390                         /* If compute shaders don't require a special value
 391                          * for this cap, we can return the same value we
 392                          * do for other shader types. */
 393                         break;
 394                 }
 395                 break;
 396         default:
 397                 return 0;
 398         }
 399
 400         switch (param) {
 401         /* Shader limits. */
 402         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 403         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 404         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 405         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 406         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 407                 return 16384;
 408         case PIPE_SHADER_CAP_MAX_INPUTS:
 409                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 410         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 411                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 412         case PIPE_SHADER_CAP_MAX_TEMPS:
 413                 return 256; /* Max native temporaries. */
 414         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 415                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 416         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 417                 return SI_NUM_CONST_BUFFERS;
 418         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 419         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 420                 return SI_NUM_SAMPLERS;
 421         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 422                 return SI_NUM_SHADER_BUFFERS;
 423         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 424                 return SI_NUM_IMAGES;
 425         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 426                 if (sscreen->debug_flags & DBG(NIR))
 427                         return 0;
 428                 return 32;
 429         case PIPE_SHADER_CAP_PREFERRED_IR:
 430                 if (sscreen->debug_flags & DBG(NIR))
 431                         return PIPE_SHADER_IR_NIR;
 432                 return PIPE_SHADER_IR_TGSI;
 433         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 434                 return 4;
 435
 436         /* Supported boolean features. */
 437         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 438         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 439         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 440         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 441         case PIPE_SHADER_CAP_INTEGERS:
 442         case PIPE_SHADER_CAP_INT64_ATOMICS:
 443         case PIPE_SHADER_CAP_FP16:
 444         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 445         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 446         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 447         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 448         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 449         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 450                 return 1;
 451
 452         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 453                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 454                 if (shader == PIPE_SHADER_GEOMETRY)
 455                         return 0;
 456
 457                 if (shader == PIPE_SHADER_VERTEX &&
 458                     !sscreen->llvm_has_working_vgpr_indexing)
 459                         return 0;
 460
 461                 /* TCS and TES load inputs directly from LDS or offchip
 462                  * memory, so indirect indexing is always supported.
 463                  * PS has to support indirect indexing, because we can't
 464                  * lower that to TEMPs for INTERP instructions.
 465                  */
 466                 return 1;
 467
 468         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 469                 return sscreen->llvm_has_working_vgpr_indexing ||
 470                        /* TCS stores outputs directly to memory. */
 471                        shader == PIPE_SHADER_TESS_CTRL;
 472
 473         /* Unsupported boolean features. */
 474         case PIPE_SHADER_CAP_SUBROUTINES:
 475         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 476         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 477         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 478                 return 0;
 479         case PIPE_SHADER_CAP_SCALAR_ISA:
 480                 return 1;
 481         }
 482         return 0;
 483 }
 484
 485 static const struct nir_shader_compiler_options nir_options = {
 486         .lower_scmp = true,
 487         .lower_flrp32 = true,
 488         .lower_flrp64 = true,
 489         .lower_fsat = true,
 490         .lower_fdiv = true,
 491         .lower_sub = true,
 492         .lower_ffma = true,
 493         .lower_pack_snorm_2x16 = true,
 494         .lower_pack_snorm_4x8 = true,
 495         .lower_pack_unorm_2x16 = true,
 496         .lower_pack_unorm_4x8 = true,
 497         .lower_unpack_snorm_2x16 = true,
 498         .lower_unpack_snorm_4x8 = true,
 499         .lower_unpack_unorm_2x16 = true,
 500         .lower_unpack_unorm_4x8 = true,
 501         .lower_extract_byte = true,
 502         .lower_extract_word = true,
 503         .max_unroll_iterations = 32,
 504         .native_integers = true,
 505 };
 506
 507 static const void *
 508 si_get_compiler_options(struct pipe_screen *screen,
 509                         enum pipe_shader_ir ir,
 510                         enum pipe_shader_type shader)
 511 {
 512         assert(ir == PIPE_SHADER_IR_NIR);
 513         return &nir_options;
 514 }
 515
 516 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 517 {
 518         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 519 }
 520
 521 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 522 {
 523         struct si_screen *sscreen = (struct si_screen *)pscreen;
 524
 525         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 526 }
 527
 528 static const char* si_get_name(struct pipe_screen *pscreen)
 529 {
 530         struct si_screen *sscreen = (struct si_screen*)pscreen;
 531
 532         return sscreen->renderer_string;
 533 }
 534
 535 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 536                                         enum pipe_video_profile profile,
 537                                         enum pipe_video_entrypoint entrypoint,
 538                                         enum pipe_video_cap param)
 539 {
 540         switch (param) {
 541         case PIPE_VIDEO_CAP_SUPPORTED:
 542                 return vl_profile_supported(screen, profile, entrypoint);
 543         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 544                 return 1;
 545         case PIPE_VIDEO_CAP_MAX_WIDTH:
 546         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 547                 return vl_video_buffer_max_size(screen);
 548         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 549                 return PIPE_FORMAT_NV12;
 550         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 551                 return false;
 552         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 553                 return false;
 554         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 555                 return true;
 556         case PIPE_VIDEO_CAP_MAX_LEVEL:
 557                 return vl_level_supported(screen, profile);
 558         default:
 559                 return 0;
 560         }
 561 }
 562
 563 static int si_get_video_param(struct pipe_screen *screen,
 564                               enum pipe_video_profile profile,
 565                               enum pipe_video_entrypoint entrypoint,
 566                               enum pipe_video_cap param)
 567 {
 568         struct si_screen *sscreen = (struct si_screen *)screen;
 569         enum pipe_video_format codec = u_reduce_video_profile(profile);
 570
 571         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 572                 switch (param) {
 573                 case PIPE_VIDEO_CAP_SUPPORTED:
 574                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 575                                 (si_vce_is_fw_version_supported(sscreen) ||
 576                                  sscreen->info.family == CHIP_RAVEN ||
 577                                  sscreen->info.family == CHIP_RAVEN2)) ||
 578                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 579                                 (sscreen->info.family == CHIP_RAVEN ||
 580                                  sscreen->info.family == CHIP_RAVEN2 ||
 581                                  si_radeon_uvd_enc_supported(sscreen)));
 582                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 583                         return 1;
 584                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 585                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 586                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 587                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 588                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 589                         return PIPE_FORMAT_NV12;
 590                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 591                         return false;
 592                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 593                         return false;
 594                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 595                         return true;
 596                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 597                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 598                 default:
 599                         return 0;
 600                 }
 601         }
 602
 603         switch (param) {
 604         case PIPE_VIDEO_CAP_SUPPORTED:
 605                 switch (codec) {
 606                 case PIPE_VIDEO_FORMAT_MPEG12:
 607                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 608                 case PIPE_VIDEO_FORMAT_MPEG4:
 609                         return 1;
 610                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 611                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 612                              sscreen->info.family == CHIP_POLARIS11) &&
 613                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 614                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 615                                 return false;
 616                         }
 617                         return true;
 618                 case PIPE_VIDEO_FORMAT_VC1:
 619                         return true;
 620                 case PIPE_VIDEO_FORMAT_HEVC:
 621                         /* Carrizo only supports HEVC Main */
 622                         if (sscreen->info.family >= CHIP_STONEY)
 623                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 624                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 625                         else if (sscreen->info.family >= CHIP_CARRIZO)
 626                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 627                         return false;
 628                 case PIPE_VIDEO_FORMAT_JPEG:
 629                         if (sscreen->info.family == CHIP_RAVEN ||
 630                             sscreen->info.family == CHIP_RAVEN2)
 631                                 return true;
 632                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 633                                 return false;
 634                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 635                                 RVID_ERR("No MJPEG support for the kernel version\n");
 636                                 return false;
 637                         }
 638                         return true;
 639                 case PIPE_VIDEO_FORMAT_VP9:
 640                         if (sscreen->info.family < CHIP_RAVEN)
 641                                 return false;
 642                         return true;
 643                 default:
 644                         return false;
 645                 }
 646         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 647                 return 1;
 648         case PIPE_VIDEO_CAP_MAX_WIDTH:
 649                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 650         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 651                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 652         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 653                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 654                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 655                         return PIPE_FORMAT_P016;
 656                 else
 657                         return PIPE_FORMAT_NV12;
 658
 659         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 660         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 661                 enum pipe_video_format format = u_reduce_video_profile(profile);
 662
 663                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 664                         return false; //The firmware doesn't support interlaced HEVC.
 665                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 666                         return false;
 667                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 668                         return false;
 669                 return true;
 670         }
 671         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 672                 return true;
 673         case PIPE_VIDEO_CAP_MAX_LEVEL:
 674                 switch (profile) {
 675                 case PIPE_VIDEO_PROFILE_MPEG1:
 676                         return 0;
 677                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 678                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 679                         return 3;
 680                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 681                         return 3;
 682                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 683                         return 5;
 684                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 685                         return 1;
 686                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 687                         return 2;
 688                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 689                         return 4;
 690                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 691                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 692                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 693                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 694                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 695                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 696                         return 186;
 697                 default:
 698                         return 0;
 699                 }
 700         default:
 701                 return 0;
 702         }
 703 }
 704
 705 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 706                                           enum pipe_format format,
 707                                           enum pipe_video_profile profile,
 708                                           enum pipe_video_entrypoint entrypoint)
 709 {
 710         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 711         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 712                 return (format == PIPE_FORMAT_NV12) ||
 713                         (format == PIPE_FORMAT_P016);
 714
 715         /* we can only handle this one with UVD */
 716         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 717                 return format == PIPE_FORMAT_NV12;
 718
 719         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 720 }
 721
 722 static unsigned get_max_threads_per_block(struct si_screen *screen,
 723                                           enum pipe_shader_ir ir_type)
 724 {
 725         if (ir_type == PIPE_SHADER_IR_NATIVE)
 726                 return 256;
 727
 728         /* Only 16 waves per thread-group on gfx9. */
 729         if (screen->info.chip_class >= GFX9)
 730                 return 1024;
 731
 732         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 733          * round number.
 734          */
 735         return 2048;
 736 }
 737
 738 static int si_get_compute_param(struct pipe_screen *screen,
 739                                 enum pipe_shader_ir ir_type,
 740                                 enum pipe_compute_cap param,
 741                                 void *ret)
 742 {
 743         struct si_screen *sscreen = (struct si_screen *)screen;
 744
 745         //TODO: select these params by asic
 746         switch (param) {
 747         case PIPE_COMPUTE_CAP_IR_TARGET: {
 748                 const char *gpu, *triple;
 749
 750                 triple = "amdgcn-mesa-mesa3d";
 751                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 752                 if (ret) {
 753                         sprintf(ret, "%s-%s", gpu, triple);
 754                 }
 755                 /* +2 for dash and terminating NIL byte */
 756                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 757         }
 758         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 759                 if (ret) {
 760                         uint64_t *grid_dimension = ret;
 761                         grid_dimension[0] = 3;
 762                 }
 763                 return 1 * sizeof(uint64_t);
 764
 765         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 766                 if (ret) {
 767                         uint64_t *grid_size = ret;
 768                         grid_size[0] = 65535;
 769                         grid_size[1] = 65535;
 770                         grid_size[2] = 65535;
 771                 }
 772                 return 3 * sizeof(uint64_t) ;
 773
 774         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 775                 if (ret) {
 776                         uint64_t *block_size = ret;
 777                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 778                         block_size[0] = threads_per_block;
 779                         block_size[1] = threads_per_block;
 780                         block_size[2] = threads_per_block;
 781                 }
 782                 return 3 * sizeof(uint64_t);
 783
 784         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 785                 if (ret) {
 786                         uint64_t *max_threads_per_block = ret;
 787                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 788                 }
 789                 return sizeof(uint64_t);
 790         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 791                 if (ret) {
 792                         uint32_t *address_bits = ret;
 793                         address_bits[0] = 64;
 794                 }
 795                 return 1 * sizeof(uint32_t);
 796
 797         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 798                 if (ret) {
 799                         uint64_t *max_global_size = ret;
 800                         uint64_t max_mem_alloc_size;
 801
 802                         si_get_compute_param(screen, ir_type,
 803                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 804                                 &max_mem_alloc_size);
 805
 806                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 807                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 808                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 809                          * make sure we never report more than
 810                          * 4 * MAX_MEM_ALLOC_SIZE.
 811                          */
 812                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 813                                                 MAX2(sscreen->info.gart_size,
 814                                                      sscreen->info.vram_size));
 815                 }
 816                 return sizeof(uint64_t);
 817
 818         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 819                 if (ret) {
 820                         uint64_t *max_local_size = ret;
 821                         /* Value reported by the closed source driver. */
 822                         *max_local_size = 32768;
 823                 }
 824                 return sizeof(uint64_t);
 825
 826         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 827                 if (ret) {
 828                         uint64_t *max_input_size = ret;
 829                         /* Value reported by the closed source driver. */
 830                         *max_input_size = 1024;
 831                 }
 832                 return sizeof(uint64_t);
 833
 834         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 835                 if (ret) {
 836                         uint64_t *max_mem_alloc_size = ret;
 837
 838                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 839                 }
 840                 return sizeof(uint64_t);
 841
 842         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 843                 if (ret) {
 844                         uint32_t *max_clock_frequency = ret;
 845                         *max_clock_frequency = sscreen->info.max_shader_clock;
 846                 }
 847                 return sizeof(uint32_t);
 848
 849         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 850                 if (ret) {
 851                         uint32_t *max_compute_units = ret;
 852                         *max_compute_units = sscreen->info.num_good_compute_units;
 853                 }
 854                 return sizeof(uint32_t);
 855
 856         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 857                 if (ret) {
 858                         uint32_t *images_supported = ret;
 859                         *images_supported = 0;
 860                 }
 861                 return sizeof(uint32_t);
 862         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 863                 break; /* unused */
 864         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 865                 if (ret) {
 866                         uint32_t *subgroup_size = ret;
 867                         *subgroup_size = 64;
 868                 }
 869                 return sizeof(uint32_t);
 870         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 871                 if (ret) {
 872                         uint64_t *max_variable_threads_per_block = ret;
 873                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 874                                 *max_variable_threads_per_block = 0;
 875                         else
 876                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 877                 }
 878                 return sizeof(uint64_t);
 879         }
 880
 881         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 882         return 0;
 883 }
 884
 885 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 886 {
 887         struct si_screen *sscreen = (struct si_screen*)screen;
 888
 889         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 890                         sscreen->info.clock_crystal_freq;
 891 }
 892
 893 static void si_query_memory_info(struct pipe_screen *screen,
 894                                  struct pipe_memory_info *info)
 895 {
 896         struct si_screen *sscreen = (struct si_screen*)screen;
 897         struct radeon_winsys *ws = sscreen->ws;
 898         unsigned vram_usage, gtt_usage;
 899
 900         info->total_device_memory = sscreen->info.vram_size / 1024;
 901         info->total_staging_memory = sscreen->info.gart_size / 1024;
 902
 903         /* The real TTM memory usage is somewhat random, because:
 904          *
 905          * 1) TTM delays freeing memory, because it can only free it after
 906          *    fences expire.
 907          *
 908          * 2) The memory usage can be really low if big VRAM evictions are
 909          *    taking place, but the real usage is well above the size of VRAM.
 910          *
 911          * Instead, return statistics of this process.
 912          */
 913         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 914         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 915
 916         info->avail_device_memory =
 917                 vram_usage <= info->total_device_memory ?
 918                                 info->total_device_memory - vram_usage : 0;
 919         info->avail_staging_memory =
 920                 gtt_usage <= info->total_staging_memory ?
 921                                 info->total_staging_memory - gtt_usage : 0;
 922
 923         info->device_memory_evicted =
 924                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 925
 926         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 927                 info->nr_device_memory_evictions =
 928                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 929         else
 930                 /* Just return the number of evicted 64KB pages. */
 931                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 932 }
 933
 934 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 935 {
 936         struct si_screen *sscreen = (struct si_screen*)pscreen;
 937
 938         return sscreen->disk_shader_cache;
 939 }
 940
 941 static void si_init_renderer_string(struct si_screen *sscreen)
 942 {
 943         struct radeon_winsys *ws = sscreen->ws;
 944         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 945         struct utsname uname_data;
 946
 947         const char *marketing_name = si_get_marketing_name(ws);
 948
 949         if (marketing_name) {
 950                 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
 951                 snprintf(second_name, sizeof(second_name), "%s, ",
 952                          sscreen->info.name);
 953         } else {
 954                 snprintf(first_name, sizeof(first_name), "AMD %s",
 955                          sscreen->info.name);
 956         }
 957
 958         if (uname(&uname_data) == 0)
 959                 snprintf(kernel_version, sizeof(kernel_version),
 960                          ", %s", uname_data.release);
 961
 962         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 963                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 964                  first_name, second_name, sscreen->info.drm_major,
 965                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 966                  kernel_version,
 967                  (HAVE_LLVM >> 8) & 0xff,
 968                  HAVE_LLVM & 0xff,
 969                  MESA_LLVM_VERSION_PATCH);
 970 }
 971
 972 void si_init_screen_get_functions(struct si_screen *sscreen)
 973 {
 974         sscreen->b.get_name = si_get_name;
 975         sscreen->b.get_vendor = si_get_vendor;
 976         sscreen->b.get_device_vendor = si_get_device_vendor;
 977         sscreen->b.get_param = si_get_param;
 978         sscreen->b.get_paramf = si_get_paramf;
 979         sscreen->b.get_compute_param = si_get_compute_param;
 980         sscreen->b.get_timestamp = si_get_timestamp;
 981         sscreen->b.get_shader_param = si_get_shader_param;
 982         sscreen->b.get_compiler_options = si_get_compiler_options;
 983         sscreen->b.get_device_uuid = si_get_device_uuid;
 984         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 985         sscreen->b.query_memory_info = si_query_memory_info;
 986         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 987
 988         if (sscreen->info.has_hw_decode) {
 989                 sscreen->b.get_video_param = si_get_video_param;
 990                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 991         } else {
 992                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 993                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 994         }
 995
 996         si_init_renderer_string(sscreen);
 997 }