src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_screen.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52         struct si_screen *sscreen = (struct si_screen *)pscreen;
  53
  54         switch (param) {
  55         /* Supported features (boolean caps). */
  56         case PIPE_CAP_ACCELERATED:
  57         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  58         case PIPE_CAP_ANISOTROPIC_FILTER:
  59         case PIPE_CAP_POINT_SPRITE:
  60         case PIPE_CAP_OCCLUSION_QUERY:
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64         case PIPE_CAP_TEXTURE_SWIZZLE:
  65         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77         case PIPE_CAP_PRIMITIVE_RESTART:
  78         case PIPE_CAP_CONDITIONAL_RENDER:
  79         case PIPE_CAP_TEXTURE_BARRIER:
  80         case PIPE_CAP_INDEP_BLEND_ENABLE:
  81         case PIPE_CAP_INDEP_BLEND_FUNC:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  83         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  84         case PIPE_CAP_START_INSTANCE:
  85         case PIPE_CAP_NPOT_TEXTURES:
  86         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  87         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  88         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  89         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  90         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  91         case PIPE_CAP_TGSI_INSTANCEID:
  92         case PIPE_CAP_COMPUTE:
  93         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  95         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  96         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  97         case PIPE_CAP_CUBE_MAP_ARRAY:
  98         case PIPE_CAP_SAMPLE_SHADING:
  99         case PIPE_CAP_DRAW_INDIRECT:
 100         case PIPE_CAP_CLIP_HALFZ:
 101         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 102         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 103         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 104         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 105         case PIPE_CAP_TGSI_TEXCOORD:
 106         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 107         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 108         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 109         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 110         case PIPE_CAP_SHAREABLE_SHADERS:
 111         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 112         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 113         case PIPE_CAP_TEXTURE_QUERY_LOD:
 114         case PIPE_CAP_TEXTURE_GATHER_SM5:
 115         case PIPE_CAP_TGSI_TXQS:
 116         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 117         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 118         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 119         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 120         case PIPE_CAP_INVALIDATE_BUFFER:
 121         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 122         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 123         case PIPE_CAP_QUERY_MEMORY_INFO:
 124         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 125         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 126         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 127         case PIPE_CAP_GENERATE_MIPMAP:
 128         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 129         case PIPE_CAP_STRING_MARKER:
 130         case PIPE_CAP_CLEAR_TEXTURE:
 131         case PIPE_CAP_CULL_DISTANCE:
 132         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 133         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 134         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 135         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 136         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 137         case PIPE_CAP_DOUBLES:
 138         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 139         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 140         case PIPE_CAP_BINDLESS_TEXTURE:
 141         case PIPE_CAP_QUERY_TIMESTAMP:
 142         case PIPE_CAP_QUERY_TIME_ELAPSED:
 143         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 144         case PIPE_CAP_MEMOBJ:
 145         case PIPE_CAP_LOAD_CONSTBUF:
 146         case PIPE_CAP_INT64:
 147         case PIPE_CAP_INT64_DIVMOD:
 148         case PIPE_CAP_TGSI_CLOCK:
 149         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 152         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153         case PIPE_CAP_TGSI_BALLOT:
 154         case PIPE_CAP_TGSI_VOTE:
 155         case PIPE_CAP_FBFETCH:
 156         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159         case PIPE_CAP_TGSI_DIV:
 160         case PIPE_CAP_PACKED_UNIFORMS:
 161         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162         case PIPE_CAP_GL_SPIRV:
 163                 return 1;
 164
 165         case PIPE_CAP_QUERY_SO_OVERFLOW:
 166                 return !sscreen->use_ngg_streamout;
 167
 168         case PIPE_CAP_POST_DEPTH_COVERAGE:
 169                 return sscreen->info.chip_class >= GFX10;
 170
 171         case PIPE_CAP_GRAPHICS:
 172                 return sscreen->info.has_graphics;
 173
 174         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 175                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 176
 177         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 178                 return sscreen->info.has_gpu_reset_status_query;
 179
 180         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 181                 return sscreen->info.has_2d_tiling;
 182
 183         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 184                 return SI_MAP_BUFFER_ALIGNMENT;
 185
 186         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 187         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 188         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 190         case PIPE_CAP_MAX_VERTEX_STREAMS:
 191         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 192         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 193                 return 4;
 194
 195         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 196         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 197                 if (!sscreen->info.has_indirect_compute_dispatch)
 198                         return 420;
 199                 return 460;
 200
 201         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 202                 /* Optimal number for good TexSubImage performance on Polaris10. */
 203                 return 64 * 1024 * 1024;
 204
 205         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 206         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 207                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 208
 209         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 210         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 211         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 212                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 213
 214         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 215                 return sscreen->info.has_sparse_vm_mappings ?
 216                                 RADEON_SPARSE_PAGE_SIZE : 0;
 217
 218
 219         /* Unsupported features. */
 220         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 221         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 222         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 223         case PIPE_CAP_USER_VERTEX_BUFFERS:
 224         case PIPE_CAP_FAKE_SW_MSAA:
 225         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 226         case PIPE_CAP_VERTEXID_NOBASE:
 227         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 228         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 229         case PIPE_CAP_UMA:
 230         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 231         case PIPE_CAP_TILE_RASTER_ORDER:
 232         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 233         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 234         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 235         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 236         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 237         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 238         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 239         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 240         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 241         case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 242                 return 0;
 243
 244         case PIPE_CAP_FENCE_SIGNAL:
 245                 return sscreen->info.has_syncobj;
 246
 247         case PIPE_CAP_CONSTBUF0_FLAGS:
 248                 return SI_RESOURCE_FLAG_32BIT;
 249
 250         case PIPE_CAP_NATIVE_FENCE_FD:
 251                 return sscreen->info.has_fence_to_handle;
 252
 253         case PIPE_CAP_DRAW_PARAMETERS:
 254         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 255         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 256                 return sscreen->has_draw_indirect_multi;
 257
 258         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 259                 return 30;
 260
 261         case PIPE_CAP_MAX_VARYINGS:
 262                 return 32;
 263
 264         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 265                 return sscreen->info.chip_class <= GFX8 ?
 266                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 267
 268         /* Stream output. */
 269         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 270         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 271                 return 32*4;
 272
 273         /* Geometry shader output. */
 274         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 275                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 276                  * gfx8 and earlier can do 1024.
 277                  */
 278                 return 256;
 279         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 280                 return 4095;
 281         case PIPE_CAP_MAX_GS_INVOCATIONS:
 282                 /* The closed driver exposes 127, but 125 is the greatest
 283                  * number that works. */
 284                 return 125;
 285
 286         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 287                 return 2048;
 288
 289         /* Texturing. */
 290         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 291                 return 16384;
 292         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 293                 return 15; /* 16384 */
 294         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 295                 if (sscreen->info.chip_class >= GFX10)
 296                         return 14;
 297                 /* textures support 8192, but layered rendering supports 2048 */
 298                 return 12;
 299         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 300                 if (sscreen->info.chip_class >= GFX10)
 301                         return 8192;
 302                 /* textures support 8192, but layered rendering supports 2048 */
 303                 return 2048;
 304
 305         /* Viewports and render targets. */
 306         case PIPE_CAP_MAX_VIEWPORTS:
 307                 return SI_MAX_VIEWPORTS;
 308         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 309         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 310         case PIPE_CAP_MAX_RENDER_TARGETS:
 311                 return 8;
 312         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 313                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 314
 315         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 316         case PIPE_CAP_MIN_TEXEL_OFFSET:
 317                 return -32;
 318
 319         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 320         case PIPE_CAP_MAX_TEXEL_OFFSET:
 321                 return 31;
 322
 323         case PIPE_CAP_ENDIANNESS:
 324                 return PIPE_ENDIAN_LITTLE;
 325
 326         case PIPE_CAP_VENDOR_ID:
 327                 return ATI_VENDOR_ID;
 328         case PIPE_CAP_DEVICE_ID:
 329                 return sscreen->info.pci_id;
 330         case PIPE_CAP_VIDEO_MEMORY:
 331                 return sscreen->info.vram_size >> 20;
 332         case PIPE_CAP_PCI_GROUP:
 333                 return sscreen->info.pci_domain;
 334         case PIPE_CAP_PCI_BUS:
 335                 return sscreen->info.pci_bus;
 336         case PIPE_CAP_PCI_DEVICE:
 337                 return sscreen->info.pci_dev;
 338         case PIPE_CAP_PCI_FUNCTION:
 339                 return sscreen->info.pci_func;
 340         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 341                 return LLVM_VERSION_MAJOR >= 10;
 342
 343         default:
 344                 return u_pipe_screen_get_param_defaults(pscreen, param);
 345         }
 346 }
 347
 348 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 349 {
 350         switch (param) {
 351         case PIPE_CAPF_MAX_LINE_WIDTH:
 352         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 353                 /* This depends on the quant mode, though the precise interactions
 354                  * are unknown. */
 355                 return 2048;
 356         case PIPE_CAPF_MAX_POINT_WIDTH:
 357         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 358                 return SI_MAX_POINT_SIZE;
 359         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 360                 return 16.0f;
 361         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 362                 return 16.0f;
 363         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 364         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 365         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 366                 return 0.0f;
 367         }
 368         return 0.0f;
 369 }
 370
 371 static int si_get_shader_param(struct pipe_screen* pscreen,
 372                                enum pipe_shader_type shader,
 373                                enum pipe_shader_cap param)
 374 {
 375         struct si_screen *sscreen = (struct si_screen *)pscreen;
 376
 377         switch(shader)
 378         {
 379         case PIPE_SHADER_FRAGMENT:
 380         case PIPE_SHADER_VERTEX:
 381         case PIPE_SHADER_GEOMETRY:
 382         case PIPE_SHADER_TESS_CTRL:
 383         case PIPE_SHADER_TESS_EVAL:
 384                 break;
 385         case PIPE_SHADER_COMPUTE:
 386                 switch (param) {
 387                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 388                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 389
 390                         if (sscreen->info.has_indirect_compute_dispatch)
 391                                 ir |= 1 << PIPE_SHADER_IR_NIR;
 392
 393                         return ir;
 394                 }
 395
 396                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 397                         uint64_t max_const_buffer_size;
 398                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 399                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 400                                 &max_const_buffer_size);
 401                         return MIN2(max_const_buffer_size, INT_MAX);
 402                 }
 403                 default:
 404                         /* If compute shaders don't require a special value
 405                          * for this cap, we can return the same value we
 406                          * do for other shader types. */
 407                         break;
 408                 }
 409                 break;
 410         default:
 411                 return 0;
 412         }
 413
 414         switch (param) {
 415         /* Shader limits. */
 416         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 417         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 418         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 419         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 420         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 421                 return 16384;
 422         case PIPE_SHADER_CAP_MAX_INPUTS:
 423                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 424         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 425                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 426         case PIPE_SHADER_CAP_MAX_TEMPS:
 427                 return 256; /* Max native temporaries. */
 428         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 429                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 430         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 431                 return SI_NUM_CONST_BUFFERS;
 432         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 433         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 434                 return SI_NUM_SAMPLERS;
 435         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 436                 return SI_NUM_SHADER_BUFFERS;
 437         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 438                 return SI_NUM_IMAGES;
 439         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 440                 return 0;
 441         case PIPE_SHADER_CAP_PREFERRED_IR:
 442                 return PIPE_SHADER_IR_NIR;
 443         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 444                 return 4;
 445
 446         /* Supported boolean features. */
 447         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 448         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 449         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 450         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 451         case PIPE_SHADER_CAP_INTEGERS:
 452         case PIPE_SHADER_CAP_INT64_ATOMICS:
 453         case PIPE_SHADER_CAP_FP16:
 454         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 455         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 456         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 457         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 459         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 460                 return 1;
 461
 462         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 463                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 464                 if (shader == PIPE_SHADER_GEOMETRY)
 465                         return 0;
 466
 467                 if (shader == PIPE_SHADER_VERTEX &&
 468                     !sscreen->llvm_has_working_vgpr_indexing)
 469                         return 0;
 470
 471                 /* TCS and TES load inputs directly from LDS or offchip
 472                  * memory, so indirect indexing is always supported.
 473                  * PS has to support indirect indexing, because we can't
 474                  * lower that to TEMPs for INTERP instructions.
 475                  */
 476                 return 1;
 477
 478         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 479                 return sscreen->llvm_has_working_vgpr_indexing ||
 480                        /* TCS stores outputs directly to memory. */
 481                        shader == PIPE_SHADER_TESS_CTRL;
 482
 483         /* Unsupported boolean features. */
 484         case PIPE_SHADER_CAP_SUBROUTINES:
 485         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 486         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 487         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 488                 return 0;
 489         }
 490         return 0;
 491 }
 492
 493 static const struct nir_shader_compiler_options nir_options = {
 494         .lower_scmp = true,
 495         .lower_flrp32 = true,
 496         .lower_flrp64 = true,
 497         .lower_fsat = true,
 498         .lower_fdiv = true,
 499         .lower_bitfield_insert_to_bitfield_select = true,
 500         .lower_bitfield_extract = true,
 501         .lower_sub = true,
 502         .fuse_ffma = true,
 503         .lower_fmod = true,
 504         .lower_pack_snorm_4x8 = true,
 505         .lower_pack_unorm_4x8 = true,
 506         .lower_unpack_snorm_2x16 = true,
 507         .lower_unpack_snorm_4x8 = true,
 508         .lower_unpack_unorm_2x16 = true,
 509         .lower_unpack_unorm_4x8 = true,
 510         .lower_extract_byte = true,
 511         .lower_extract_word = true,
 512         .lower_rotate = true,
 513         .lower_to_scalar = true,
 514         .optimize_sample_mask_in = true,
 515         .max_unroll_iterations = 32,
 516         .use_interpolated_input_intrinsics = true,
 517 };
 518
 519 static const void *
 520 si_get_compiler_options(struct pipe_screen *screen,
 521                         enum pipe_shader_ir ir,
 522                         enum pipe_shader_type shader)
 523 {
 524         assert(ir == PIPE_SHADER_IR_NIR);
 525         return &nir_options;
 526 }
 527
 528 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 529 {
 530         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 531 }
 532
 533 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 534 {
 535         struct si_screen *sscreen = (struct si_screen *)pscreen;
 536
 537         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 538 }
 539
 540 static const char* si_get_name(struct pipe_screen *pscreen)
 541 {
 542         struct si_screen *sscreen = (struct si_screen*)pscreen;
 543
 544         return sscreen->renderer_string;
 545 }
 546
 547 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 548                                         enum pipe_video_profile profile,
 549                                         enum pipe_video_entrypoint entrypoint,
 550                                         enum pipe_video_cap param)
 551 {
 552         switch (param) {
 553         case PIPE_VIDEO_CAP_SUPPORTED:
 554                 return vl_profile_supported(screen, profile, entrypoint);
 555         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 556                 return 1;
 557         case PIPE_VIDEO_CAP_MAX_WIDTH:
 558         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 559                 return vl_video_buffer_max_size(screen);
 560         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 561                 return PIPE_FORMAT_NV12;
 562         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 563                 return false;
 564         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 565                 return false;
 566         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 567                 return true;
 568         case PIPE_VIDEO_CAP_MAX_LEVEL:
 569                 return vl_level_supported(screen, profile);
 570         default:
 571                 return 0;
 572         }
 573 }
 574
 575 static int si_get_video_param(struct pipe_screen *screen,
 576                               enum pipe_video_profile profile,
 577                               enum pipe_video_entrypoint entrypoint,
 578                               enum pipe_video_cap param)
 579 {
 580         struct si_screen *sscreen = (struct si_screen *)screen;
 581         enum pipe_video_format codec = u_reduce_video_profile(profile);
 582
 583         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 584                 switch (param) {
 585                 case PIPE_VIDEO_CAP_SUPPORTED:
 586                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 587                                 (si_vce_is_fw_version_supported(sscreen) ||
 588                                 sscreen->info.family >= CHIP_RAVEN)) ||
 589                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 590                                 (sscreen->info.family >= CHIP_RAVEN ||
 591                                 si_radeon_uvd_enc_supported(sscreen)));
 592                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 593                         return 1;
 594                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 595                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 596                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 597                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 598                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 599                         return PIPE_FORMAT_NV12;
 600                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 601                         return false;
 602                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 603                         return false;
 604                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 605                         return true;
 606                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 607                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 608                 default:
 609                         return 0;
 610                 }
 611         }
 612
 613         switch (param) {
 614         case PIPE_VIDEO_CAP_SUPPORTED:
 615                 switch (codec) {
 616                 case PIPE_VIDEO_FORMAT_MPEG12:
 617                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 618                 case PIPE_VIDEO_FORMAT_MPEG4:
 619                         return 1;
 620                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 621                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 622                              sscreen->info.family == CHIP_POLARIS11) &&
 623                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 624                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 625                                 return false;
 626                         }
 627                         return true;
 628                 case PIPE_VIDEO_FORMAT_VC1:
 629                         return true;
 630                 case PIPE_VIDEO_FORMAT_HEVC:
 631                         /* Carrizo only supports HEVC Main */
 632                         if (sscreen->info.family >= CHIP_STONEY)
 633                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 634                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 635                         else if (sscreen->info.family >= CHIP_CARRIZO)
 636                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 637                         return false;
 638                 case PIPE_VIDEO_FORMAT_JPEG:
 639                         if (sscreen->info.family >= CHIP_RAVEN)
 640                                 return true;
 641                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 642                                 return false;
 643                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 644                                 RVID_ERR("No MJPEG support for the kernel version\n");
 645                                 return false;
 646                         }
 647                         return true;
 648                 case PIPE_VIDEO_FORMAT_VP9:
 649                         if (sscreen->info.family < CHIP_RAVEN)
 650                                 return false;
 651                         return true;
 652                 default:
 653                         return false;
 654                 }
 655         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 656                 return 1;
 657         case PIPE_VIDEO_CAP_MAX_WIDTH:
 658                 switch (codec) {
 659                 case PIPE_VIDEO_FORMAT_HEVC:
 660                 case PIPE_VIDEO_FORMAT_VP9:
 661                         return (sscreen->info.family < CHIP_RENOIR) ?
 662                                ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
 663                                8192;
 664                 default:
 665                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 666                 }
 667         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 668                 switch (codec) {
 669                 case PIPE_VIDEO_FORMAT_HEVC:
 670                 case PIPE_VIDEO_FORMAT_VP9:
 671                         return (sscreen->info.family < CHIP_RENOIR) ?
 672                                ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
 673                                4352;
 674                 default:
 675                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 676                 }
 677         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 678                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 679                         return PIPE_FORMAT_P010;
 680                 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 681                         return PIPE_FORMAT_P016;
 682                 else
 683                         return PIPE_FORMAT_NV12;
 684
 685         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 686         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 687                 enum pipe_video_format format = u_reduce_video_profile(profile);
 688
 689                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 690                         return false; //The firmware doesn't support interlaced HEVC.
 691                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 692                         return false;
 693                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 694                         return false;
 695                 return true;
 696         }
 697         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 698                 return true;
 699         case PIPE_VIDEO_CAP_MAX_LEVEL:
 700                 switch (profile) {
 701                 case PIPE_VIDEO_PROFILE_MPEG1:
 702                         return 0;
 703                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 704                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 705                         return 3;
 706                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 707                         return 3;
 708                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 709                         return 5;
 710                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 711                         return 1;
 712                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 713                         return 2;
 714                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 715                         return 4;
 716                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 717                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 718                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 719                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 720                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 721                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 722                         return 186;
 723                 default:
 724                         return 0;
 725                 }
 726         default:
 727                 return 0;
 728         }
 729 }
 730
 731 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 732                                        enum pipe_format format,
 733                                        enum pipe_video_profile profile,
 734                                        enum pipe_video_entrypoint entrypoint)
 735 {
 736         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 737         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 738                 return (format == PIPE_FORMAT_NV12) ||
 739                         (format == PIPE_FORMAT_P016);
 740
 741         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 742         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 743                 return format == PIPE_FORMAT_P016;
 744
 745
 746         /* we can only handle this one with UVD */
 747         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 748                 return format == PIPE_FORMAT_NV12;
 749
 750         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 751 }
 752
 753 static unsigned get_max_threads_per_block(struct si_screen *screen,
 754                                           enum pipe_shader_ir ir_type)
 755 {
 756         if (ir_type == PIPE_SHADER_IR_NATIVE)
 757                 return 256;
 758
 759         /* LLVM 10 only supports 1024 threads per block. */
 760         return 1024;
 761 }
 762
 763 static int si_get_compute_param(struct pipe_screen *screen,
 764                                 enum pipe_shader_ir ir_type,
 765                                 enum pipe_compute_cap param,
 766                                 void *ret)
 767 {
 768         struct si_screen *sscreen = (struct si_screen *)screen;
 769
 770         //TODO: select these params by asic
 771         switch (param) {
 772         case PIPE_COMPUTE_CAP_IR_TARGET: {
 773                 const char *gpu, *triple;
 774
 775                 triple = "amdgcn-mesa-mesa3d";
 776                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 777                 if (ret) {
 778                         sprintf(ret, "%s-%s", gpu, triple);
 779                 }
 780                 /* +2 for dash and terminating NIL byte */
 781                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 782         }
 783         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 784                 if (ret) {
 785                         uint64_t *grid_dimension = ret;
 786                         grid_dimension[0] = 3;
 787                 }
 788                 return 1 * sizeof(uint64_t);
 789
 790         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 791                 if (ret) {
 792                         uint64_t *grid_size = ret;
 793                         grid_size[0] = 65535;
 794                         grid_size[1] = 65535;
 795                         grid_size[2] = 65535;
 796                 }
 797                 return 3 * sizeof(uint64_t) ;
 798
 799         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 800                 if (ret) {
 801                         uint64_t *block_size = ret;
 802                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 803                         block_size[0] = threads_per_block;
 804                         block_size[1] = threads_per_block;
 805                         block_size[2] = threads_per_block;
 806                 }
 807                 return 3 * sizeof(uint64_t);
 808
 809         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 810                 if (ret) {
 811                         uint64_t *max_threads_per_block = ret;
 812                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 813                 }
 814                 return sizeof(uint64_t);
 815         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 816                 if (ret) {
 817                         uint32_t *address_bits = ret;
 818                         address_bits[0] = 64;
 819                 }
 820                 return 1 * sizeof(uint32_t);
 821
 822         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 823                 if (ret) {
 824                         uint64_t *max_global_size = ret;
 825                         uint64_t max_mem_alloc_size;
 826
 827                         si_get_compute_param(screen, ir_type,
 828                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 829                                 &max_mem_alloc_size);
 830
 831                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 832                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 833                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 834                          * make sure we never report more than
 835                          * 4 * MAX_MEM_ALLOC_SIZE.
 836                          */
 837                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 838                                                 MAX2(sscreen->info.gart_size,
 839                                                      sscreen->info.vram_size));
 840                 }
 841                 return sizeof(uint64_t);
 842
 843         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 844                 if (ret) {
 845                         uint64_t *max_local_size = ret;
 846                         /* Value reported by the closed source driver. */
 847                         *max_local_size = 32768;
 848                 }
 849                 return sizeof(uint64_t);
 850
 851         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 852                 if (ret) {
 853                         uint64_t *max_input_size = ret;
 854                         /* Value reported by the closed source driver. */
 855                         *max_input_size = 1024;
 856                 }
 857                 return sizeof(uint64_t);
 858
 859         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 860                 if (ret) {
 861                         uint64_t *max_mem_alloc_size = ret;
 862
 863                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 864                 }
 865                 return sizeof(uint64_t);
 866
 867         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 868                 if (ret) {
 869                         uint32_t *max_clock_frequency = ret;
 870                         *max_clock_frequency = sscreen->info.max_shader_clock;
 871                 }
 872                 return sizeof(uint32_t);
 873
 874         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 875                 if (ret) {
 876                         uint32_t *max_compute_units = ret;
 877                         *max_compute_units = sscreen->info.num_good_compute_units;
 878                 }
 879                 return sizeof(uint32_t);
 880
 881         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 882                 if (ret) {
 883                         uint32_t *images_supported = ret;
 884                         *images_supported = 0;
 885                 }
 886                 return sizeof(uint32_t);
 887         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 888                 break; /* unused */
 889         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 890                 if (ret) {
 891                         uint32_t *subgroup_size = ret;
 892                         *subgroup_size = sscreen->compute_wave_size;
 893                 }
 894                 return sizeof(uint32_t);
 895         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 896                 if (ret) {
 897                         uint64_t *max_variable_threads_per_block = ret;
 898                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 899                                 *max_variable_threads_per_block = 0;
 900                         else
 901                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 902                 }
 903                 return sizeof(uint64_t);
 904         }
 905
 906         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 907         return 0;
 908 }
 909
 910 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 911 {
 912         struct si_screen *sscreen = (struct si_screen*)screen;
 913
 914         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 915                         sscreen->info.clock_crystal_freq;
 916 }
 917
 918 static void si_query_memory_info(struct pipe_screen *screen,
 919                                  struct pipe_memory_info *info)
 920 {
 921         struct si_screen *sscreen = (struct si_screen*)screen;
 922         struct radeon_winsys *ws = sscreen->ws;
 923         unsigned vram_usage, gtt_usage;
 924
 925         info->total_device_memory = sscreen->info.vram_size / 1024;
 926         info->total_staging_memory = sscreen->info.gart_size / 1024;
 927
 928         /* The real TTM memory usage is somewhat random, because:
 929          *
 930          * 1) TTM delays freeing memory, because it can only free it after
 931          *    fences expire.
 932          *
 933          * 2) The memory usage can be really low if big VRAM evictions are
 934          *    taking place, but the real usage is well above the size of VRAM.
 935          *
 936          * Instead, return statistics of this process.
 937          */
 938         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 939         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 940
 941         info->avail_device_memory =
 942                 vram_usage <= info->total_device_memory ?
 943                                 info->total_device_memory - vram_usage : 0;
 944         info->avail_staging_memory =
 945                 gtt_usage <= info->total_staging_memory ?
 946                                 info->total_staging_memory - gtt_usage : 0;
 947
 948         info->device_memory_evicted =
 949                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 950
 951         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 952                 info->nr_device_memory_evictions =
 953                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 954         else
 955                 /* Just return the number of evicted 64KB pages. */
 956                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 957 }
 958
 959 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 960 {
 961         struct si_screen *sscreen = (struct si_screen*)pscreen;
 962
 963         return sscreen->disk_shader_cache;
 964 }
 965
 966 static void si_init_renderer_string(struct si_screen *sscreen)
 967 {
 968         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 969         struct utsname uname_data;
 970
 971         if (sscreen->info.marketing_name) {
 972                 snprintf(first_name, sizeof(first_name), "%s",
 973                          sscreen->info.marketing_name);
 974                 snprintf(second_name, sizeof(second_name), "%s, ",
 975                          sscreen->info.name);
 976         } else {
 977                 snprintf(first_name, sizeof(first_name), "AMD %s",
 978                          sscreen->info.name);
 979         }
 980
 981         if (uname(&uname_data) == 0)
 982                 snprintf(kernel_version, sizeof(kernel_version),
 983                          ", %s", uname_data.release);
 984
 985         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 986                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 987                  first_name, second_name, sscreen->info.drm_major,
 988                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 989                  kernel_version);
 990 }
 991
 992 void si_init_screen_get_functions(struct si_screen *sscreen)
 993 {
 994         sscreen->b.get_name = si_get_name;
 995         sscreen->b.get_vendor = si_get_vendor;
 996         sscreen->b.get_device_vendor = si_get_device_vendor;
 997         sscreen->b.get_param = si_get_param;
 998         sscreen->b.get_paramf = si_get_paramf;
 999         sscreen->b.get_compute_param = si_get_compute_param;
1000         sscreen->b.get_timestamp = si_get_timestamp;
1001         sscreen->b.get_shader_param = si_get_shader_param;
1002         sscreen->b.get_compiler_options = si_get_compiler_options;
1003         sscreen->b.get_device_uuid = si_get_device_uuid;
1004         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1005         sscreen->b.query_memory_info = si_query_memory_info;
1006         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1007
1008         if (sscreen->info.has_hw_decode) {
1009                 sscreen->b.get_video_param = si_get_video_param;
1010                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1011         } else {
1012                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1013                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1014         }
1015
1016         si_init_renderer_string(sscreen);
1017 }