src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  51 {
  52         if (!ws->get_chip_name)
  53                 return NULL;
  54         return ws->get_chip_name(ws);
  55 }
  56
  57 const char *si_get_family_name(const struct si_screen *sscreen)
  58 {
  59         switch (sscreen->info.family) {
  60         case CHIP_TAHITI: return "AMD TAHITI";
  61         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  62         case CHIP_VERDE: return "AMD CAPE VERDE";
  63         case CHIP_OLAND: return "AMD OLAND";
  64         case CHIP_HAINAN: return "AMD HAINAN";
  65         case CHIP_BONAIRE: return "AMD BONAIRE";
  66         case CHIP_KAVERI: return "AMD KAVERI";
  67         case CHIP_KABINI: return "AMD KABINI";
  68         case CHIP_HAWAII: return "AMD HAWAII";
  69         case CHIP_MULLINS: return "AMD MULLINS";
  70         case CHIP_TONGA: return "AMD TONGA";
  71         case CHIP_ICELAND: return "AMD ICELAND";
  72         case CHIP_CARRIZO: return "AMD CARRIZO";
  73         case CHIP_FIJI: return "AMD FIJI";
  74         case CHIP_STONEY: return "AMD STONEY";
  75         case CHIP_POLARIS10: return "AMD POLARIS10";
  76         case CHIP_POLARIS11: return "AMD POLARIS11";
  77         case CHIP_POLARIS12: return "AMD POLARIS12";
  78         case CHIP_VEGAM: return "AMD VEGAM";
  79         case CHIP_VEGA10: return "AMD VEGA10";
  80         case CHIP_VEGA12: return "AMD VEGA12";
  81         case CHIP_RAVEN: return "AMD RAVEN";
  82         default: return "AMD unknown";
  83         }
  84 }
  85
  86 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  87 {
  88         struct si_screen *sscreen = (struct si_screen *)pscreen;
  89
  90         switch (param) {
  91         /* Supported features (boolean caps). */
  92         case PIPE_CAP_ACCELERATED:
  93         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  94         case PIPE_CAP_ANISOTROPIC_FILTER:
  95         case PIPE_CAP_POINT_SPRITE:
  96         case PIPE_CAP_OCCLUSION_QUERY:
  97         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  99         case PIPE_CAP_TEXTURE_SWIZZLE:
 100         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 101         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 102         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 103         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 104         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 105         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 106         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 107         case PIPE_CAP_SM3:
 108         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109         case PIPE_CAP_PRIMITIVE_RESTART:
 110         case PIPE_CAP_CONDITIONAL_RENDER:
 111         case PIPE_CAP_TEXTURE_BARRIER:
 112         case PIPE_CAP_INDEP_BLEND_ENABLE:
 113         case PIPE_CAP_INDEP_BLEND_FUNC:
 114         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 116         case PIPE_CAP_START_INSTANCE:
 117         case PIPE_CAP_NPOT_TEXTURES:
 118         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 119         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 120         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 121         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 122         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 123         case PIPE_CAP_TGSI_INSTANCEID:
 124         case PIPE_CAP_COMPUTE:
 125         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 126         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 127         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 128         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 129         case PIPE_CAP_CUBE_MAP_ARRAY:
 130         case PIPE_CAP_SAMPLE_SHADING:
 131         case PIPE_CAP_DRAW_INDIRECT:
 132         case PIPE_CAP_CLIP_HALFZ:
 133         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 134         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 135         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 136         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 137         case PIPE_CAP_TGSI_TEXCOORD:
 138         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 139         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 140         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 141         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 142         case PIPE_CAP_SHAREABLE_SHADERS:
 143         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 144         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 145         case PIPE_CAP_TEXTURE_QUERY_LOD:
 146         case PIPE_CAP_TEXTURE_GATHER_SM5:
 147         case PIPE_CAP_TGSI_TXQS:
 148         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 149         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 150         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 151         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 152         case PIPE_CAP_INVALIDATE_BUFFER:
 153         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 154         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 155         case PIPE_CAP_QUERY_MEMORY_INFO:
 156         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 157         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 158         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 159         case PIPE_CAP_GENERATE_MIPMAP:
 160         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 161         case PIPE_CAP_STRING_MARKER:
 162         case PIPE_CAP_CLEAR_TEXTURE:
 163         case PIPE_CAP_CULL_DISTANCE:
 164         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 165         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 166         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 167         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 168         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 169         case PIPE_CAP_DOUBLES:
 170         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 171         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 172         case PIPE_CAP_BINDLESS_TEXTURE:
 173         case PIPE_CAP_QUERY_TIMESTAMP:
 174         case PIPE_CAP_QUERY_TIME_ELAPSED:
 175         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 176         case PIPE_CAP_QUERY_SO_OVERFLOW:
 177         case PIPE_CAP_MEMOBJ:
 178         case PIPE_CAP_LOAD_CONSTBUF:
 179         case PIPE_CAP_INT64:
 180         case PIPE_CAP_INT64_DIVMOD:
 181         case PIPE_CAP_TGSI_CLOCK:
 182         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 183         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 184         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 185         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 186         case PIPE_CAP_TGSI_VOTE:
 187         case PIPE_CAP_TGSI_FS_FBFETCH:
 188                 return 1;
 189
 190         case PIPE_CAP_TGSI_BALLOT:
 191                 return HAVE_LLVM >= 0x0500;
 192
 193         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 194                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 195
 196         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 197                 return sscreen->info.has_gpu_reset_status_query ||
 198                        sscreen->info.has_gpu_reset_counter_query;
 199
 200         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 201                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 202                 return sscreen->info.chip_class < CIK ||
 203                        (sscreen->info.drm_major == 2 &&
 204                         sscreen->info.drm_minor >= 35) ||
 205                        sscreen->info.drm_major == 3;
 206
 207         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 208                 return SI_MAP_BUFFER_ALIGNMENT;
 209
 210         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 211         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 212         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 213         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 214         case PIPE_CAP_MAX_VERTEX_STREAMS:
 215         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 216                 return 4;
 217
 218         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 219                 if (sscreen->info.has_indirect_compute_dispatch)
 220                         return 450;
 221                 return 420;
 222
 223         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 224                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 225
 226         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 227         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 228         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 229                 return !sscreen->info.has_unaligned_shader_loads;
 230
 231         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 232                 /* TODO: GFX9 hangs. */
 233                 if (sscreen->info.chip_class >= GFX9)
 234                         return 0;
 235                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 236                  * faults are mitigated in software.
 237                  */
 238                 if (sscreen->info.chip_class >= CIK &&
 239                     sscreen->info.drm_major == 3 &&
 240                     sscreen->info.drm_minor >= 13)
 241                         return RADEON_SPARSE_PAGE_SIZE;
 242                 return 0;
 243
 244         case PIPE_CAP_PACKED_UNIFORMS:
 245                 if (sscreen->debug_flags & DBG(NIR))
 246                         return 1;
 247                 return 0;
 248
 249         /* Unsupported features. */
 250         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 251         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 252         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 253         case PIPE_CAP_USER_VERTEX_BUFFERS:
 254         case PIPE_CAP_FAKE_SW_MSAA:
 255         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 256         case PIPE_CAP_VERTEXID_NOBASE:
 257         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 258         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 259         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 260         case PIPE_CAP_UMA:
 261         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 262         case PIPE_CAP_POST_DEPTH_COVERAGE:
 263         case PIPE_CAP_TILE_RASTER_ORDER:
 264         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 265         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 266         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 267         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 268         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 269         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 270         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 271         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 272                 return 0;
 273
 274         case PIPE_CAP_FENCE_SIGNAL:
 275                 return sscreen->info.has_syncobj;
 276
 277         case PIPE_CAP_CONSTBUF0_FLAGS:
 278                 return SI_RESOURCE_FLAG_32BIT;
 279
 280         case PIPE_CAP_NATIVE_FENCE_FD:
 281                 return sscreen->info.has_fence_to_handle;
 282
 283         case PIPE_CAP_DRAW_PARAMETERS:
 284         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 285         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 286                 return sscreen->has_draw_indirect_multi;
 287
 288         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 289                 return 30;
 290
 291         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 292                 return sscreen->info.chip_class <= VI ?
 293                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 294
 295         /* Stream output. */
 296         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 297         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 298                 return 32*4;
 299
 300         /* Geometry shader output. */
 301         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 302                 return 1024;
 303         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 304                 return 4095;
 305
 306         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 307                 return 2048;
 308
 309         /* Texturing. */
 310         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 311         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 312                 return 15; /* 16384 */
 313         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 314                 /* textures support 8192, but layered rendering supports 2048 */
 315                 return 12;
 316         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 317                 /* textures support 8192, but layered rendering supports 2048 */
 318                 return 2048;
 319
 320         /* Viewports and render targets. */
 321         case PIPE_CAP_MAX_VIEWPORTS:
 322                 return SI_MAX_VIEWPORTS;
 323         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 324         case PIPE_CAP_MAX_RENDER_TARGETS:
 325                 return 8;
 326
 327         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 328         case PIPE_CAP_MIN_TEXEL_OFFSET:
 329                 return -32;
 330
 331         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 332         case PIPE_CAP_MAX_TEXEL_OFFSET:
 333                 return 31;
 334
 335         case PIPE_CAP_ENDIANNESS:
 336                 return PIPE_ENDIAN_LITTLE;
 337
 338         case PIPE_CAP_VENDOR_ID:
 339                 return ATI_VENDOR_ID;
 340         case PIPE_CAP_DEVICE_ID:
 341                 return sscreen->info.pci_id;
 342         case PIPE_CAP_VIDEO_MEMORY:
 343                 return sscreen->info.vram_size >> 20;
 344         case PIPE_CAP_PCI_GROUP:
 345                 return sscreen->info.pci_domain;
 346         case PIPE_CAP_PCI_BUS:
 347                 return sscreen->info.pci_bus;
 348         case PIPE_CAP_PCI_DEVICE:
 349                 return sscreen->info.pci_dev;
 350         case PIPE_CAP_PCI_FUNCTION:
 351                 return sscreen->info.pci_func;
 352         }
 353         return 0;
 354 }
 355
 356 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 357 {
 358         switch (param) {
 359         case PIPE_CAPF_MAX_LINE_WIDTH:
 360         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 361         case PIPE_CAPF_MAX_POINT_WIDTH:
 362         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 363                 return 8192.0f;
 364         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 365                 return 16.0f;
 366         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 367                 return 16.0f;
 368         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 369         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 370         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 371                 return 0.0f;
 372         }
 373         return 0.0f;
 374 }
 375
 376 static int si_get_shader_param(struct pipe_screen* pscreen,
 377                                enum pipe_shader_type shader,
 378                                enum pipe_shader_cap param)
 379 {
 380         struct si_screen *sscreen = (struct si_screen *)pscreen;
 381
 382         switch(shader)
 383         {
 384         case PIPE_SHADER_FRAGMENT:
 385         case PIPE_SHADER_VERTEX:
 386         case PIPE_SHADER_GEOMETRY:
 387         case PIPE_SHADER_TESS_CTRL:
 388         case PIPE_SHADER_TESS_EVAL:
 389                 break;
 390         case PIPE_SHADER_COMPUTE:
 391                 switch (param) {
 392                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 393                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 394
 395                         if (sscreen->info.has_indirect_compute_dispatch)
 396                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 397
 398                         return ir;
 399                 }
 400
 401                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 402                         uint64_t max_const_buffer_size;
 403                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 404                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 405                                 &max_const_buffer_size);
 406                         return MIN2(max_const_buffer_size, INT_MAX);
 407                 }
 408                 default:
 409                         /* If compute shaders don't require a special value
 410                          * for this cap, we can return the same value we
 411                          * do for other shader types. */
 412                         break;
 413                 }
 414                 break;
 415         default:
 416                 return 0;
 417         }
 418
 419         switch (param) {
 420         /* Shader limits. */
 421         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 422         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 423         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 424         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 425         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 426                 return 16384;
 427         case PIPE_SHADER_CAP_MAX_INPUTS:
 428                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 429         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 430                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 431         case PIPE_SHADER_CAP_MAX_TEMPS:
 432                 return 256; /* Max native temporaries. */
 433         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 434                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 435         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 436                 return SI_NUM_CONST_BUFFERS;
 437         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 438         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 439                 return SI_NUM_SAMPLERS;
 440         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 441                 return SI_NUM_SHADER_BUFFERS;
 442         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 443                 return SI_NUM_IMAGES;
 444         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 445                 if (sscreen->debug_flags & DBG(NIR))
 446                         return 0;
 447                 return 32;
 448         case PIPE_SHADER_CAP_PREFERRED_IR:
 449                 if (sscreen->debug_flags & DBG(NIR))
 450                         return PIPE_SHADER_IR_NIR;
 451                 return PIPE_SHADER_IR_TGSI;
 452         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 453                 return 4;
 454
 455         /* Supported boolean features. */
 456         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 457         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 458         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 459         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 460         case PIPE_SHADER_CAP_INTEGERS:
 461         case PIPE_SHADER_CAP_INT64_ATOMICS:
 462         case PIPE_SHADER_CAP_FP16:
 463         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 464         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 465         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 466         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 467         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 468         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 469                 return 1;
 470
 471         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 472                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 473                 if (shader == PIPE_SHADER_GEOMETRY)
 474                         return 0;
 475
 476                 if (shader == PIPE_SHADER_VERTEX &&
 477                     !sscreen->llvm_has_working_vgpr_indexing)
 478                         return 0;
 479
 480                 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
 481                  * This means we don't support INTERP instructions with
 482                  * indirect indexing on inputs.
 483                  */
 484                 if (shader == PIPE_SHADER_FRAGMENT &&
 485                     !sscreen->llvm_has_working_vgpr_indexing &&
 486                     HAVE_LLVM < 0x0700)
 487                         return 0;
 488
 489                 /* TCS and TES load inputs directly from LDS or offchip
 490                  * memory, so indirect indexing is always supported.
 491                  * PS has to support indirect indexing, because we can't
 492                  * lower that to TEMPs for INTERP instructions.
 493                  */
 494                 return 1;
 495
 496         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 497                 return sscreen->llvm_has_working_vgpr_indexing ||
 498                        /* TCS stores outputs directly to memory. */
 499                        shader == PIPE_SHADER_TESS_CTRL;
 500
 501         /* Unsupported boolean features. */
 502         case PIPE_SHADER_CAP_SUBROUTINES:
 503         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 504         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 505         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 506                 return 0;
 507         }
 508         return 0;
 509 }
 510
 511 static const struct nir_shader_compiler_options nir_options = {
 512         .lower_scmp = true,
 513         .lower_flrp32 = true,
 514         .lower_flrp64 = true,
 515         .lower_fpow = true,
 516         .lower_fsat = true,
 517         .lower_fdiv = true,
 518         .lower_sub = true,
 519         .lower_ffma = true,
 520         .lower_pack_snorm_2x16 = true,
 521         .lower_pack_snorm_4x8 = true,
 522         .lower_pack_unorm_2x16 = true,
 523         .lower_pack_unorm_4x8 = true,
 524         .lower_unpack_snorm_2x16 = true,
 525         .lower_unpack_snorm_4x8 = true,
 526         .lower_unpack_unorm_2x16 = true,
 527         .lower_unpack_unorm_4x8 = true,
 528         .lower_extract_byte = true,
 529         .lower_extract_word = true,
 530         .max_unroll_iterations = 32,
 531         .native_integers = true,
 532 };
 533
 534 static const void *
 535 si_get_compiler_options(struct pipe_screen *screen,
 536                         enum pipe_shader_ir ir,
 537                         enum pipe_shader_type shader)
 538 {
 539         assert(ir == PIPE_SHADER_IR_NIR);
 540         return &nir_options;
 541 }
 542
 543 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 544 {
 545         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 546 }
 547
 548 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 549 {
 550         struct si_screen *sscreen = (struct si_screen *)pscreen;
 551
 552         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 553 }
 554
 555 static const char* si_get_name(struct pipe_screen *pscreen)
 556 {
 557         struct si_screen *sscreen = (struct si_screen*)pscreen;
 558
 559         return sscreen->renderer_string;
 560 }
 561
 562 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 563                                         enum pipe_video_profile profile,
 564                                         enum pipe_video_entrypoint entrypoint,
 565                                         enum pipe_video_cap param)
 566 {
 567         switch (param) {
 568         case PIPE_VIDEO_CAP_SUPPORTED:
 569                 return vl_profile_supported(screen, profile, entrypoint);
 570         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 571                 return 1;
 572         case PIPE_VIDEO_CAP_MAX_WIDTH:
 573         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 574                 return vl_video_buffer_max_size(screen);
 575         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 576                 return PIPE_FORMAT_NV12;
 577         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 578                 return false;
 579         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 580                 return false;
 581         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 582                 return true;
 583         case PIPE_VIDEO_CAP_MAX_LEVEL:
 584                 return vl_level_supported(screen, profile);
 585         default:
 586                 return 0;
 587         }
 588 }
 589
 590 static int si_get_video_param(struct pipe_screen *screen,
 591                               enum pipe_video_profile profile,
 592                               enum pipe_video_entrypoint entrypoint,
 593                               enum pipe_video_cap param)
 594 {
 595         struct si_screen *sscreen = (struct si_screen *)screen;
 596         enum pipe_video_format codec = u_reduce_video_profile(profile);
 597
 598         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 599                 switch (param) {
 600                 case PIPE_VIDEO_CAP_SUPPORTED:
 601                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 602                                 (si_vce_is_fw_version_supported(sscreen) ||
 603                                 sscreen->info.family == CHIP_RAVEN)) ||
 604                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 605                                 (sscreen->info.family == CHIP_RAVEN ||
 606                                 si_radeon_uvd_enc_supported(sscreen)));
 607                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 608                         return 1;
 609                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 610                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 611                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 612                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 613                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 614                         return PIPE_FORMAT_NV12;
 615                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 616                         return false;
 617                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 618                         return false;
 619                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 620                         return true;
 621                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 622                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 623                 default:
 624                         return 0;
 625                 }
 626         }
 627
 628         switch (param) {
 629         case PIPE_VIDEO_CAP_SUPPORTED:
 630                 switch (codec) {
 631                 case PIPE_VIDEO_FORMAT_MPEG12:
 632                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 633                 case PIPE_VIDEO_FORMAT_MPEG4:
 634                         return 1;
 635                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 636                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 637                              sscreen->info.family == CHIP_POLARIS11) &&
 638                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 639                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 640                                 return false;
 641                         }
 642                         return true;
 643                 case PIPE_VIDEO_FORMAT_VC1:
 644                         return true;
 645                 case PIPE_VIDEO_FORMAT_HEVC:
 646                         /* Carrizo only supports HEVC Main */
 647                         if (sscreen->info.family >= CHIP_STONEY)
 648                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 649                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 650                         else if (sscreen->info.family >= CHIP_CARRIZO)
 651                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 652                         return false;
 653                 case PIPE_VIDEO_FORMAT_JPEG:
 654                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 655                                 return false;
 656                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 657                                 RVID_ERR("No MJPEG support for the kernel version\n");
 658                                 return false;
 659                         }
 660                         return true;
 661                 case PIPE_VIDEO_FORMAT_VP9:
 662                         if (sscreen->info.family < CHIP_RAVEN)
 663                                 return false;
 664                         return true;
 665                 default:
 666                         return false;
 667                 }
 668         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 669                 return 1;
 670         case PIPE_VIDEO_CAP_MAX_WIDTH:
 671                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 672         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 673                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 674         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 675                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 676                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 677                         return PIPE_FORMAT_P016;
 678                 else
 679                         return PIPE_FORMAT_NV12;
 680
 681         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 682         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 683                 enum pipe_video_format format = u_reduce_video_profile(profile);
 684
 685                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 686                         return false; //The firmware doesn't support interlaced HEVC.
 687                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 688                         return false;
 689                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 690                         return false;
 691                 return true;
 692         }
 693         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 694                 return true;
 695         case PIPE_VIDEO_CAP_MAX_LEVEL:
 696                 switch (profile) {
 697                 case PIPE_VIDEO_PROFILE_MPEG1:
 698                         return 0;
 699                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 700                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 701                         return 3;
 702                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 703                         return 3;
 704                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 705                         return 5;
 706                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 707                         return 1;
 708                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 709                         return 2;
 710                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 711                         return 4;
 712                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 713                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 714                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 715                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 716                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 717                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 718                         return 186;
 719                 default:
 720                         return 0;
 721                 }
 722         default:
 723                 return 0;
 724         }
 725 }
 726
 727 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 728                                           enum pipe_format format,
 729                                           enum pipe_video_profile profile,
 730                                           enum pipe_video_entrypoint entrypoint)
 731 {
 732         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 733         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 734                 return (format == PIPE_FORMAT_NV12) ||
 735                         (format == PIPE_FORMAT_P016);
 736
 737         /* we can only handle this one with UVD */
 738         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 739                 return format == PIPE_FORMAT_NV12;
 740
 741         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 742 }
 743
 744 static unsigned get_max_threads_per_block(struct si_screen *screen,
 745                                           enum pipe_shader_ir ir_type)
 746 {
 747         if (ir_type == PIPE_SHADER_IR_NATIVE)
 748                 return 256;
 749
 750         /* Only 16 waves per thread-group on gfx9. */
 751         if (screen->info.chip_class >= GFX9)
 752                 return 1024;
 753
 754         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 755          * round number.
 756          */
 757         return 2048;
 758 }
 759
 760 static int si_get_compute_param(struct pipe_screen *screen,
 761                                 enum pipe_shader_ir ir_type,
 762                                 enum pipe_compute_cap param,
 763                                 void *ret)
 764 {
 765         struct si_screen *sscreen = (struct si_screen *)screen;
 766
 767         //TODO: select these params by asic
 768         switch (param) {
 769         case PIPE_COMPUTE_CAP_IR_TARGET: {
 770                 const char *gpu, *triple;
 771
 772                 triple = "amdgcn-mesa-mesa3d";
 773                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 774                 if (ret) {
 775                         sprintf(ret, "%s-%s", gpu, triple);
 776                 }
 777                 /* +2 for dash and terminating NIL byte */
 778                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 779         }
 780         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 781                 if (ret) {
 782                         uint64_t *grid_dimension = ret;
 783                         grid_dimension[0] = 3;
 784                 }
 785                 return 1 * sizeof(uint64_t);
 786
 787         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 788                 if (ret) {
 789                         uint64_t *grid_size = ret;
 790                         grid_size[0] = 65535;
 791                         grid_size[1] = 65535;
 792                         grid_size[2] = 65535;
 793                 }
 794                 return 3 * sizeof(uint64_t) ;
 795
 796         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 797                 if (ret) {
 798                         uint64_t *block_size = ret;
 799                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 800                         block_size[0] = threads_per_block;
 801                         block_size[1] = threads_per_block;
 802                         block_size[2] = threads_per_block;
 803                 }
 804                 return 3 * sizeof(uint64_t);
 805
 806         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 807                 if (ret) {
 808                         uint64_t *max_threads_per_block = ret;
 809                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 810                 }
 811                 return sizeof(uint64_t);
 812         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 813                 if (ret) {
 814                         uint32_t *address_bits = ret;
 815                         address_bits[0] = 64;
 816                 }
 817                 return 1 * sizeof(uint32_t);
 818
 819         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 820                 if (ret) {
 821                         uint64_t *max_global_size = ret;
 822                         uint64_t max_mem_alloc_size;
 823
 824                         si_get_compute_param(screen, ir_type,
 825                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 826                                 &max_mem_alloc_size);
 827
 828                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 829                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 830                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 831                          * make sure we never report more than
 832                          * 4 * MAX_MEM_ALLOC_SIZE.
 833                          */
 834                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 835                                                 MAX2(sscreen->info.gart_size,
 836                                                      sscreen->info.vram_size));
 837                 }
 838                 return sizeof(uint64_t);
 839
 840         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 841                 if (ret) {
 842                         uint64_t *max_local_size = ret;
 843                         /* Value reported by the closed source driver. */
 844                         *max_local_size = 32768;
 845                 }
 846                 return sizeof(uint64_t);
 847
 848         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 849                 if (ret) {
 850                         uint64_t *max_input_size = ret;
 851                         /* Value reported by the closed source driver. */
 852                         *max_input_size = 1024;
 853                 }
 854                 return sizeof(uint64_t);
 855
 856         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 857                 if (ret) {
 858                         uint64_t *max_mem_alloc_size = ret;
 859
 860                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 861                 }
 862                 return sizeof(uint64_t);
 863
 864         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 865                 if (ret) {
 866                         uint32_t *max_clock_frequency = ret;
 867                         *max_clock_frequency = sscreen->info.max_shader_clock;
 868                 }
 869                 return sizeof(uint32_t);
 870
 871         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 872                 if (ret) {
 873                         uint32_t *max_compute_units = ret;
 874                         *max_compute_units = sscreen->info.num_good_compute_units;
 875                 }
 876                 return sizeof(uint32_t);
 877
 878         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 879                 if (ret) {
 880                         uint32_t *images_supported = ret;
 881                         *images_supported = 0;
 882                 }
 883                 return sizeof(uint32_t);
 884         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 885                 break; /* unused */
 886         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 887                 if (ret) {
 888                         uint32_t *subgroup_size = ret;
 889                         *subgroup_size = 64;
 890                 }
 891                 return sizeof(uint32_t);
 892         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 893                 if (ret) {
 894                         uint64_t *max_variable_threads_per_block = ret;
 895                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 896                                 *max_variable_threads_per_block = 0;
 897                         else
 898                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 899                 }
 900                 return sizeof(uint64_t);
 901         }
 902
 903         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 904         return 0;
 905 }
 906
 907 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 908 {
 909         struct si_screen *sscreen = (struct si_screen*)screen;
 910
 911         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 912                         sscreen->info.clock_crystal_freq;
 913 }
 914
 915 static void si_query_memory_info(struct pipe_screen *screen,
 916                                  struct pipe_memory_info *info)
 917 {
 918         struct si_screen *sscreen = (struct si_screen*)screen;
 919         struct radeon_winsys *ws = sscreen->ws;
 920         unsigned vram_usage, gtt_usage;
 921
 922         info->total_device_memory = sscreen->info.vram_size / 1024;
 923         info->total_staging_memory = sscreen->info.gart_size / 1024;
 924
 925         /* The real TTM memory usage is somewhat random, because:
 926          *
 927          * 1) TTM delays freeing memory, because it can only free it after
 928          *    fences expire.
 929          *
 930          * 2) The memory usage can be really low if big VRAM evictions are
 931          *    taking place, but the real usage is well above the size of VRAM.
 932          *
 933          * Instead, return statistics of this process.
 934          */
 935         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 936         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 937
 938         info->avail_device_memory =
 939                 vram_usage <= info->total_device_memory ?
 940                                 info->total_device_memory - vram_usage : 0;
 941         info->avail_staging_memory =
 942                 gtt_usage <= info->total_staging_memory ?
 943                                 info->total_staging_memory - gtt_usage : 0;
 944
 945         info->device_memory_evicted =
 946                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 947
 948         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 949                 info->nr_device_memory_evictions =
 950                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 951         else
 952                 /* Just return the number of evicted 64KB pages. */
 953                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 954 }
 955
 956 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 957 {
 958         struct si_screen *sscreen = (struct si_screen*)pscreen;
 959
 960         return sscreen->disk_shader_cache;
 961 }
 962
 963 static void si_init_renderer_string(struct si_screen *sscreen)
 964 {
 965         struct radeon_winsys *ws = sscreen->ws;
 966         char family_name[32] = {}, kernel_version[128] = {};
 967         struct utsname uname_data;
 968
 969         const char *chip_name = si_get_marketing_name(ws);
 970
 971         if (chip_name)
 972                 snprintf(family_name, sizeof(family_name), "%s, ",
 973                          si_get_family_name(sscreen) + 4);
 974         else
 975                 chip_name = si_get_family_name(sscreen);
 976
 977         if (uname(&uname_data) == 0)
 978                 snprintf(kernel_version, sizeof(kernel_version),
 979                          ", %s", uname_data.release);
 980
 981         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 982                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 983                  chip_name, family_name, sscreen->info.drm_major,
 984                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 985                  kernel_version,
 986                  (HAVE_LLVM >> 8) & 0xff,
 987                  HAVE_LLVM & 0xff,
 988                  MESA_LLVM_VERSION_PATCH);
 989 }
 990
 991 void si_init_screen_get_functions(struct si_screen *sscreen)
 992 {
 993         sscreen->b.get_name = si_get_name;
 994         sscreen->b.get_vendor = si_get_vendor;
 995         sscreen->b.get_device_vendor = si_get_device_vendor;
 996         sscreen->b.get_param = si_get_param;
 997         sscreen->b.get_paramf = si_get_paramf;
 998         sscreen->b.get_compute_param = si_get_compute_param;
 999         sscreen->b.get_timestamp = si_get_timestamp;
1000         sscreen->b.get_shader_param = si_get_shader_param;
1001         sscreen->b.get_compiler_options = si_get_compiler_options;
1002         sscreen->b.get_device_uuid = si_get_device_uuid;
1003         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1004         sscreen->b.query_memory_info = si_query_memory_info;
1005         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1006
1007         if (sscreen->info.has_hw_decode) {
1008                 sscreen->b.get_video_param = si_get_video_param;
1009                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1010         } else {
1011                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1012                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1013         }
1014
1015         si_init_renderer_string(sscreen);
1016 }