projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
[mesa.git] / src / gallium / drivers / radeonsi / si_get.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_screen.h"
33 #include "util/u_video.h"
34 #include "compiler/nir/nir.h"
35
36 #include <sys/utsname.h>
37
38 static const char *si_get_vendor(struct pipe_screen *pscreen)
39 {
40 /* Don't change this. Games such as Alien Isolation are broken if this
41 * returns "Advanced Micro Devices, Inc."
42 */
43 return "X.Org";
44 }
45
46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
47 {
48 return "AMD";
49 }
50
51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
52 {
53 if (!ws->get_chip_name)
54 return NULL;
55 return ws->get_chip_name(ws);
56 }
57
58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
59 {
60 struct si_screen *sscreen = (struct si_screen *)pscreen;
61
62 switch (param) {
63 /* Supported features (boolean caps). */
64 case PIPE_CAP_ACCELERATED:
65 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
66 case PIPE_CAP_ANISOTROPIC_FILTER:
67 case PIPE_CAP_POINT_SPRITE:
68 case PIPE_CAP_OCCLUSION_QUERY:
69 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
70 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
71 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
72 case PIPE_CAP_TEXTURE_SWIZZLE:
73 case PIPE_CAP_DEPTH_CLIP_DISABLE:
74 case PIPE_CAP_SHADER_STENCIL_EXPORT:
75 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
76 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
77 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
78 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
79 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
80 case PIPE_CAP_SM3:
81 case PIPE_CAP_SEAMLESS_CUBE_MAP:
82 case PIPE_CAP_PRIMITIVE_RESTART:
83 case PIPE_CAP_CONDITIONAL_RENDER:
84 case PIPE_CAP_TEXTURE_BARRIER:
85 case PIPE_CAP_INDEP_BLEND_ENABLE:
86 case PIPE_CAP_INDEP_BLEND_FUNC:
87 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
88 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
89 case PIPE_CAP_START_INSTANCE:
90 case PIPE_CAP_NPOT_TEXTURES:
91 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
92 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
93 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
94 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
95 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
96 case PIPE_CAP_TGSI_INSTANCEID:
97 case PIPE_CAP_COMPUTE:
98 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
99 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
100 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
101 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
102 case PIPE_CAP_CUBE_MAP_ARRAY:
103 case PIPE_CAP_SAMPLE_SHADING:
104 case PIPE_CAP_DRAW_INDIRECT:
105 case PIPE_CAP_CLIP_HALFZ:
106 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
107 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
108 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
109 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
110 case PIPE_CAP_TGSI_TEXCOORD:
111 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
112 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
113 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
114 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
115 case PIPE_CAP_SHAREABLE_SHADERS:
116 case PIPE_CAP_DEPTH_BOUNDS_TEST:
117 case PIPE_CAP_SAMPLER_VIEW_TARGET:
118 case PIPE_CAP_TEXTURE_QUERY_LOD:
119 case PIPE_CAP_TEXTURE_GATHER_SM5:
120 case PIPE_CAP_TGSI_TXQS:
121 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
122 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
123 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
124 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
125 case PIPE_CAP_INVALIDATE_BUFFER:
126 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
127 case PIPE_CAP_QUERY_BUFFER_OBJECT:
128 case PIPE_CAP_QUERY_MEMORY_INFO:
129 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
130 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
131 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
132 case PIPE_CAP_GENERATE_MIPMAP:
133 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
134 case PIPE_CAP_STRING_MARKER:
135 case PIPE_CAP_CLEAR_TEXTURE:
136 case PIPE_CAP_CULL_DISTANCE:
137 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
138 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
139 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
140 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
141 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
142 case PIPE_CAP_DOUBLES:
143 case PIPE_CAP_TGSI_TEX_TXF_LZ:
144 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
145 case PIPE_CAP_BINDLESS_TEXTURE:
146 case PIPE_CAP_QUERY_TIMESTAMP:
147 case PIPE_CAP_QUERY_TIME_ELAPSED:
148 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
149 case PIPE_CAP_QUERY_SO_OVERFLOW:
150 case PIPE_CAP_MEMOBJ:
151 case PIPE_CAP_LOAD_CONSTBUF:
152 case PIPE_CAP_INT64:
153 case PIPE_CAP_INT64_DIVMOD:
154 case PIPE_CAP_TGSI_CLOCK:
155 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
156 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
157 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
158 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
159 case PIPE_CAP_TGSI_BALLOT:
160 case PIPE_CAP_TGSI_VOTE:
161 case PIPE_CAP_TGSI_FS_FBFETCH:
162 return 1;
163
164 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
165 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
166
167 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
168 return sscreen->info.has_gpu_reset_status_query ||
169 sscreen->info.has_gpu_reset_counter_query;
170
171 case PIPE_CAP_TEXTURE_MULTISAMPLE:
172 return sscreen->info.has_2d_tiling;
173
174 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
175 return SI_MAP_BUFFER_ALIGNMENT;
176
177 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
178 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
179 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
180 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
181 case PIPE_CAP_MAX_VERTEX_STREAMS:
182 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
183 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
184 return 4;
185
186 case PIPE_CAP_GLSL_FEATURE_LEVEL:
187 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
188 if (sscreen->info.has_indirect_compute_dispatch)
189 return 450;
190 return 420;
191
192 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
193 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
194 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
195
196 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
197 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
198 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
199 return !sscreen->info.has_unaligned_shader_loads;
200
201 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
202 return sscreen->info.has_sparse_vm_mappings ?
203 RADEON_SPARSE_PAGE_SIZE : 0;
204
205 case PIPE_CAP_PACKED_UNIFORMS:
206 if (sscreen->debug_flags & DBG(NIR))
207 return 1;
208 return 0;
209
210 /* Unsupported features. */
211 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
212 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
213 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
214 case PIPE_CAP_USER_VERTEX_BUFFERS:
215 case PIPE_CAP_FAKE_SW_MSAA:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
217 case PIPE_CAP_VERTEXID_NOBASE:
218 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
219 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
220 case PIPE_CAP_UMA:
221 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
222 case PIPE_CAP_POST_DEPTH_COVERAGE:
223 case PIPE_CAP_TILE_RASTER_ORDER:
224 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
225 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
226 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
227 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
228 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
229 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
230 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
231 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
232 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
233 return 0;
234
235 case PIPE_CAP_FENCE_SIGNAL:
236 return sscreen->info.has_syncobj;
237
238 case PIPE_CAP_CONSTBUF0_FLAGS:
239 return SI_RESOURCE_FLAG_32BIT;
240
241 case PIPE_CAP_NATIVE_FENCE_FD:
242 return sscreen->info.has_fence_to_handle;
243
244 case PIPE_CAP_DRAW_PARAMETERS:
245 case PIPE_CAP_MULTI_DRAW_INDIRECT:
246 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
247 return sscreen->has_draw_indirect_multi;
248
249 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
250 return 30;
251
252 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
253 return sscreen->info.chip_class <= VI ?
254 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
255
256 /* Stream output. */
257 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
258 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
259 return 32*4;
260
261 /* Geometry shader output. */
262 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
263 return 1024;
264 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
265 return 4095;
266 case PIPE_CAP_MAX_GS_INVOCATIONS:
267 /* The closed driver exposes 127, but 125 is the greatest
268 * number that works. */
269 return 125;
270
271 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
272 return 2048;
273
274 /* Texturing. */
275 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
276 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
277 return 15; /* 16384 */
278 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
279 /* textures support 8192, but layered rendering supports 2048 */
280 return 12;
281 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
282 /* textures support 8192, but layered rendering supports 2048 */
283 return 2048;
284
285 /* Viewports and render targets. */
286 case PIPE_CAP_MAX_VIEWPORTS:
287 return SI_MAX_VIEWPORTS;
288 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
289 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
290 case PIPE_CAP_MAX_RENDER_TARGETS:
291 return 8;
292 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
293 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
294
295 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
296 case PIPE_CAP_MIN_TEXEL_OFFSET:
297 return -32;
298
299 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
300 case PIPE_CAP_MAX_TEXEL_OFFSET:
301 return 31;
302
303 case PIPE_CAP_ENDIANNESS:
304 return PIPE_ENDIAN_LITTLE;
305
306 case PIPE_CAP_VENDOR_ID:
307 return ATI_VENDOR_ID;
308 case PIPE_CAP_DEVICE_ID:
309 return sscreen->info.pci_id;
310 case PIPE_CAP_VIDEO_MEMORY:
311 return sscreen->info.vram_size >> 20;
312 case PIPE_CAP_PCI_GROUP:
313 return sscreen->info.pci_domain;
314 case PIPE_CAP_PCI_BUS:
315 return sscreen->info.pci_bus;
316 case PIPE_CAP_PCI_DEVICE:
317 return sscreen->info.pci_dev;
318 case PIPE_CAP_PCI_FUNCTION:
319 return sscreen->info.pci_func;
320
321 default:
322 return u_pipe_screen_get_param_defaults(pscreen, param);
323 }
324 }
325
326 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
327 {
328 switch (param) {
329 case PIPE_CAPF_MAX_LINE_WIDTH:
330 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
331 case PIPE_CAPF_MAX_POINT_WIDTH:
332 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
333 return 8192.0f;
334 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
335 return 16.0f;
336 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
337 return 16.0f;
338 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
339 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
340 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
341 return 0.0f;
342 }
343 return 0.0f;
344 }
345
346 static int si_get_shader_param(struct pipe_screen* pscreen,
347 enum pipe_shader_type shader,
348 enum pipe_shader_cap param)
349 {
350 struct si_screen *sscreen = (struct si_screen *)pscreen;
351
352 switch(shader)
353 {
354 case PIPE_SHADER_FRAGMENT:
355 case PIPE_SHADER_VERTEX:
356 case PIPE_SHADER_GEOMETRY:
357 case PIPE_SHADER_TESS_CTRL:
358 case PIPE_SHADER_TESS_EVAL:
359 break;
360 case PIPE_SHADER_COMPUTE:
361 switch (param) {
362 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
363 int ir = 1 << PIPE_SHADER_IR_NATIVE;
364
365 if (sscreen->info.has_indirect_compute_dispatch)
366 ir |= 1 << PIPE_SHADER_IR_TGSI;
367
368 return ir;
369 }
370
371 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
372 uint64_t max_const_buffer_size;
373 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
374 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
375 &max_const_buffer_size);
376 return MIN2(max_const_buffer_size, INT_MAX);
377 }
378 default:
379 /* If compute shaders don't require a special value
380 * for this cap, we can return the same value we
381 * do for other shader types. */
382 break;
383 }
384 break;
385 default:
386 return 0;
387 }
388
389 switch (param) {
390 /* Shader limits. */
391 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
392 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
393 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
394 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
395 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
396 return 16384;
397 case PIPE_SHADER_CAP_MAX_INPUTS:
398 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
399 case PIPE_SHADER_CAP_MAX_OUTPUTS:
400 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
401 case PIPE_SHADER_CAP_MAX_TEMPS:
402 return 256; /* Max native temporaries. */
403 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
404 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
405 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
406 return SI_NUM_CONST_BUFFERS;
407 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
408 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
409 return SI_NUM_SAMPLERS;
410 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
411 return SI_NUM_SHADER_BUFFERS;
412 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
413 return SI_NUM_IMAGES;
414 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
415 if (sscreen->debug_flags & DBG(NIR))
416 return 0;
417 return 32;
418 case PIPE_SHADER_CAP_PREFERRED_IR:
419 if (sscreen->debug_flags & DBG(NIR))
420 return PIPE_SHADER_IR_NIR;
421 return PIPE_SHADER_IR_TGSI;
422 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
423 return 4;
424
425 /* Supported boolean features. */
426 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
427 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
428 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
429 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
430 case PIPE_SHADER_CAP_INTEGERS:
431 case PIPE_SHADER_CAP_INT64_ATOMICS:
432 case PIPE_SHADER_CAP_FP16:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
434 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
435 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
436 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
437 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
438 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
439 return 1;
440
441 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
442 /* TODO: Indirect indexing of GS inputs is unimplemented. */
443 if (shader == PIPE_SHADER_GEOMETRY)
444 return 0;
445
446 if (shader == PIPE_SHADER_VERTEX &&
447 !sscreen->llvm_has_working_vgpr_indexing)
448 return 0;
449
450 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
451 * This means we don't support INTERP instructions with
452 * indirect indexing on inputs.
453 */
454 if (shader == PIPE_SHADER_FRAGMENT &&
455 !sscreen->llvm_has_working_vgpr_indexing &&
456 HAVE_LLVM < 0x0700)
457 return 0;
458
459 /* TCS and TES load inputs directly from LDS or offchip
460 * memory, so indirect indexing is always supported.
461 * PS has to support indirect indexing, because we can't
462 * lower that to TEMPs for INTERP instructions.
463 */
464 return 1;
465
466 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
467 return sscreen->llvm_has_working_vgpr_indexing ||
468 /* TCS stores outputs directly to memory. */
469 shader == PIPE_SHADER_TESS_CTRL;
470
471 /* Unsupported boolean features. */
472 case PIPE_SHADER_CAP_SUBROUTINES:
473 case PIPE_SHADER_CAP_SUPPORTED_IRS:
474 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
475 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
476 return 0;
477 case PIPE_SHADER_CAP_SCALAR_ISA:
478 return 1;
479 }
480 return 0;
481 }
482
483 static const struct nir_shader_compiler_options nir_options = {
484 .lower_scmp = true,
485 .lower_flrp32 = true,
486 .lower_flrp64 = true,
487 .lower_fpow = true,
488 .lower_fsat = true,
489 .lower_fdiv = true,
490 .lower_sub = true,
491 .lower_ffma = true,
492 .lower_pack_snorm_2x16 = true,
493 .lower_pack_snorm_4x8 = true,
494 .lower_pack_unorm_2x16 = true,
495 .lower_pack_unorm_4x8 = true,
496 .lower_unpack_snorm_2x16 = true,
497 .lower_unpack_snorm_4x8 = true,
498 .lower_unpack_unorm_2x16 = true,
499 .lower_unpack_unorm_4x8 = true,
500 .lower_extract_byte = true,
501 .lower_extract_word = true,
502 .max_unroll_iterations = 32,
503 .native_integers = true,
504 };
505
506 static const void *
507 si_get_compiler_options(struct pipe_screen *screen,
508 enum pipe_shader_ir ir,
509 enum pipe_shader_type shader)
510 {
511 assert(ir == PIPE_SHADER_IR_NIR);
512 return &nir_options;
513 }
514
515 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
516 {
517 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
518 }
519
520 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
521 {
522 struct si_screen *sscreen = (struct si_screen *)pscreen;
523
524 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
525 }
526
527 static const char* si_get_name(struct pipe_screen *pscreen)
528 {
529 struct si_screen *sscreen = (struct si_screen*)pscreen;
530
531 return sscreen->renderer_string;
532 }
533
534 static int si_get_video_param_no_decode(struct pipe_screen *screen,
535 enum pipe_video_profile profile,
536 enum pipe_video_entrypoint entrypoint,
537 enum pipe_video_cap param)
538 {
539 switch (param) {
540 case PIPE_VIDEO_CAP_SUPPORTED:
541 return vl_profile_supported(screen, profile, entrypoint);
542 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
543 return 1;
544 case PIPE_VIDEO_CAP_MAX_WIDTH:
545 case PIPE_VIDEO_CAP_MAX_HEIGHT:
546 return vl_video_buffer_max_size(screen);
547 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
548 return PIPE_FORMAT_NV12;
549 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
550 return false;
551 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
552 return false;
553 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
554 return true;
555 case PIPE_VIDEO_CAP_MAX_LEVEL:
556 return vl_level_supported(screen, profile);
557 default:
558 return 0;
559 }
560 }
561
562 static int si_get_video_param(struct pipe_screen *screen,
563 enum pipe_video_profile profile,
564 enum pipe_video_entrypoint entrypoint,
565 enum pipe_video_cap param)
566 {
567 struct si_screen *sscreen = (struct si_screen *)screen;
568 enum pipe_video_format codec = u_reduce_video_profile(profile);
569
570 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
571 switch (param) {
572 case PIPE_VIDEO_CAP_SUPPORTED:
573 return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
574 (si_vce_is_fw_version_supported(sscreen) ||
575 sscreen->info.family == CHIP_RAVEN)) ||
576 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
577 (sscreen->info.family == CHIP_RAVEN ||
578 si_radeon_uvd_enc_supported(sscreen)));
579 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
580 return 1;
581 case PIPE_VIDEO_CAP_MAX_WIDTH:
582 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
583 case PIPE_VIDEO_CAP_MAX_HEIGHT:
584 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
585 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
586 return PIPE_FORMAT_NV12;
587 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
588 return false;
589 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
590 return false;
591 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
592 return true;
593 case PIPE_VIDEO_CAP_STACKED_FRAMES:
594 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
595 default:
596 return 0;
597 }
598 }
599
600 switch (param) {
601 case PIPE_VIDEO_CAP_SUPPORTED:
602 switch (codec) {
603 case PIPE_VIDEO_FORMAT_MPEG12:
604 return profile != PIPE_VIDEO_PROFILE_MPEG1;
605 case PIPE_VIDEO_FORMAT_MPEG4:
606 return 1;
607 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
608 if ((sscreen->info.family == CHIP_POLARIS10 ||
609 sscreen->info.family == CHIP_POLARIS11) &&
610 sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
611 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
612 return false;
613 }
614 return true;
615 case PIPE_VIDEO_FORMAT_VC1:
616 return true;
617 case PIPE_VIDEO_FORMAT_HEVC:
618 /* Carrizo only supports HEVC Main */
619 if (sscreen->info.family >= CHIP_STONEY)
620 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
621 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
622 else if (sscreen->info.family >= CHIP_CARRIZO)
623 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
624 return false;
625 case PIPE_VIDEO_FORMAT_JPEG:
626 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
627 return false;
628 if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
629 RVID_ERR("No MJPEG support for the kernel version\n");
630 return false;
631 }
632 return true;
633 case PIPE_VIDEO_FORMAT_VP9:
634 if (sscreen->info.family < CHIP_RAVEN)
635 return false;
636 return true;
637 default:
638 return false;
639 }
640 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
641 return 1;
642 case PIPE_VIDEO_CAP_MAX_WIDTH:
643 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
644 case PIPE_VIDEO_CAP_MAX_HEIGHT:
645 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
646 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
647 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
648 profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
649 return PIPE_FORMAT_P016;
650 else
651 return PIPE_FORMAT_NV12;
652
653 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
654 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
655 enum pipe_video_format format = u_reduce_video_profile(profile);
656
657 if (format == PIPE_VIDEO_FORMAT_HEVC)
658 return false; //The firmware doesn't support interlaced HEVC.
659 else if (format == PIPE_VIDEO_FORMAT_JPEG)
660 return false;
661 else if (format == PIPE_VIDEO_FORMAT_VP9)
662 return false;
663 return true;
664 }
665 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
666 return true;
667 case PIPE_VIDEO_CAP_MAX_LEVEL:
668 switch (profile) {
669 case PIPE_VIDEO_PROFILE_MPEG1:
670 return 0;
671 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
672 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
673 return 3;
674 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
675 return 3;
676 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
677 return 5;
678 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
679 return 1;
680 case PIPE_VIDEO_PROFILE_VC1_MAIN:
681 return 2;
682 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
683 return 4;
684 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
685 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
686 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
687 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
688 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
689 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
690 return 186;
691 default:
692 return 0;
693 }
694 default:
695 return 0;
696 }
697 }
698
699 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
700 enum pipe_format format,
701 enum pipe_video_profile profile,
702 enum pipe_video_entrypoint entrypoint)
703 {
704 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
705 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
706 return (format == PIPE_FORMAT_NV12) ||
707 (format == PIPE_FORMAT_P016);
708
709 /* we can only handle this one with UVD */
710 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
711 return format == PIPE_FORMAT_NV12;
712
713 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
714 }
715
716 static unsigned get_max_threads_per_block(struct si_screen *screen,
717 enum pipe_shader_ir ir_type)
718 {
719 if (ir_type == PIPE_SHADER_IR_NATIVE)
720 return 256;
721
722 /* Only 16 waves per thread-group on gfx9. */
723 if (screen->info.chip_class >= GFX9)
724 return 1024;
725
726 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
727 * round number.
728 */
729 return 2048;
730 }
731
732 static int si_get_compute_param(struct pipe_screen *screen,
733 enum pipe_shader_ir ir_type,
734 enum pipe_compute_cap param,
735 void *ret)
736 {
737 struct si_screen *sscreen = (struct si_screen *)screen;
738
739 //TODO: select these params by asic
740 switch (param) {
741 case PIPE_COMPUTE_CAP_IR_TARGET: {
742 const char *gpu, *triple;
743
744 triple = "amdgcn-mesa-mesa3d";
745 gpu = ac_get_llvm_processor_name(sscreen->info.family);
746 if (ret) {
747 sprintf(ret, "%s-%s", gpu, triple);
748 }
749 /* +2 for dash and terminating NIL byte */
750 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
751 }
752 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
753 if (ret) {
754 uint64_t *grid_dimension = ret;
755 grid_dimension[0] = 3;
756 }
757 return 1 * sizeof(uint64_t);
758
759 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
760 if (ret) {
761 uint64_t *grid_size = ret;
762 grid_size[0] = 65535;
763 grid_size[1] = 65535;
764 grid_size[2] = 65535;
765 }
766 return 3 * sizeof(uint64_t) ;
767
768 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
769 if (ret) {
770 uint64_t *block_size = ret;
771 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
772 block_size[0] = threads_per_block;
773 block_size[1] = threads_per_block;
774 block_size[2] = threads_per_block;
775 }
776 return 3 * sizeof(uint64_t);
777
778 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
779 if (ret) {
780 uint64_t *max_threads_per_block = ret;
781 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
782 }
783 return sizeof(uint64_t);
784 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
785 if (ret) {
786 uint32_t *address_bits = ret;
787 address_bits[0] = 64;
788 }
789 return 1 * sizeof(uint32_t);
790
791 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
792 if (ret) {
793 uint64_t *max_global_size = ret;
794 uint64_t max_mem_alloc_size;
795
796 si_get_compute_param(screen, ir_type,
797 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
798 &max_mem_alloc_size);
799
800 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
801 * 1/4 of the MAX_GLOBAL_SIZE. Since the
802 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
803 * make sure we never report more than
804 * 4 * MAX_MEM_ALLOC_SIZE.
805 */
806 *max_global_size = MIN2(4 * max_mem_alloc_size,
807 MAX2(sscreen->info.gart_size,
808 sscreen->info.vram_size));
809 }
810 return sizeof(uint64_t);
811
812 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
813 if (ret) {
814 uint64_t *max_local_size = ret;
815 /* Value reported by the closed source driver. */
816 *max_local_size = 32768;
817 }
818 return sizeof(uint64_t);
819
820 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
821 if (ret) {
822 uint64_t *max_input_size = ret;
823 /* Value reported by the closed source driver. */
824 *max_input_size = 1024;
825 }
826 return sizeof(uint64_t);
827
828 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
829 if (ret) {
830 uint64_t *max_mem_alloc_size = ret;
831
832 *max_mem_alloc_size = sscreen->info.max_alloc_size;
833 }
834 return sizeof(uint64_t);
835
836 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
837 if (ret) {
838 uint32_t *max_clock_frequency = ret;
839 *max_clock_frequency = sscreen->info.max_shader_clock;
840 }
841 return sizeof(uint32_t);
842
843 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
844 if (ret) {
845 uint32_t *max_compute_units = ret;
846 *max_compute_units = sscreen->info.num_good_compute_units;
847 }
848 return sizeof(uint32_t);
849
850 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
851 if (ret) {
852 uint32_t *images_supported = ret;
853 *images_supported = 0;
854 }
855 return sizeof(uint32_t);
856 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
857 break; /* unused */
858 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
859 if (ret) {
860 uint32_t *subgroup_size = ret;
861 *subgroup_size = 64;
862 }
863 return sizeof(uint32_t);
864 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
865 if (ret) {
866 uint64_t *max_variable_threads_per_block = ret;
867 if (ir_type == PIPE_SHADER_IR_NATIVE)
868 *max_variable_threads_per_block = 0;
869 else
870 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
871 }
872 return sizeof(uint64_t);
873 }
874
875 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
876 return 0;
877 }
878
879 static uint64_t si_get_timestamp(struct pipe_screen *screen)
880 {
881 struct si_screen *sscreen = (struct si_screen*)screen;
882
883 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
884 sscreen->info.clock_crystal_freq;
885 }
886
887 static void si_query_memory_info(struct pipe_screen *screen,
888 struct pipe_memory_info *info)
889 {
890 struct si_screen *sscreen = (struct si_screen*)screen;
891 struct radeon_winsys *ws = sscreen->ws;
892 unsigned vram_usage, gtt_usage;
893
894 info->total_device_memory = sscreen->info.vram_size / 1024;
895 info->total_staging_memory = sscreen->info.gart_size / 1024;
896
897 /* The real TTM memory usage is somewhat random, because:
898 *
899 * 1) TTM delays freeing memory, because it can only free it after
900 * fences expire.
901 *
902 * 2) The memory usage can be really low if big VRAM evictions are
903 * taking place, but the real usage is well above the size of VRAM.
904 *
905 * Instead, return statistics of this process.
906 */
907 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
908 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
909
910 info->avail_device_memory =
911 vram_usage <= info->total_device_memory ?
912 info->total_device_memory - vram_usage : 0;
913 info->avail_staging_memory =
914 gtt_usage <= info->total_staging_memory ?
915 info->total_staging_memory - gtt_usage : 0;
916
917 info->device_memory_evicted =
918 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
919
920 if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
921 info->nr_device_memory_evictions =
922 ws->query_value(ws, RADEON_NUM_EVICTIONS);
923 else
924 /* Just return the number of evicted 64KB pages. */
925 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
926 }
927
928 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
929 {
930 struct si_screen *sscreen = (struct si_screen*)pscreen;
931
932 return sscreen->disk_shader_cache;
933 }
934
935 static void si_init_renderer_string(struct si_screen *sscreen)
936 {
937 struct radeon_winsys *ws = sscreen->ws;
938 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
939 struct utsname uname_data;
940
941 const char *marketing_name = si_get_marketing_name(ws);
942
943 if (marketing_name) {
944 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
945 snprintf(second_name, sizeof(second_name), "%s, ",
946 sscreen->info.name);
947 } else {
948 snprintf(first_name, sizeof(first_name), "AMD %s",
949 sscreen->info.name);
950 }
951
952 if (uname(&uname_data) == 0)
953 snprintf(kernel_version, sizeof(kernel_version),
954 ", %s", uname_data.release);
955
956 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
957 "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
958 first_name, second_name, sscreen->info.drm_major,
959 sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
960 kernel_version,
961 (HAVE_LLVM >> 8) & 0xff,
962 HAVE_LLVM & 0xff,
963 MESA_LLVM_VERSION_PATCH);
964 }
965
966 void si_init_screen_get_functions(struct si_screen *sscreen)
967 {
968 sscreen->b.get_name = si_get_name;
969 sscreen->b.get_vendor = si_get_vendor;
970 sscreen->b.get_device_vendor = si_get_device_vendor;
971 sscreen->b.get_param = si_get_param;
972 sscreen->b.get_paramf = si_get_paramf;
973 sscreen->b.get_compute_param = si_get_compute_param;
974 sscreen->b.get_timestamp = si_get_timestamp;
975 sscreen->b.get_shader_param = si_get_shader_param;
976 sscreen->b.get_compiler_options = si_get_compiler_options;
977 sscreen->b.get_device_uuid = si_get_device_uuid;
978 sscreen->b.get_driver_uuid = si_get_driver_uuid;
979 sscreen->b.query_memory_info = si_query_memory_info;
980 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
981
982 if (sscreen->info.has_hw_decode) {
983 sscreen->b.get_video_param = si_get_video_param;
984 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
985 } else {
986 sscreen->b.get_video_param = si_get_video_param_no_decode;
987 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
988 }
989
990 si_init_renderer_string(sscreen);
991 }