src/gallium/drivers/radeonsi/si_gfx_cs.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_pipe.h"
  27
  28 #include "util/os_time.h"
  29
  30 /* initialize */
  31 void si_need_gfx_cs_space(struct si_context *ctx)
  32 {
  33         struct radeon_winsys_cs *cs = ctx->gfx_cs;
  34
  35         /* There is no need to flush the DMA IB here, because
  36          * r600_need_dma_space always flushes the GFX IB if there is
  37          * a conflict, which means any unflushed DMA commands automatically
  38          * precede the GFX IB (= they had no dependency on the GFX IB when
  39          * they were submitted).
  40          */
  41
  42         /* There are two memory usage counters in the winsys for all buffers
  43          * that have been added (cs_add_buffer) and two counters in the pipe
  44          * driver for those that haven't been added yet.
  45          */
  46         if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
  47                                                    ctx->vram, ctx->gtt))) {
  48                 ctx->gtt = 0;
  49                 ctx->vram = 0;
  50                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  51                 return;
  52         }
  53         ctx->gtt = 0;
  54         ctx->vram = 0;
  55
  56         /* If the IB is sufficiently large, don't count the space needed
  57          * and just flush if there is not enough space left.
  58          *
  59          * Also reserve space for stopping queries at the end of IB, because
  60          * the number of active queries is mostly unlimited.
  61          */
  62         unsigned need_dwords = 2048 + ctx->num_cs_dw_queries_suspend;
  63         if (!ctx->ws->cs_check_space(cs, need_dwords))
  64                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  65 }
  66
  67 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
  68                      struct pipe_fence_handle **fence)
  69 {
  70         struct radeon_winsys_cs *cs = ctx->gfx_cs;
  71         struct radeon_winsys *ws = ctx->ws;
  72
  73         if (ctx->gfx_flush_in_progress)
  74                 return;
  75
  76         if (!radeon_emitted(cs, ctx->initial_gfx_cs_size))
  77                 return;
  78
  79         if (si_check_device_reset(ctx))
  80                 return;
  81
  82         if (ctx->screen->debug_flags & DBG(CHECK_VM))
  83                 flags &= ~PIPE_FLUSH_ASYNC;
  84
  85         /* If the state tracker is flushing the GFX IB, si_flush_from_st is
  86          * responsible for flushing the DMA IB and merging the fences from both.
  87          * This code is only needed when the driver flushes the GFX IB
  88          * internally, and it never asks for a fence handle.
  89          */
  90         if (radeon_emitted(ctx->dma_cs, 0)) {
  91                 assert(fence == NULL); /* internal flushes only */
  92                 si_flush_dma_cs(ctx, flags, NULL);
  93         }
  94
  95         ctx->gfx_flush_in_progress = true;
  96
  97         if (!LIST_IS_EMPTY(&ctx->active_queries))
  98                 si_suspend_queries(ctx);
  99
 100         ctx->streamout.suspended = false;
 101         if (ctx->streamout.begin_emitted) {
 102                 si_emit_streamout_end(ctx);
 103                 ctx->streamout.suspended = true;
 104         }
 105
 106         ctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 107                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 108
 109         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 110         if (ctx->chip_class == VI && ctx->screen->info.drm_minor <= 1)
 111                 ctx->flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 112                                 SI_CONTEXT_INV_VMEM_L1;
 113
 114         /* Make sure CP DMA is idle at the end of IBs after L2 prefetches
 115          * because the kernel doesn't wait for it. */
 116         if (ctx->chip_class >= CIK)
 117                 si_cp_dma_wait_for_idle(ctx);
 118
 119         si_emit_cache_flush(ctx);
 120
 121         if (ctx->current_saved_cs) {
 122                 si_trace_emit(ctx);
 123                 si_log_hw_flush(ctx);
 124
 125                 /* Save the IB for debug contexts. */
 126                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 127                 ctx->current_saved_cs->flushed = true;
 128                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 129         }
 130
 131         /* Flush the CS. */
 132         ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
 133         if (fence)
 134                 ws->fence_reference(fence, ctx->last_gfx_fence);
 135
 136         /* This must be after cs_flush returns, since the context's API
 137          * thread can concurrently read this value in si_fence_finish. */
 138         ctx->num_gfx_cs_flushes++;
 139
 140         /* Check VM faults if needed. */
 141         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 142                 /* Use conservative timeout 800ms, after which we won't wait any
 143                  * longer and assume the GPU is hung.
 144                  */
 145                 ctx->ws->fence_wait(ctx->ws, ctx->last_gfx_fence, 800*1000*1000);
 146
 147                 si_check_vm_faults(ctx, &ctx->current_saved_cs->gfx, RING_GFX);
 148         }
 149
 150         if (ctx->current_saved_cs)
 151                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 152
 153         si_begin_new_gfx_cs(ctx);
 154         ctx->gfx_flush_in_progress = false;
 155 }
 156
 157 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 158 {
 159         static const uint32_t zeros[1];
 160         assert(!ctx->current_saved_cs);
 161
 162         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 163         if (!ctx->current_saved_cs)
 164                 return;
 165
 166         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 167
 168         ctx->current_saved_cs->trace_buf = (struct r600_resource*)
 169                                  pipe_buffer_create(ctx->b.screen, 0,
 170                                                     PIPE_USAGE_STAGING, 8);
 171         if (!ctx->current_saved_cs->trace_buf) {
 172                 free(ctx->current_saved_cs);
 173                 ctx->current_saved_cs = NULL;
 174                 return;
 175         }
 176
 177         pipe_buffer_write_nooverlap(&ctx->b, &ctx->current_saved_cs->trace_buf->b.b,
 178                                     0, sizeof(zeros), zeros);
 179         ctx->current_saved_cs->trace_id = 0;
 180
 181         si_trace_emit(ctx);
 182
 183         radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
 184                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 185 }
 186
 187 void si_begin_new_gfx_cs(struct si_context *ctx)
 188 {
 189         if (ctx->is_debug)
 190                 si_begin_gfx_cs_debug(ctx);
 191
 192         /* Flush read caches at the beginning of CS not flushed by the kernel. */
 193         if (ctx->chip_class >= CIK)
 194                 ctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
 195                                 SI_CONTEXT_INV_ICACHE;
 196
 197         ctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
 198
 199         /* set all valid group as dirty so they get reemited on
 200          * next draw command
 201          */
 202         si_pm4_reset_emitted(ctx);
 203
 204         /* The CS initialization should be emitted before everything else. */
 205         si_pm4_emit(ctx, ctx->init_config);
 206         if (ctx->init_config_gs_rings)
 207                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 208
 209         if (ctx->queued.named.ls)
 210                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 211         if (ctx->queued.named.hs)
 212                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 213         if (ctx->queued.named.es)
 214                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 215         if (ctx->queued.named.gs)
 216                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 217         if (ctx->queued.named.vs)
 218                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 219         if (ctx->queued.named.ps)
 220                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 221         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 222                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 223
 224         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 225         bool has_clear_state = ctx->screen->has_clear_state;
 226         if (has_clear_state) {
 227                 ctx->framebuffer.dirty_cbufs =
 228                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 229                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 230                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 231         } else {
 232                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 233                 ctx->framebuffer.dirty_zsbuf = true;
 234         }
 235         /* This should always be marked as dirty to set the framebuffer scissor
 236          * at least. */
 237         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 238
 239         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 240         /* CLEAR_STATE sets zeros. */
 241         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 242                 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 243         ctx->msaa_sample_locs.nr_samples = 0;
 244         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 245         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 246         /* CLEAR_STATE sets 0xffff. */
 247         if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
 248                 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 249         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 250         /* CLEAR_STATE sets zeros. */
 251         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 252                 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 253         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 254         if (ctx->chip_class >= GFX9)
 255                 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
 256         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 257         si_mark_atom_dirty(ctx, &ctx->spi_map);
 258         si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
 259         si_mark_atom_dirty(ctx, &ctx->render_cond_atom);
 260         si_all_descriptors_begin_new_cs(ctx);
 261         si_all_resident_buffers_begin_new_cs(ctx);
 262
 263         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 264         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 265         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 266         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 267         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 268
 269         si_mark_atom_dirty(ctx, &ctx->scratch_state);
 270         if (ctx->scratch_buffer) {
 271                 si_context_add_resource_size(ctx, &ctx->scratch_buffer->b.b);
 272         }
 273
 274         if (ctx->streamout.suspended) {
 275                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 276                 si_streamout_buffers_dirty(ctx);
 277         }
 278
 279         if (!LIST_IS_EMPTY(&ctx->active_queries))
 280                 si_resume_queries(ctx);
 281
 282         assert(!ctx->gfx_cs->prev_dw);
 283         ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
 284
 285         /* Invalidate various draw states so that they are emitted before
 286          * the first draw call. */
 287         si_invalidate_draw_sh_constants(ctx);
 288         ctx->last_index_size = -1;
 289         ctx->last_primitive_restart_en = -1;
 290         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 291         ctx->last_gs_out_prim = -1;
 292         ctx->last_prim = -1;
 293         ctx->last_multi_vgt_param = -1;
 294         ctx->last_rast_prim = -1;
 295         ctx->last_sc_line_stipple = ~0;
 296         ctx->last_vs_state = ~0;
 297         ctx->last_ls = NULL;
 298         ctx->last_tcs = NULL;
 299         ctx->last_tes_sh_base = -1;
 300         ctx->last_num_tcs_input_cp = -1;
 301
 302         ctx->cs_shader_state.initialized = false;
 303 }